commit 480d33b8a21182ad0be54e6e1f0dd01accc698f3
author Chia-I Wu <olvaffe@gmail.com> Fri Aug 29 10:26:14 2014 +0800
committer Chia-I Wu <olvaffe@gmail.com> Fri Aug 29 10:28:50 2014 +0800
tree a7c33df02a8027eec1d6a26ab674763a4ae2eca3
parent ef12c1ae1c4096847e879bf4515f0308fbe5de7a

intel: fix assertion failures on Haswell

icd/intel/pipeline.c

diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c
index 22071b6..06d765e 100644
--- a/icd/intel/pipeline.c
+++ b/icd/intel/pipeline.c
@@ -487,7 +487,7 @@
     uint32_t *dw;
     int end;
 
-    INTEL_GPU_ASSERT(builder->gpu, 7, 7);
+    INTEL_GPU_ASSERT(builder->gpu, 7, 7.5);
 
     /*
     * From the Ivy Bridge PRM, volume 2 part 1, page 68:
@@ -677,7 +677,7 @@
     const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
     uint32_t *dw;
 
-    INTEL_GPU_ASSERT(builder->gpu, 7, 7);
+    INTEL_GPU_ASSERT(builder->gpu, 7, 7.5);
 
     dw = pipeline_cmd_ptr(p, cmd_len);
     dw[0] = dw0;
@@ -712,7 +712,7 @@
     const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (cmd_len - 2);
     uint32_t *dw;
 
-    INTEL_GPU_ASSERT(builder->gpu, 7, 7);
+    INTEL_GPU_ASSERT(builder->gpu, 7, 7.5);
 
     dw = pipeline_cmd_ptr(p, cmd_len);
     dw[0] = dw0;
@@ -728,7 +728,7 @@
     const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
     uint32_t *dw;
 
-    INTEL_GPU_ASSERT(builder->gpu, 7, 7);
+    INTEL_GPU_ASSERT(builder->gpu, 7, 7.5);
 
     dw = pipeline_cmd_ptr(p, cmd_len);
     dw[0] = dw0;