intel: add support for MRT
Scan XGL_PIPELINE_CB_STATE to know the number of attachments bound. Update
emit_binding_table() to emit null SURFACE_STATEs for holes.
Change color attachments indexing to be cmd->bind.att.rt[slot->u.index]
instead of cmd->bind.att.rt[i]. While slot->u.index is equal to i for RTs,
the latter is semantically wrong.
diff --git a/icd/intel/pipeline_shader.c b/icd/intel/pipeline_shader.c
index 41a39b2..329bdba 100644
--- a/icd/intel/pipeline_shader.c
+++ b/icd/intel/pipeline_shader.c
@@ -339,12 +339,34 @@
return XGL_SUCCESS;
}
+static int pipeline_get_last_color_attachment(const struct intel_pipeline *pipeline,
+ const struct intel_pipeline_create_info *info)
+{
+ int idx;
+
+ for (idx = ARRAY_SIZE(info->cb.attachment) - 1; idx >= 0; idx--) {
+ const XGL_PIPELINE_CB_ATTACHMENT_STATE *att =
+ &info->cb.attachment[idx];
+
+ if (!icd_format_is_undef(att->format))
+ break;
+ }
+
+ return idx;
+}
+
static XGL_RESULT pipeline_build_fs(struct intel_pipeline *pipeline,
const struct intel_pipeline_create_info *info)
{
struct intel_pipeline_shader *fs = &pipeline->fs;
+ int rt_count;
XGL_RESULT ret;
+ rt_count = pipeline_get_last_color_attachment(pipeline, info) + 1;
+ /* at least one NULL RT */
+ if (rt_count <= 0)
+ rt_count = 1;
+
assert(!info->fs.linkConstBufferCount);
// Right here, lower the IR to ISA using NOS
@@ -354,10 +376,9 @@
if (ret != XGL_SUCCESS)
return ret;
- /* assuming one RT; need to parse the shader */
fs->rmap = rmap_create(pipeline->dev,
&info->fs.descriptorSetMapping[0],
- &info->fs.dynamicMemoryViewMapping, 1);
+ &info->fs.dynamicMemoryViewMapping, rt_count);
if (!fs->rmap) {
icd_free(fs->pCode);
return XGL_ERROR_OUT_OF_MEMORY;