commit 97aa4deab1fad7cbc3fae856512c7f9ac2c29eac
author Chia-I Wu <olv@lunarg.com> Thu Mar 05 15:43:16 2015 -0700
committer Chia-I Wu <olv@lunarg.com> Fri Mar 06 11:22:24 2015 -0700
tree 0c027df43b46ddfce2b8824666e4e81fcd765c56
parent f81ca1d9dd32ec1c04c16b39627c7f58e8ba6db0

intel: update genhw headers

Lots of renames and Gen8 support.  Changes verified by "gcc -E" and diff to
have some confidence that I did not mess up.

icd/intel/view.c

diff --git a/icd/intel/view.c b/icd/intel/view.c
index 9593e95..cebbcf9 100644
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -187,7 +187,7 @@
            pitch;
 
    dw[4] = 0;
-   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT;
+   dw[5] = GEN7_MOCS_L3_WB << GEN7_SURFACE_DW5_MOCS__SHIFT;
 
    dw[6] = 0;
    dw[7] = 0;
@@ -431,7 +431,7 @@
    else
       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
 
-   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT |
+   dw[5] = GEN7_MOCS_L3_WB << GEN7_SURFACE_DW5_MOCS__SHIFT |
            (first_level) << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
            lod;
 
@@ -979,7 +979,7 @@
 
       dw4 = (info.depth - 1) << 21 |
             info.first_layer << 10 |
-            GEN7_MOCS_L3_ON;
+            GEN7_MOCS_L3_WB;
 
       dw5 = 0;
 
@@ -1028,7 +1028,7 @@
       dw[7] = img->s8_offset;
 
       if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
-         dw[6] |= GEN7_MOCS_L3_ON << GEN6_STENCIL_DW1_MOCS__SHIFT;
+         dw[6] |= GEN7_MOCS_L3_WB << GEN6_STENCIL_DW1_MOCS__SHIFT;
       if (intel_gpu_gen(gpu) >= INTEL_GEN(7.5))
          dw[6] |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
    }
@@ -1043,7 +1043,7 @@
       dw[9] = img->aux_offset;
 
       if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
-         dw[8] |= GEN7_MOCS_L3_ON << GEN6_HIZ_DW1_MOCS__SHIFT;
+         dw[8] |= GEN7_MOCS_L3_WB << GEN6_HIZ_DW1_MOCS__SHIFT;
    }
    else {
       dw[8] = 0;