commit 9e81ebbd16f67780dff31214969fb0cecd4af098
author Chia-I Wu <olv@lunarg.com> Thu Jul 09 10:16:34 2015 +0800
committer Courtney Goeltzenleuchter <courtney@LunarG.com> Fri Jul 17 10:05:17 2015 -0600
tree a36ca89321bd69cec14d594e72a29dc2eb3db46c
parent 337d70a6052d6543e43fcf5a48b0cc4fe8447d89

intel: get depth/stencil format from VkRenderPassCreateInfo

The same info will be removed from VkPipelineDsStateCreateInfo after an
upcoming header change.

Fix bugs in tests.

icd/intel/cmd_pipeline.c

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 19d844d..6d1b0f5 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -476,6 +476,7 @@
                                       uint32_t body[6])
 {
     const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
+    const struct intel_render_pass *rp = cmd->bind.render_pass;
     const struct intel_dynamic_rs *raster = cmd->bind.state.raster;
     uint32_t dw1, dw2, dw3;
 
@@ -491,7 +492,7 @@
     if (cmd_gen(cmd) >= INTEL_GEN(7)) {
         int format;
 
-        switch (pipeline->db_format) {
+        switch (rp->depthStencilFormat) {
         case VK_FORMAT_D16_UNORM:
             format = GEN6_ZFORMAT_D16_UNORM;
             break;