vulkan: Consistent naming scheme for resources in XGL

Bug 13230
header: 0.78.0
includes review feedback.

v2: replace VK_FORMAT_IMAGE_COPY_BIT by VK_FORMAT_COLOR_ATTACHMENT_BIT for now
    (olv)
diff --git a/icd/intel/buf.c b/icd/intel/buf.c
index b670b7c..291e298 100644
--- a/icd/intel/buf.c
+++ b/icd/intel/buf.c
@@ -60,8 +60,10 @@
              *      bytes added beyond that to account for the L1 cache line."
              */
             mem_req->size = buf->size;
-            if (buf->usage & VK_BUFFER_USAGE_SHADER_ACCESS_READ_BIT)
+            if (buf->usage & (VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT |
+                             VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT)) {
                 mem_req->size = u_align(mem_req->size, 256) + 16;
+            }
 
             mem_req->alignment = 4096;
             mem_req->memType = VK_MEMORY_TYPE_BUFFER;
diff --git a/icd/intel/cmd_barrier.c b/icd/intel/cmd_barrier.c
index e1eb1e1..93f7d33 100644
--- a/icd/intel/cmd_barrier.c
+++ b/icd/intel/cmd_barrier.c
@@ -244,7 +244,7 @@
     }
 
     /* CPU write is cache coherent, so VK_MEMORY_OUTPUT_CPU_WRITE_BIT needs no flush. */
-    /* Meta handles flushes, so VK_MEMORY_OUTPUT_COPY_BIT needs no flush. */
+    /* Meta handles flushes, so VK_MEMORY_OUTPUT_TRANSFER_BIT needs no flush. */
 
     if (input_mask & (VK_MEMORY_INPUT_SHADER_READ_BIT | VK_MEMORY_INPUT_UNIFORM_READ_BIT)) {
         flush_flags |= GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
@@ -264,7 +264,7 @@
      * VK_MEMORY_INPUT_INDEX_FETCH_BIT
      * VK_MEMORY_INPUT_COLOR_ATTACHMENT_BIT
      * VK_MEMORY_INPUT_DEPTH_STENCIL_ATTACHMENT_BIT
-     * VK_MEMORY_INPUT_COPY_BIT
+     * VK_MEMORY_INPUT_TRANSFER_BIT
      */
 
     cmd_batch_flush(cmd, flush_flags);
diff --git a/icd/intel/cmd_meta.c b/icd/intel/cmd_meta.c
index 4037585..f1b362e 100644
--- a/icd/intel/cmd_meta.c
+++ b/icd/intel/cmd_meta.c
@@ -43,7 +43,7 @@
     memset(&info, 0, sizeof(info));
     info.sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO;
     info.buffer = buf;
-    info.viewType = VK_BUFFER_VIEW_TYPED;
+    info.viewType = VK_BUFFER_VIEW_FORMATTED;
     info.format = format;
     info.range = range;
 
diff --git a/icd/intel/desc.c b/icd/intel/desc.c
index d599d96..66a2ea7 100644
--- a/icd/intel/desc.c
+++ b/icd/intel/desc.c
@@ -180,18 +180,18 @@
     case VK_DESCRIPTOR_TYPE_SAMPLER:
         sampler_size = region->sampler_desc_size;
         break;
-    case VK_DESCRIPTOR_TYPE_SAMPLER_TEXTURE:
+    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
         surface_size = region->surface_desc_size;
         sampler_size = region->sampler_desc_size;
         break;
-    case VK_DESCRIPTOR_TYPE_TEXTURE:
-    case VK_DESCRIPTOR_TYPE_TEXTURE_BUFFER:
-    case VK_DESCRIPTOR_TYPE_IMAGE:
-    case VK_DESCRIPTOR_TYPE_IMAGE_BUFFER:
+    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
+    case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
+    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
+    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
     case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
-    case VK_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER:
+    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
     case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
-    case VK_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
+    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
         surface_size = region->surface_desc_size;
         break;
     default:
@@ -559,7 +559,7 @@
     const struct intel_desc_layout_binding *binding;
     uint32_t i;
 
-    if (!desc_iter_init_for_update(&iter, set, VK_DESCRIPTOR_TYPE_SAMPLER_TEXTURE,
+    if (!desc_iter_init_for_update(&iter, set, VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
                 update->binding, update->arrayIndex))
         return;
 
@@ -667,7 +667,7 @@
     uint32_t i;
 
     /* disallow combined sampler textures */
-    if (update->descriptorType == VK_DESCRIPTOR_TYPE_SAMPLER_TEXTURE)
+    if (update->descriptorType == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
         return;
 
     if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
@@ -726,7 +726,7 @@
 
         switch (lb->descriptorType) {
         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
-        case VK_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
+        case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
             layout->dynamic_desc_count += lb->count;
             break;
         default:
diff --git a/icd/intel/format.c b/icd/intel/format.c
index 032cdd2..9f40cf3 100644
--- a/icd/intel/format.c
+++ b/icd/intel/format.c
@@ -577,7 +577,7 @@
     vf = (fmt < ARRAY_SIZE(intel_vf_caps)) ?  &intel_vf_caps[fmt] : NULL;
     dp = (fmt < ARRAY_SIZE(intel_dp_caps)) ?  &intel_dp_caps[fmt] : NULL;
 
-    features = VK_FORMAT_MEMORY_SHADER_ACCESS_BIT;
+    features = VK_FORMAT_STORAGE_IMAGE_BIT;
 
 #define TEST(dev, func, cap) ((func) && (func)->cap && \
         intel_gpu_gen((dev)->gpu) >= (func)->cap)
@@ -588,20 +588,20 @@
     if (TEST(dev, sampler, sampling)) {
         if (icd_format_is_int(format) ||
             TEST(dev, sampler, filtering))
-            features |= VK_FORMAT_IMAGE_SHADER_READ_BIT;
+            features |= VK_FORMAT_SAMPLED_IMAGE_BIT;
     }
 
     if (TEST(dev, dp, typed_write))
-        features |= VK_FORMAT_IMAGE_SHADER_WRITE_BIT;
+        features |= VK_FORMAT_SAMPLED_IMAGE_BIT;
 
     if (TEST(dev, dp, rt_write)) {
-        features |= VK_FORMAT_COLOR_ATTACHMENT_WRITE_BIT;
+        features |= VK_FORMAT_COLOR_ATTACHMENT_BIT;
 
         if (TEST(dev, dp, rt_write_blending))
             features |= VK_FORMAT_COLOR_ATTACHMENT_BLEND_BIT;
 
-        if (features & VK_FORMAT_IMAGE_SHADER_READ_BIT) {
-            features |= VK_FORMAT_IMAGE_COPY_BIT |
+        if (features & VK_FORMAT_SAMPLED_IMAGE_BIT) {
+            features |= VK_FORMAT_SAMPLED_IMAGE_BIT |
                         VK_FORMAT_CONVERSION_BIT;
         }
     }
@@ -619,18 +619,18 @@
 
     switch (format) {
     case VK_FMT_S8_UINT:
-        features = VK_FORMAT_STENCIL_ATTACHMENT_BIT;;
+        features = VK_FORMAT_DEPTH_STENCIL_ATTACHMENT_BIT;;
         break;
     case VK_FMT_D16_UNORM:
     case VK_FMT_D24_UNORM:
     case VK_FMT_D32_SFLOAT:
-        features = VK_FORMAT_DEPTH_ATTACHMENT_BIT;
+        features = VK_FORMAT_DEPTH_STENCIL_ATTACHMENT_BIT;
         break;
     case VK_FMT_D16_UNORM_S8_UINT:
     case VK_FMT_D24_UNORM_S8_UINT:
     case VK_FMT_D32_SFLOAT_S8_UINT:
-        features = VK_FORMAT_DEPTH_ATTACHMENT_BIT |
-                   VK_FORMAT_STENCIL_ATTACHMENT_BIT;
+        features = VK_FORMAT_DEPTH_STENCIL_ATTACHMENT_BIT |
+                   VK_FORMAT_DEPTH_STENCIL_ATTACHMENT_BIT;
         break;
     default:
         features = 0;
@@ -644,7 +644,7 @@
                                                VkFormat format)
 {
     return (format == VK_FMT_UNDEFINED) ?
-        VK_FORMAT_MEMORY_SHADER_ACCESS_BIT : 0;
+        VK_FORMAT_STORAGE_IMAGE_BIT : 0;
 }
 
 static void intel_format_get_props(const struct intel_dev *dev,
diff --git a/icd/intel/img.c b/icd/intel/img.c
index 8850b01..76e499a 100644
--- a/icd/intel/img.c
+++ b/icd/intel/img.c
@@ -155,7 +155,7 @@
         s8_info = *info;
         s8_info.format = VK_FMT_S8_UINT;
         /* no stencil texturing */
-        s8_info.usage &= ~VK_IMAGE_USAGE_SHADER_ACCESS_READ_BIT;
+        s8_info.usage &= ~VK_IMAGE_USAGE_SAMPLED_BIT;
         assert(icd_format_is_ds(info->format));
 
         intel_layout_init(img->s8_layout, dev, &s8_info, scanout);
diff --git a/icd/intel/layout.c b/icd/intel/layout.c
index 67df8a9..dbc5e14 100644
--- a/icd/intel/layout.c
+++ b/icd/intel/layout.c
@@ -534,7 +534,7 @@
       valid_tilings &= ~LAYOUT_TILING_W;
    }
 
-   if (info->usage & VK_IMAGE_USAGE_SHADER_ACCESS_READ_BIT) {
+   if (info->usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
       if (intel_gpu_gen(params->gpu) < INTEL_GEN(8))
          valid_tilings &= ~LAYOUT_TILING_W;
    }
@@ -561,7 +561,7 @@
       preferred_tilings &= ~LAYOUT_TILING_W;
 
    if (info->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
-                      VK_IMAGE_USAGE_SHADER_ACCESS_READ_BIT)) {
+                      VK_IMAGE_USAGE_SAMPLED_BIT)) {
       /*
        * heuristically set a minimum width/height for enabling tiling
        */
@@ -844,7 +844,7 @@
     *      padding purposes. The value of 4 for j still applies for mip level
     *      alignment and QPitch calculation."
     */
-   if (info->usage & VK_IMAGE_USAGE_SHADER_ACCESS_READ_BIT) {
+   if (info->usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
       if (align_w < layout->align_i)
           align_w = layout->align_i;
       if (align_h < layout->align_j)
@@ -911,7 +911,7 @@
        *      required above."
        */
       if (intel_gpu_gen(params->gpu) >= INTEL_GEN(7.5) &&
-          (params->info->usage & VK_IMAGE_USAGE_SHADER_ACCESS_READ_BIT) &&
+          (params->info->usage & VK_IMAGE_USAGE_SAMPLED_BIT) &&
           layout->tiling == GEN6_TILING_NONE)
          h += (64 + layout->bo_stride - 1) / layout->bo_stride;
 
diff --git a/icd/intel/view.c b/icd/intel/view.c
index f74ae20..ea6dc14 100644
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -1070,9 +1070,9 @@
                                  struct intel_buf_view **view_ret)
 {
     struct intel_buf *buf = intel_buf(info->buffer);
-    const bool will_write = (buf->usage |
-            (VK_BUFFER_USAGE_SHADER_ACCESS_WRITE_BIT &
-             VK_BUFFER_USAGE_SHADER_ACCESS_ATOMIC_BIT));
+    /* TODO: Is transfer destination the only shader write operation? */
+    const bool will_write = (buf->usage & (VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT |
+                             VK_BUFFER_USAGE_STORAGE_BUFFER_BIT));
     VkFormat format;
     VkGpuSize stride;
     uint32_t *cmd;