commit b368698d94b84a963094895bbeddbeeee3e6520f
author Chia-I Wu <olv@lunarg.com> Fri Feb 27 09:51:16 2015 -0700
committer Chia-I Wu <olv@lunarg.com> Fri Feb 27 12:31:17 2015 -0700
tree 9c10d57f85ae8cbdc82491e3f5984fd78baaa284
parent 1b293966226bc7fb6a1e31c3c74a9e461598efe5

intel: enable L3 cache

Set GEN7_MOCS_L3_ON everywhere.

icd/intel/view.c

diff --git a/icd/intel/view.c b/icd/intel/view.c
index 8f746ba..9fda59b 100644
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -187,7 +187,7 @@
            pitch;
 
    dw[4] = 0;
-   dw[5] = 0;
+   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT;
 
    dw[6] = 0;
    dw[7] = 0;
@@ -431,7 +431,8 @@
    else
       dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1;
 
-   dw[5] = (first_level) << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
+   dw[5] = GEN7_MOCS_L3_ON << GEN7_SURFACE_DW5_MOCS__SHIFT |
+           (first_level) << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
            lod;
 
    dw[6] = 0;
@@ -977,7 +978,8 @@
             info.lod;
 
       dw4 = (info.depth - 1) << 21 |
-            info.first_layer << 10;
+            info.first_layer << 10 |
+            GEN7_MOCS_L3_ON;
 
       dw5 = 0;
 
@@ -1025,6 +1027,8 @@
       dw[6] = info.stencil.stride - 1;
       dw[7] = img->s8_offset;
 
+      if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
+         dw[6] |= GEN7_MOCS_L3_ON << GEN6_STENCIL_DW1_MOCS__SHIFT;
       if (intel_gpu_gen(gpu) >= INTEL_GEN(7.5))
          dw[6] |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
    }
@@ -1037,6 +1041,9 @@
    if (info.hiz.stride) {
       dw[8] = info.hiz.stride - 1;
       dw[9] = img->aux_offset;
+
+      if (intel_gpu_gen(gpu) >= INTEL_GEN(7))
+         dw[8] |= GEN7_MOCS_L3_ON << GEN6_HIZ_DW1_MOCS__SHIFT;
    }
    else {
       dw[8] = 0;