intel: Remove scissor enable and scissor count
bug #12925
header version: r29511
Remove separate scissor enable and scissor count. Scissor always
enabled and must always provide scissor rect for every viewport.
diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 2e400de..6e211a2 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -410,6 +410,9 @@
dw2 = pipeline->cmd_sf_cull;
+ /* Scissor is always enabled */
+ dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
+
if (pipeline->sample_count > 1) {
dw2 |= 128 << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
GEN7_SF_DW2_MSRASTMODE_ON_PATTERN;
@@ -418,9 +421,6 @@
GEN7_SF_DW2_MSRASTMODE_OFF_PIXEL;
}
- if (pipeline->scissor_enable)
- dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
-
/* in U8.3 */
point_width = (int) (raster->rs_info.pointSize * 8.0f + 0.5f);
point_width = U_CLAMP(point_width, 1, 2047);
@@ -1307,8 +1307,7 @@
return;
assert(viewport->cmd_len == (8 + 4 + 2) *
- viewport->viewport_count + (viewport->has_scissor_rects) ?
- (viewport->viewport_count * 2) : 0);
+ /* viewports */ viewport->viewport_count + (/* scissor */ viewport->viewport_count * 2));
sf_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SF_VIEWPORT,
GEN6_ALIGNMENT_SF_VIEWPORT, 8 * viewport->viewport_count,
@@ -1322,13 +1321,9 @@
GEN6_ALIGNMENT_SF_VIEWPORT, 2 * viewport->viewport_count,
&viewport->cmd[viewport->cmd_cc_pos]);
- if (viewport->has_scissor_rects) {
- scissor_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
- GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
- &viewport->cmd[viewport->cmd_scissor_rect_pos]);
- } else {
- scissor_offset = 0;
- }
+ scissor_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
+ GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
+ &viewport->cmd[viewport->cmd_scissor_rect_pos]);
gen6_3DSTATE_VIEWPORT_STATE_POINTERS(cmd,
clip_offset, sf_offset, cc_offset);
@@ -1379,14 +1374,12 @@
static void gen7_viewport_states(struct intel_cmd *cmd)
{
const struct intel_dynamic_vp *viewport = cmd->bind.state.viewport;
- const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
uint32_t offset;
if (!viewport)
return;
- assert(viewport->cmd_len == (16 + 2 + 2 * pipeline->scissor_enable) *
- viewport->viewport_count);
+ assert(viewport->cmd_len == (16 + 2 + 2) * viewport->viewport_count);
offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SF_VIEWPORT,
GEN7_ALIGNMENT_SF_CLIP_VIEWPORT, 16 * viewport->viewport_count,
@@ -1402,14 +1395,12 @@
GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
offset);
- if (pipeline->scissor_enable) {
- offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
- GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
- &viewport->cmd[viewport->cmd_scissor_rect_pos]);
- gen7_3dstate_pointer(cmd,
- GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS,
- offset);
- }
+ offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
+ GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
+ &viewport->cmd[viewport->cmd_scissor_rect_pos]);
+ gen7_3dstate_pointer(cmd,
+ GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS,
+ offset);
}
static void gen6_pcb(struct intel_cmd *cmd, int subop,
diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c
index 184989e..95de6c0 100644
--- a/icd/intel/pipeline.c
+++ b/icd/intel/pipeline.c
@@ -1262,8 +1262,6 @@
pipeline->tess_state = info->tess;
}
- pipeline->scissor_enable = info->vp.scissorEnable;
-
return ret;
}
diff --git a/icd/intel/pipeline.h b/icd/intel/pipeline.h
index b1f4c14..5983f9c 100644
--- a/icd/intel/pipeline.h
+++ b/icd/intel/pipeline.h
@@ -194,7 +194,6 @@
// XGL_PIPELINE_RS_STATE_CREATE_INFO rs_state;
bool depthClipEnable;
bool rasterizerDiscardEnable;
- bool scissor_enable;
XGL_PIPELINE_TESS_STATE_CREATE_INFO tess_state;
diff --git a/icd/intel/state.c b/icd/intel/state.c
index c40211b..5fe0cd3 100644
--- a/icd/intel/state.c
+++ b/icd/intel/state.c
@@ -96,31 +96,26 @@
{
INTEL_GPU_ASSERT(gpu, 6, 7.5);
- state->viewport_count = info->viewportCount;
- state->has_scissor_rects = (info->scissorCount > 0);
+ state->viewport_count = info->viewportAndScissorCount;
- assert(info->viewportCount < INTEL_MAX_RENDER_TARGETS);
- assert(info->scissorCount < INTEL_MAX_RENDER_TARGETS);
- assert(!state->has_scissor_rects || info->scissorCount == info->viewportCount);
+ assert(info->viewportAndScissorCount < INTEL_MAX_RENDER_TARGETS);
if (intel_gpu_gen(gpu) >= INTEL_GEN(7)) {
- state->cmd_len = 16 * info->viewportCount;
+ state->cmd_len = 16 * info->viewportAndScissorCount;
state->cmd_clip_pos = 8;
} else {
- state->cmd_len = 8 * info->viewportCount;
+ state->cmd_len = 8 * info->viewportAndScissorCount;
state->cmd_clip_pos = state->cmd_len;
- state->cmd_len += 4 * info->viewportCount;
+ state->cmd_len += 4 * info->viewportAndScissorCount;
}
state->cmd_cc_pos = state->cmd_len;
- state->cmd_len += 2 * info->viewportCount;
+ state->cmd_len += 2 * info->viewportAndScissorCount;
- if (state->has_scissor_rects) {
- state->cmd_scissor_rect_pos = state->cmd_len;
- state->cmd_len += 2 * info->viewportCount;
- }
+ state->cmd_scissor_rect_pos = state->cmd_len;
+ state->cmd_len += 2 * info->viewportAndScissorCount;
state->cmd = icd_alloc(sizeof(uint32_t) * state->cmd_len,
0, XGL_SYSTEM_ALLOC_INTERNAL);
@@ -152,7 +147,7 @@
cc_viewport = state->cmd + state->cmd_cc_pos;
scissor_rect = state->cmd + state->cmd_scissor_rect_pos;
- for (i = 0; i < info->viewportCount; i++) {
+ for (i = 0; i < info->viewportAndScissorCount; i++) {
const XGL_VIEWPORT *viewport = &info->pViewports[i];
uint32_t *dw = NULL;
float translate[3], scale[3];
@@ -195,7 +190,7 @@
cc_viewport += 2;
}
- for (i = 0; i < info->scissorCount; i++) {
+ for (i = 0; i < info->viewportAndScissorCount; i++) {
const XGL_RECT *scissor = &info->pScissors[i];
/* SCISSOR_RECT */
int16_t max_x, max_y;
diff --git a/icd/intel/state.h b/icd/intel/state.h
index e41f9dd..67e3410 100644
--- a/icd/intel/state.h
+++ b/icd/intel/state.h
@@ -37,7 +37,6 @@
struct intel_obj obj;
uint32_t viewport_count;
- bool has_scissor_rects;
/* SF_CLIP_VIEWPORTs, CC_VIEWPORTs, and SCISSOR_RECTs */
uint32_t *cmd;
uint32_t cmd_len;