commit c8f54f7bf75d8a8da5c5747c7eb741f2b977a80a
author Courtney Goeltzenleuchter <courtney@LunarG.com> Thu Oct 15 17:59:39 2015 -0600
committer Courtney Goeltzenleuchter <courtney@LunarG.com> Fri Oct 23 17:31:14 2015 -0600
tree 3188bcb41c87fdefab1b5c0007ef1b05deb8ad05
parent de94316d3ee4158a072c4bb966128511fa567ff8

bug-14737: Move alphaToCoverageEnable to MultisampleStateCreateInfo

icd/intel/cmd_pipeline.c

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index 89b48df..206a03e 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -665,7 +665,7 @@
         dw5 |= GEN6_PS_DISPATCH_16 << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
 
     if (fs->uses & INTEL_SHADER_USE_KILL ||
-        pipeline->cb_state.alphaToCoverageEnable)
+        pipeline->alphaToCoverageEnable)
         dw5 |= GEN6_WM_DW5_PS_KILL_PIXEL;
 
     if (fs->computed_depth_mode)
@@ -727,7 +727,7 @@
           GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
 
     if (fs->uses & INTEL_SHADER_USE_KILL ||
-        pipeline->cb_state.alphaToCoverageEnable)
+        pipeline->alphaToCoverageEnable)
         dw1 |= GEN7_WM_DW1_PS_KILL_PIXEL;
 
     dw1 |= fs->computed_depth_mode << GEN7_WM_DW1_PSCDEPTH__SHIFT;

icd/intel/pipeline.c

diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c
index 4105c26..e77ac8f 100644
--- a/icd/intel/pipeline.c
+++ b/icd/intel/pipeline.c
@@ -958,6 +958,8 @@
 
     pipeline->sample_count = (info->ms.rasterSamples <= 1) ? 1 : info->ms.rasterSamples;
 
+    pipeline->alphaToCoverageEnable = info->ms.alphaToCoverageEnable;
+
     /* 3DSTATE_SAMPLE_MASK */
     cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
     cmd_len = 2;

icd/intel/pipeline.h

diff --git a/icd/intel/pipeline.h b/icd/intel/pipeline.h
index 416ba2c..00bb7a7 100644
--- a/icd/intel/pipeline.h
+++ b/icd/intel/pipeline.h
@@ -208,6 +208,8 @@
     bool rasterizerDiscardEnable;
     bool depthBiasEnable;
 
+    bool alphaToCoverageEnable;
+
     VkPipelineTessellationStateCreateInfo tess_state;
 
     uint32_t active_shaders;