commit cd83cf1c3c6519f9adbe1a083aaeafefd9148621
author Chia-I Wu <olvaffe@gmail.com> Sat Aug 23 17:26:08 2014 +0800
committer Chia-I Wu <olvaffe@gmail.com> Sat Aug 23 17:50:19 2014 +0800
tree c6a840fc326eaee89e777ecc0f4a1546297ea9e3
parent ed83387423fe5b04bb3bb1f12365a3a72ce37713

intel: export the length of SURFACE_STATE

6 on GEN6 and 8 on GEN7+.

icd/intel/view.c

diff --git a/icd/intel/view.c b/icd/intel/view.c
index 960e868..da8f231 100644
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -1020,10 +1020,13 @@
 void intel_null_view_init(struct intel_null_view *view,
                           struct intel_dev *dev)
 {
-    if (intel_gpu_gen(dev->gpu) >= INTEL_GEN(7))
+    if (intel_gpu_gen(dev->gpu) >= INTEL_GEN(7)) {
         surface_state_null_gen7(dev->gpu, view->cmd);
-    else
+        view->cmd_len = 8;
+    } else {
         surface_state_null_gen6(dev->gpu, view->cmd);
+        view->cmd_len = 6;
+    }
 }
 
 void intel_mem_view_init(struct intel_mem_view *view,
@@ -1050,10 +1053,12 @@
         surface_state_buf_gen7(dev->gpu, info->offset,
                 info->range, info->stride, info->format,
                 will_write, will_write, view->cmd);
+        view->cmd_len = 8;
     } else {
         surface_state_buf_gen6(dev->gpu, info->offset,
                 info->range, info->stride, info->format,
                 will_write, will_write, view->cmd);
+        view->cmd_len = 6;
     }
 }
 
@@ -1088,12 +1093,14 @@
                 info->subresourceRange.mipLevels,
                 info->subresourceRange.baseArraySlice,
                 info->subresourceRange.arraySize, false, view->cmd);
+        view->cmd_len = 8;
     } else {
         surface_state_tex_gen6(dev->gpu, img, info->viewType, info->format,
                 info->subresourceRange.baseMipLevel,
                 info->subresourceRange.mipLevels,
                 info->subresourceRange.baseArraySlice,
                 info->subresourceRange.arraySize, false, view->cmd);
+        view->cmd_len = 6;
     }
 
     *view_ret = view;
@@ -1135,12 +1142,14 @@
                 info->format, info->mipLevel, 1,
                 info->baseArraySlice, info->arraySize,
                 true, view->cmd);
+        view->cmd_len = 8;
     } else {
         surface_state_tex_gen6(dev->gpu, img,
                 img_type_to_view_type(img->type),
                 info->format, info->mipLevel, 1,
                 info->baseArraySlice, info->arraySize,
                 true, view->cmd);
+        view->cmd_len = 6;
     }
 
     *view_ret = view;