commit d1eb90cec1ebe9e78da91e80f4470156556d51b2
author Chia-I Wu <olvaffe@gmail.com> Sat Mar 07 06:01:45 2015 +0800
committer Chia-I Wu <olvaffe@gmail.com> Thu Mar 12 12:16:59 2015 +0800
tree 9a598f5a4ada3110c44e534ca94e8c8866b59ee2
parent 3d0f59ca2b94346dc613c522d54769b5eefd6216

intel: update layout code from ilo

The new code has Gen8 support and minor bug fixes.  It also switched from
INTEL_TILING_x to GEN6_TILING_x.

icd/intel/view.c

diff --git a/icd/intel/view.c b/icd/intel/view.c
index cebbcf9..07e17fe 100644
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -221,16 +221,6 @@
     }
 }
 
-static int winsys_tiling_to_surface_tiling(enum intel_tiling_mode tiling)
-{
-    switch (tiling) {
-    case INTEL_TILING_NONE: return GEN6_TILING_NONE;
-    case INTEL_TILING_X:    return GEN6_TILING_X;
-    case INTEL_TILING_Y:    return GEN6_TILING_Y;
-    default: assert(!"unknown tiling"); return GEN6_TILING_NONE;
-    }
-}
-
 static int channel_swizzle_to_scs(XGL_CHANNEL_SWIZZLE swizzle)
 {
     switch (swizzle) {
@@ -351,16 +341,17 @@
     *
     *     "For linear surfaces, this field (X Offset) must be zero."
     */
-   if (img->layout.tiling == INTEL_TILING_NONE) {
+   if (img->layout.tiling == GEN6_TILING_NONE) {
       if (is_rt) {
          const int elem_size U_ASSERT_ONLY = icd_format_get_size(format);
          assert(pitch % elem_size == 0);
       }
    }
 
+   assert(img->layout.tiling != GEN8_TILING_W);
    dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
            surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
-           winsys_tiling_to_surface_tiling(img->layout.tiling) << 13;
+           img->layout.tiling << 13;
 
    /*
     * From the Ivy Bridge PRM, volume 4 part 1, page 63:
@@ -688,7 +679,7 @@
     *
     *     "For linear surfaces, this field (X Offset) must be zero"
     */
-   if (img->layout.tiling == INTEL_TILING_NONE) {
+   if (img->layout.tiling == GEN6_TILING_NONE) {
       if (is_rt) {
          const int elem_size U_ASSERT_ONLY = icd_format_get_size(format);
          assert(pitch % elem_size == 0);
@@ -713,9 +704,10 @@
            (width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT |
            lod << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
 
+   assert(img->layout.tiling != GEN8_TILING_W);
    dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT |
            (pitch - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
-           winsys_tiling_to_surface_tiling(img->layout.tiling);
+           img->layout.tiling;
 
    dw[4] = first_level << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
            first_layer << 17 |