| commit | db3fbc43fbdf184d376f786c24cdacc4ce776022 | [log] [tgz] |
|---|---|---|
| author | Chia-I Wu <olvaffe@gmail.com> | Tue Mar 24 10:55:40 2015 +0800 |
| committer | Mike Stroyan <mike@LunarG.com> | Tue Mar 24 15:39:16 2015 -0600 |
| tree | c6d97558c9a44ee59045eea91ce09924fb39b37b | |
| parent | 341c0f8c9565a30975979f3a59bb250deebdea22 [diff] [blame] |
intel: honor programPointSize Set up 3DSTATE_SF according to programPointSize.
diff --git a/icd/intel/pipeline.h b/icd/intel/pipeline.h index 8151037..c340301 100644 --- a/icd/intel/pipeline.h +++ b/icd/intel/pipeline.h
@@ -195,6 +195,7 @@ // XGL_PIPELINE_RS_STATE_CREATE_INFO rs_state; bool depthClipEnable; bool rasterizerDiscardEnable; + bool use_rs_point_size; XGL_PIPELINE_TESS_STATE_CREATE_INFO tess_state;