i965: Add Intel driver ICD
This driver will work with Ivybridge and Haswell graphics.
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3a854d6..fa2c6d1 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -15,6 +15,7 @@
include_directories("${PROJECT_BINARY_DIR}")
# xgl global includes
+include_directories("/usr/include/drm")
include_directories("${PROJECT_SOURCE_DIR}/include")
set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c99 -Wall")
diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt
new file mode 100644
index 0000000..4469ff6
--- /dev/null
+++ b/drivers/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory (intel)
diff --git a/drivers/intel/CMakeLists.txt b/drivers/intel/CMakeLists.txt
new file mode 100644
index 0000000..916fe09
--- /dev/null
+++ b/drivers/intel/CMakeLists.txt
@@ -0,0 +1,25 @@
+# Create the i965 XGL DRI library
+
+include_directories("${PROJECT_SOURCE_DIR}/loader")
+
+link_directories (
+)
+
+link_libraries (
+ drm
+ udev
+)
+
+
+add_library(XGL_i965 SHARED
+ init_driver.c
+ gpuinfo.c
+ )
+
+IF(UNIX)
+ IF(CMAKE_COMPILER_IS_GNUCC)
+ SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fvisibility=hidden")
+ ENDIF(CMAKE_COMPILER_IS_GNUCC)
+ENDIF(UNIX)
+
+# set_target_properties(i915_xgl PROPERTIES PREFIX "")
diff --git a/drivers/intel/driver.h b/drivers/intel/driver.h
new file mode 100644
index 0000000..fbf4ee2
--- /dev/null
+++ b/drivers/intel/driver.h
@@ -0,0 +1,196 @@
+/*
+ * Mesa 3-D graphics library
+ *
+ * Copyright (C) 2012-2013 LunarG, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Courtney Goeltzenleuchter <courtney@lunarg.com>
+ */
+
+#ifndef __DRIVER_H_INCLUDED__
+#define __DRIVER_H_INCLUDED__
+
+#include <stdio.h>
+
+#include "xgl.h"
+#include "xglDbg.h"
+
+struct icd_dispatch_table {
+ XGL_RESULT (XGLAPI *InitAndEnumerateGpus)(const XGL_APPLICATION_INFO* pAppInfo, const XGL_ALLOC_CALLBACKS* pAllocCb, XGL_UINT maxGpus, XGL_UINT* pGpuCount, XGL_PHYSICAL_GPU* pGpus);
+ XGL_RESULT (XGLAPI *GetGpuInfo)(XGL_PHYSICAL_GPU gpu, XGL_PHYSICAL_GPU_INFO_TYPE infoType, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *CreateDevice)(XGL_PHYSICAL_GPU gpu, const XGL_DEVICE_CREATE_INFO* pCreateInfo, XGL_DEVICE* pDevice);
+ XGL_RESULT (XGLAPI *DestroyDevice)(XGL_DEVICE device);
+ XGL_RESULT (XGLAPI *GetExtensionSupport)(XGL_PHYSICAL_GPU gpu, const XGL_CHAR* pExtName);
+ XGL_RESULT (XGLAPI *GetDeviceQueue)(XGL_DEVICE device, XGL_QUEUE_TYPE queueType, XGL_UINT queueIndex, XGL_QUEUE* pQueue);
+ XGL_RESULT (XGLAPI *QueueSubmit)(XGL_QUEUE queue, XGL_UINT cmdBufferCount, const XGL_CMD_BUFFER* pCmdBuffers, XGL_UINT memRefCount, const XGL_MEMORY_REF* pMemRefs, XGL_FENCE fence);
+ XGL_RESULT (XGLAPI *QueueSetGlobalMemReferences)(XGL_QUEUE queue, XGL_UINT memRefCount, const XGL_MEMORY_REF* pMemRefs);
+ XGL_RESULT (XGLAPI *QueueWaitIdle)(XGL_QUEUE queue);
+ XGL_RESULT (XGLAPI *DeviceWaitIdle)(XGL_DEVICE device);
+ XGL_RESULT (XGLAPI *GetMemoryHeapCount)(XGL_DEVICE device, XGL_UINT* pCount);
+ XGL_RESULT (XGLAPI *GetMemoryHeapInfo)(XGL_DEVICE device, XGL_UINT heapId, XGL_MEMORY_HEAP_INFO_TYPE infoType, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *AllocMemory)(XGL_DEVICE device, const XGL_MEMORY_ALLOC_INFO* pAllocInfo, XGL_GPU_MEMORY* pMem);
+ XGL_RESULT (XGLAPI *FreeMemory)(XGL_GPU_MEMORY mem);
+ XGL_RESULT (XGLAPI *SetMemoryPriority)(XGL_GPU_MEMORY mem, XGL_MEMORY_PRIORITY priority);
+ XGL_RESULT (XGLAPI *MapMemory)(XGL_GPU_MEMORY mem, XGL_FLAGS flags, XGL_VOID** ppData);
+ XGL_RESULT (XGLAPI *UnmapMemory)(XGL_GPU_MEMORY mem);
+ XGL_RESULT (XGLAPI *PinSystemMemory)(XGL_DEVICE device, const XGL_VOID* pSysMem, XGL_SIZE memSize, XGL_GPU_MEMORY* pMem);
+ XGL_RESULT (XGLAPI *RemapVirtualMemoryPages)(XGL_DEVICE device, XGL_UINT rangeCount, const XGL_VIRTUAL_MEMORY_REMAP_RANGE* pRanges, XGL_UINT preWaitSemaphoreCount, const XGL_QUEUE_SEMAPHORE* pPreWaitSemaphores, XGL_UINT postSignalSemaphoreCount, const XGL_QUEUE_SEMAPHORE* pPostSignalSemaphores);
+ XGL_RESULT (XGLAPI *GetMultiGpuCompatibility)(XGL_PHYSICAL_GPU gpu0, XGL_PHYSICAL_GPU gpu1, XGL_GPU_COMPATIBILITY_INFO* pInfo);
+ XGL_RESULT (XGLAPI *OpenSharedMemory)(XGL_DEVICE device, const XGL_MEMORY_OPEN_INFO* pOpenInfo, XGL_GPU_MEMORY* pMem);
+ XGL_RESULT (XGLAPI *OpenSharedQueueSemaphore)(XGL_DEVICE device, const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo, XGL_QUEUE_SEMAPHORE* pSemaphore);
+ XGL_RESULT (XGLAPI *OpenPeerMemory)(XGL_DEVICE device, const XGL_PEER_MEMORY_OPEN_INFO* pOpenInfo, XGL_GPU_MEMORY* pMem);
+ XGL_RESULT (XGLAPI *OpenPeerImage)(XGL_DEVICE device, const XGL_PEER_IMAGE_OPEN_INFO* pOpenInfo, XGL_IMAGE* pImage, XGL_GPU_MEMORY* pMem);
+ XGL_RESULT (XGLAPI *DestroyObject)(XGL_OBJECT object);
+ XGL_RESULT (XGLAPI *GetObjectInfo)(XGL_BASE_OBJECT object, XGL_OBJECT_INFO_TYPE infoType, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *BindObjectMemory)(XGL_OBJECT object, XGL_GPU_MEMORY mem, XGL_GPU_SIZE offset);
+ XGL_RESULT (XGLAPI *CreateFence)(XGL_DEVICE device, const XGL_FENCE_CREATE_INFO* pCreateInfo, XGL_FENCE* pFence);
+ XGL_RESULT (XGLAPI *GetFenceStatus)(XGL_FENCE fence);
+ XGL_RESULT (XGLAPI *WaitForFences)(XGL_DEVICE device, XGL_UINT fenceCount, const XGL_FENCE* pFences, XGL_BOOL waitAll, XGL_UINT64 timeout);
+ XGL_RESULT (XGLAPI *CreateQueueSemaphore)(XGL_DEVICE device, const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo, XGL_QUEUE_SEMAPHORE* pSemaphore);
+ XGL_RESULT (XGLAPI *SignalQueueSemaphore)(XGL_QUEUE queue, XGL_QUEUE_SEMAPHORE semaphore);
+ XGL_RESULT (XGLAPI *WaitQueueSemaphore)(XGL_QUEUE queue, XGL_QUEUE_SEMAPHORE semaphore);
+ XGL_RESULT (XGLAPI *CreateEvent)(XGL_DEVICE device, const XGL_EVENT_CREATE_INFO* pCreateInfo, XGL_EVENT* pEvent);
+ XGL_RESULT (XGLAPI *GetEventStatus)(XGL_EVENT event);
+ XGL_RESULT (XGLAPI *SetEvent)(XGL_EVENT event);
+ XGL_RESULT (XGLAPI *ResetEvent)(XGL_EVENT event);
+ XGL_RESULT (XGLAPI *CreateQueryPool)(XGL_DEVICE device, const XGL_QUERY_POOL_CREATE_INFO* pCreateInfo, XGL_QUERY_POOL* pQueryPool);
+ XGL_RESULT (XGLAPI *GetQueryPoolResults)(XGL_QUERY_POOL queryPool, XGL_UINT startQuery, XGL_UINT queryCount, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *GetFormatInfo)(XGL_DEVICE device, XGL_FORMAT format, XGL_FORMAT_INFO_TYPE infoType, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *CreateImage)(XGL_DEVICE device, const XGL_IMAGE_CREATE_INFO* pCreateInfo, XGL_IMAGE* pImage);
+ XGL_RESULT (XGLAPI *GetImageSubresourceInfo)(XGL_IMAGE image, const XGL_IMAGE_SUBRESOURCE* pSubresource, XGL_SUBRESOURCE_INFO_TYPE infoType, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *CreateImageView)(XGL_DEVICE device, const XGL_IMAGE_VIEW_CREATE_INFO* pCreateInfo, XGL_IMAGE_VIEW* pView);
+ XGL_RESULT (XGLAPI *CreateColorAttachmentView)(XGL_DEVICE device, const XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO* pCreateInfo, XGL_COLOR_ATTACHMENT_VIEW* pView);
+ XGL_RESULT (XGLAPI *CreateDepthStencilView)(XGL_DEVICE device, const XGL_DEPTH_STENCIL_VIEW_CREATE_INFO* pCreateInfo, XGL_DEPTH_STENCIL_VIEW* pView);
+ XGL_RESULT (XGLAPI *CreateShader)(XGL_DEVICE device, const XGL_SHADER_CREATE_INFO* pCreateInfo, XGL_SHADER* pShader);
+ XGL_RESULT (XGLAPI *CreateGraphicsPipeline)(XGL_DEVICE device, const XGL_GRAPHICS_PIPELINE_CREATE_INFO* pCreateInfo, XGL_PIPELINE* pPipeline);
+ XGL_RESULT (XGLAPI *CreateComputePipeline)(XGL_DEVICE device, const XGL_COMPUTE_PIPELINE_CREATE_INFO* pCreateInfo, XGL_PIPELINE* pPipeline);
+ XGL_RESULT (XGLAPI *StorePipeline)(XGL_PIPELINE pipeline, XGL_SIZE* pDataSize, XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *LoadPipeline)(XGL_DEVICE device, XGL_SIZE dataSize, const XGL_VOID* pData, XGL_PIPELINE* pPipeline);
+ XGL_RESULT (XGLAPI *CreatePipelineDelta)(XGL_DEVICE device, XGL_PIPELINE p1, XGL_PIPELINE p2, XGL_PIPELINE_DELTA* delta);
+ XGL_RESULT (XGLAPI *CreateSampler)(XGL_DEVICE device, const XGL_SAMPLER_CREATE_INFO* pCreateInfo, XGL_SAMPLER* pSampler);
+ XGL_RESULT (XGLAPI *CreateDescriptorSet)(XGL_DEVICE device, const XGL_DESCRIPTOR_SET_CREATE_INFO* pCreateInfo, XGL_DESCRIPTOR_SET* pDescriptorSet);
+ XGL_VOID (XGLAPI *BeginDescriptorSetUpdate)(XGL_DESCRIPTOR_SET descriptorSet);
+ XGL_VOID (XGLAPI *EndDescriptorSetUpdate)(XGL_DESCRIPTOR_SET descriptorSet);
+ XGL_VOID (XGLAPI *AttachSamplerDescriptors)(XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT startSlot, XGL_UINT slotCount, const XGL_SAMPLER* pSamplers);
+ XGL_VOID (XGLAPI *AttachImageViewDescriptors)(XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT startSlot, XGL_UINT slotCount, const XGL_IMAGE_VIEW_ATTACH_INFO* pImageViews);
+ XGL_VOID (XGLAPI *AttachMemoryViewDescriptors)(XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT startSlot, XGL_UINT slotCount, const XGL_MEMORY_VIEW_ATTACH_INFO* pMemViews);
+ XGL_VOID (XGLAPI *AttachNestedDescriptors)(XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT startSlot, XGL_UINT slotCount, const XGL_DESCRIPTOR_SET_ATTACH_INFO* pNestedDescriptorSets);
+ XGL_VOID (XGLAPI *ClearDescriptorSetSlots)(XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT startSlot, XGL_UINT slotCount);
+ XGL_RESULT (XGLAPI *CreateViewportState)(XGL_DEVICE device, const XGL_VIEWPORT_STATE_CREATE_INFO* pCreateInfo, XGL_VIEWPORT_STATE_OBJECT* pState);
+ XGL_RESULT (XGLAPI *CreateRasterState)(XGL_DEVICE device, const XGL_RASTER_STATE_CREATE_INFO* pCreateInfo, XGL_RASTER_STATE_OBJECT* pState);
+ XGL_RESULT (XGLAPI *CreateMsaaState)(XGL_DEVICE device, const XGL_MSAA_STATE_CREATE_INFO* pCreateInfo, XGL_MSAA_STATE_OBJECT* pState);
+ XGL_RESULT (XGLAPI *CreateColorBlendState)(XGL_DEVICE device, const XGL_COLOR_BLEND_STATE_CREATE_INFO* pCreateInfo, XGL_COLOR_BLEND_STATE_OBJECT* pState);
+ XGL_RESULT (XGLAPI *CreateDepthStencilState)(XGL_DEVICE device, const XGL_DEPTH_STENCIL_STATE_CREATE_INFO* pCreateInfo, XGL_DEPTH_STENCIL_STATE_OBJECT* pState);
+ XGL_RESULT (XGLAPI *CreateCommandBuffer)(XGL_DEVICE device, const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo, XGL_CMD_BUFFER* pCmdBuffer);
+ XGL_RESULT (XGLAPI *BeginCommandBuffer)(XGL_CMD_BUFFER cmdBuffer, XGL_FLAGS flags);
+ XGL_RESULT (XGLAPI *EndCommandBuffer)(XGL_CMD_BUFFER cmdBuffer);
+ XGL_RESULT (XGLAPI *ResetCommandBuffer)(XGL_CMD_BUFFER cmdBuffer);
+ XGL_VOID (XGLAPI *CmdBindPipeline)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_PIPELINE pipeline);
+ XGL_VOID (XGLAPI *CmdBindPipelineDelta)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_PIPELINE_DELTA delta);
+ XGL_VOID (XGLAPI *CmdBindStateObject)(XGL_CMD_BUFFER cmdBuffer, XGL_STATE_BIND_POINT stateBindPoint, XGL_STATE_OBJECT state);
+ XGL_VOID (XGLAPI *CmdBindDescriptorSet)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_UINT index, XGL_DESCRIPTOR_SET descriptorSet, XGL_UINT slotOffset);
+ XGL_VOID (XGLAPI *CmdBindDynamicMemoryView)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
+ XGL_VOID (XGLAPI *CmdBindIndexData)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY mem, XGL_GPU_SIZE offset, XGL_INDEX_TYPE indexType);
+ XGL_VOID (XGLAPI *CmdBindAttachments)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT colorAttachmentCount, const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments, const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
+ XGL_VOID (XGLAPI *CmdPrepareMemoryRegions)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT transitionCount, const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
+ XGL_VOID (XGLAPI *CmdPrepareImages)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT transitionCount, const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
+ XGL_VOID (XGLAPI *CmdDraw)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT firstVertex, XGL_UINT vertexCount, XGL_UINT firstInstance, XGL_UINT instanceCount);
+ XGL_VOID (XGLAPI *CmdDrawIndexed)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT firstIndex, XGL_UINT indexCount, XGL_INT vertexOffset, XGL_UINT firstInstance, XGL_UINT instanceCount);
+ XGL_VOID (XGLAPI *CmdDrawIndirect)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY mem, XGL_GPU_SIZE offset, XGL_UINT32 count, XGL_UINT32 stride);
+ XGL_VOID (XGLAPI *CmdDrawIndexedIndirect)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY mem, XGL_GPU_SIZE offset, XGL_UINT32 count, XGL_UINT32 stride);
+ XGL_VOID (XGLAPI *CmdDispatch)(XGL_CMD_BUFFER cmdBuffer, XGL_UINT x, XGL_UINT y, XGL_UINT z);
+ XGL_VOID (XGLAPI *CmdDispatchIndirect)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY mem, XGL_GPU_SIZE offset);
+ XGL_VOID (XGLAPI *CmdCopyMemory)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY srcMem, XGL_GPU_MEMORY destMem, XGL_UINT regionCount, const XGL_MEMORY_COPY* pRegions);
+ XGL_VOID (XGLAPI *CmdCopyImage)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE srcImage, XGL_IMAGE destImage, XGL_UINT regionCount, const XGL_IMAGE_COPY* pRegions);
+ XGL_VOID (XGLAPI *CmdCopyMemoryToImage)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY srcMem, XGL_IMAGE destImage, XGL_UINT regionCount, const XGL_MEMORY_IMAGE_COPY* pRegions);
+ XGL_VOID (XGLAPI *CmdCopyImageToMemory)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE srcImage, XGL_GPU_MEMORY destMem, XGL_UINT regionCount, const XGL_MEMORY_IMAGE_COPY* pRegions);
+ XGL_VOID (XGLAPI *CmdCloneImageData)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE srcImage, XGL_IMAGE_STATE srcImageState, XGL_IMAGE destImage, XGL_IMAGE_STATE destImageState);
+ XGL_VOID (XGLAPI *CmdUpdateMemory)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY destMem, XGL_GPU_SIZE destOffset, XGL_GPU_SIZE dataSize, const XGL_UINT32* pData);
+ XGL_VOID (XGLAPI *CmdFillMemory)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY destMem, XGL_GPU_SIZE destOffset, XGL_GPU_SIZE fillSize, XGL_UINT32 data);
+ XGL_VOID (XGLAPI *CmdClearColorImage)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE image, const XGL_FLOAT color[4], XGL_UINT rangeCount, const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
+ XGL_VOID (XGLAPI *CmdClearColorImageRaw)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE image, const XGL_UINT32 color[4], XGL_UINT rangeCount, const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
+ XGL_VOID (XGLAPI *CmdClearDepthStencil)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE image, XGL_FLOAT depth, XGL_UINT32 stencil, XGL_UINT rangeCount, const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
+ XGL_VOID (XGLAPI *CmdResolveImage)(XGL_CMD_BUFFER cmdBuffer, XGL_IMAGE srcImage, XGL_IMAGE destImage, XGL_UINT rectCount, const XGL_IMAGE_RESOLVE* pRects);
+ XGL_VOID (XGLAPI *CmdSetEvent)(XGL_CMD_BUFFER cmdBuffer, XGL_EVENT event);
+ XGL_VOID (XGLAPI *CmdResetEvent)(XGL_CMD_BUFFER cmdBuffer, XGL_EVENT event);
+ XGL_VOID (XGLAPI *CmdMemoryAtomic)(XGL_CMD_BUFFER cmdBuffer, XGL_GPU_MEMORY destMem, XGL_GPU_SIZE destOffset, XGL_UINT64 srcData, XGL_ATOMIC_OP atomicOp);
+ XGL_VOID (XGLAPI *CmdBeginQuery)(XGL_CMD_BUFFER cmdBuffer, XGL_QUERY_POOL queryPool, XGL_UINT slot, XGL_FLAGS flags);
+ XGL_VOID (XGLAPI *CmdEndQuery)(XGL_CMD_BUFFER cmdBuffer, XGL_QUERY_POOL queryPool, XGL_UINT slot);
+ XGL_VOID (XGLAPI *CmdResetQueryPool)(XGL_CMD_BUFFER cmdBuffer, XGL_QUERY_POOL queryPool, XGL_UINT startQuery, XGL_UINT queryCount);
+ XGL_VOID (XGLAPI *CmdWriteTimestamp)(XGL_CMD_BUFFER cmdBuffer, XGL_TIMESTAMP_TYPE timestampType, XGL_GPU_MEMORY destMem, XGL_GPU_SIZE destOffset);
+ XGL_VOID (XGLAPI *CmdInitAtomicCounters)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_UINT startCounter, XGL_UINT counterCount, const XGL_UINT32* pData);
+ XGL_VOID (XGLAPI *CmdLoadAtomicCounters)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_UINT startCounter, XGL_UINT counterCount, XGL_GPU_MEMORY srcMem, XGL_GPU_SIZE srcOffset);
+ XGL_VOID (XGLAPI *CmdSaveAtomicCounters)(XGL_CMD_BUFFER cmdBuffer, XGL_PIPELINE_BIND_POINT pipelineBindPoint, XGL_UINT startCounter, XGL_UINT counterCount, XGL_GPU_MEMORY destMem, XGL_GPU_SIZE destOffset);
+ XGL_RESULT (XGLAPI *DbgSetValidationLevel)(XGL_DEVICE device, XGL_VALIDATION_LEVEL validationLevel);
+ XGL_RESULT (XGLAPI *DbgRegisterMsgCallback)(XGL_DBG_MSG_CALLBACK_FUNCTION pfnMsgCallback, XGL_VOID* pUserData);
+ XGL_RESULT (XGLAPI *DbgUnregisterMsgCallback)(XGL_DBG_MSG_CALLBACK_FUNCTION pfnMsgCallback);
+ XGL_RESULT (XGLAPI *DbgSetMessageFilter)(XGL_DEVICE device, XGL_INT msgCode, XGL_DBG_MSG_FILTER filter);
+ XGL_RESULT (XGLAPI *DbgSetObjectTag)(XGL_BASE_OBJECT object, XGL_SIZE tagSize, const XGL_VOID* pTag);
+ XGL_RESULT (XGLAPI *DbgSetGlobalOption)(XGL_DBG_GLOBAL_OPTION dbgOption, XGL_SIZE dataSize, const XGL_VOID* pData);
+ XGL_RESULT (XGLAPI *DbgSetDeviceOption)(XGL_DEVICE device, XGL_DBG_DEVICE_OPTION dbgOption, XGL_SIZE dataSize, const XGL_VOID* pData);
+ XGL_VOID (XGLAPI *CmdDbgMarkerBegin)(XGL_CMD_BUFFER cmdBuffer, const XGL_CHAR* pMarker);
+ XGL_VOID (XGLAPI *CmdDbgMarkerEnd)(XGL_CMD_BUFFER cmdBuffer);
+};
+
+/**
+ * Typedefs for all XGL API entrypoint functions.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Base class for device drivers.
+ */
+#define MAX_DRIVER_NAME 64
+
+struct _xgl_device {
+ /* MUST be first element of structure */
+ struct icd_dispatch_table *exec;
+
+ struct icd_dispatch_table xgl;
+ struct icd_dispatch_table validation;
+
+ int fd; /* file descriptor of render-node */
+ uint32_t dev_id;
+ uint32_t ven_id;
+ char device_path[XGL_MAX_PHYSICAL_GPU_NAME];
+ char driver_name[MAX_DRIVER_NAME];
+ void *driver_handle;
+};
+
+
+struct _xgl_config {
+ XGL_BOOL UserDefinedAlloc;
+ XGL_ALLOC_CALLBACKS xgl_alloc;
+
+ XGL_UINT num_gpus;
+ struct _xgl_device gpu_info[XGL_MAX_PHYSICAL_GPUS];
+ XGL_PHYSICAL_GPU render_node_list[XGL_MAX_PHYSICAL_GPUS];
+};
+
+extern struct _xgl_config icd_data;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif // __cplusplus
+#endif /* __DRIVER_H_INCLUDED__ */
diff --git a/drivers/intel/gen7_functions.h b/drivers/intel/gen7_functions.h
new file mode 100644
index 0000000..b696dfa
--- /dev/null
+++ b/drivers/intel/gen7_functions.h
@@ -0,0 +1,36 @@
+/*
+ * XGL 3-D graphics library
+ *
+ * Copyright (C) 2014 LunarG, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Courtney Goeltzenleuchter <courtney@lunarg.com>
+ */
+
+#ifndef GEN7_FUNCTIONS_H
+#define GEN7_FUNCTIONS_H
+#include "driver.h"
+
+XGL_RESULT gen7_GetGpuInfo(XGL_PHYSICAL_GPU gpu,
+ XGL_PHYSICAL_GPU_INFO_TYPE infoType,
+ XGL_SIZE * pDataSize, XGL_VOID * pData);
+
+#endif // GEN7_FUNCTIONS_H
diff --git a/drivers/intel/gpuinfo.c b/drivers/intel/gpuinfo.c
new file mode 100644
index 0000000..80db0d8
--- /dev/null
+++ b/drivers/intel/gpuinfo.c
@@ -0,0 +1,55 @@
+/*
+ * XGL 3-D graphics library
+ *
+ * Copyright (C) 2014 LunarG, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Courtney Goeltzenleuchter <courtney@lunarg.com>
+ */
+
+#include "driver.h"
+
+XGL_RESULT gen7_GetGpuInfo(XGL_PHYSICAL_GPU gpu,
+ XGL_PHYSICAL_GPU_INFO_TYPE infoType,
+ XGL_SIZE * pDataSize, XGL_VOID * pData)
+{
+ XGL_RESULT ret = XGL_SUCCESS;
+ struct _xgl_device *pdev = (struct _xgl_device *) gpu;
+
+ switch (infoType) {
+ case XGL_INFO_TYPE_PHYSICAL_GPU_PROPERTIES:
+ break;
+
+ case XGL_INFO_TYPE_PHYSICAL_GPU_PERFORMANCE:
+ break;
+
+ case XGL_INFO_TYPE_PHYSICAL_GPU_QUEUE_PROPERTIES:
+ break;
+
+ case XGL_INFO_TYPE_PHYSICAL_GPU_MEMORY_PROPERTIES:
+ break;
+
+ default:
+ ret = XGL_ERROR_INVALID_VALUE;
+ }
+
+ return ret;
+}
diff --git a/drivers/intel/init_driver.c b/drivers/intel/init_driver.c
new file mode 100644
index 0000000..5af9184
--- /dev/null
+++ b/drivers/intel/init_driver.c
@@ -0,0 +1,391 @@
+/*
+ * XGL 3-D graphics library
+ *
+ * Copyright (C) 2014 LunarG, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Courtney Goeltzenleuchter <courtney@lunarg.com>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <assert.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <dirent.h>
+#include <errno.h>
+#include <fnmatch.h>
+
+#include <pciaccess.h>
+
+#include <xf86drm.h>
+#include <drm/i915_drm.h>
+
+#include <libudev.h>
+#include <dlfcn.h>
+
+#ifdef HAVE_VALGRIND
+#include <valgrind.h>
+#include <memcheck.h>
+#define VG(x) x
+#else
+#define VG(x)
+#endif
+
+#define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
+
+#include "xgl.h"
+#include "xglDbg.h"
+
+#include "driver.h"
+#include "intel_chipset.h"
+#include "gen7_functions.h"
+
+XGL_RESULT XGLAPI GetExtensionSupport(XGL_PHYSICAL_GPU gpu, const XGL_CHAR* pExtName);
+
+
+#if defined(__WIN32__) && !defined(__CYGWIN__)
+#elif defined(__CYGWIN__) && defined(USE_OPENGL32) /* use native windows opengl32 */
+# define ICDENTRY extern
+#elif (defined(__GNUC__) && __GNUC__ >= 4) || (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590))
+# define ICDENTRY __attribute__((visibility("default")))
+#endif /* WIN32 && !CYGWIN */
+
+#define LOADER_DBG_MSG_SIZE 256
+
+/*
+ * Global to contain application allocation call-backs
+ * and GPU enumeration info.
+ */
+struct _xgl_config icd_data;
+
+struct icd_msg_callback {
+ XGL_DBG_MSG_CALLBACK_FUNCTION func;
+ XGL_VOID *data;
+
+ struct icd_msg_callback *next;
+};
+
+static XGL_VOID *_xglAlloc(XGL_VOID * pUserData, XGL_SIZE size,
+ XGL_SIZE alignment, XGL_SYSTEM_ALLOC_TYPE allocType)
+{
+ // TODO: ensure alignment
+ // can we use? aligned_alloc(alignment, size);
+ return (XGL_VOID *) malloc(size);
+}
+
+static XGL_VOID _xglFree(XGL_VOID * pUserData, XGL_VOID * pMem)
+{
+ free(pMem);
+}
+
+static struct icd_msg_callback *icd_msg_callbacks = NULL;
+
+static XGL_RESULT icd_msg_callback_add(XGL_DBG_MSG_CALLBACK_FUNCTION func,
+ XGL_VOID * data)
+{
+ struct icd_msg_callback *cb;
+
+ cb = malloc(sizeof(*cb));
+ if (!cb)
+ return XGL_ERROR_OUT_OF_MEMORY;
+
+ cb->func = func;
+ cb->data = data;
+
+ cb->next = icd_msg_callbacks;
+ icd_msg_callbacks = cb;
+
+ return XGL_SUCCESS;
+}
+
+static XGL_RESULT icd_msg_callback_remove(XGL_DBG_MSG_CALLBACK_FUNCTION func)
+{
+ struct icd_msg_callback *cb = icd_msg_callbacks;
+
+ /*
+ * Find the first match.
+ *
+ * XXX What if the same callback function is registered more
+ * than once?
+ */
+ while (cb) {
+ if (cb->func == func)
+ break;
+ cb = cb->next;
+ }
+
+ if (!cb)
+ return XGL_ERROR_INVALID_POINTER;
+
+ free(cb);
+
+ return XGL_SUCCESS;
+}
+
+static void icd_msg_callback_clear(void)
+{
+ struct icd_msg_callback *cb = icd_msg_callbacks;
+
+ cb = icd_msg_callbacks;
+ while (cb) {
+ struct icd_msg_callback *next = cb->next;
+ free(cb);
+ cb = next;
+ }
+}
+
+static void loader_err(XGL_INT msg_code, const char *format, ...)
+{
+ const struct icd_msg_callback *cb = icd_msg_callbacks;
+ char msg[LOADER_DBG_MSG_SIZE];
+ va_list ap;
+ int ret;
+
+ if (!cb) {
+#if 1
+ fputs(msg, stderr);
+ fputc('\n', stderr);
+#endif
+ return;
+ }
+
+ va_start(ap, format);
+ ret = vsnprintf(msg, sizeof(msg), format, ap);
+ if (ret >= sizeof(msg) || ret < 0)
+ msg[sizeof(msg) - 1] = '\0';
+ va_end(ap);
+
+ while (cb) {
+ cb->func(0, 0, XGL_NULL_HANDLE, 0, msg_code, (const XGL_CHAR *) msg,
+ cb->data);
+ cb = cb->next;
+ }
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglLoad()
+{
+ memset(&icd_data, 0, sizeof(icd_data));
+ return XGL_SUCCESS;
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglUnload()
+{
+ // TODO: Free resources
+ icd_msg_callback_clear();
+ return XGL_SUCCESS;
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglDbgSetGlobalOption(XGL_DBG_GLOBAL_OPTION dbgOption,
+ XGL_SIZE dataSize,
+ const XGL_VOID * pData)
+{
+ return XGL_SUCCESS;
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglDbgRegisterMsgCallback(XGL_DBG_MSG_CALLBACK_FUNCTION
+ pfnMsgCallback,
+ XGL_VOID * pUserData)
+{
+ return icd_msg_callback_add(pfnMsgCallback, pUserData);
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglDbgUnregisterMsgCallback(XGL_DBG_MSG_CALLBACK_FUNCTION
+ pfnMsgCallback)
+{
+ return icd_msg_callback_remove(pfnMsgCallback);
+}
+
+static int is_render_node(int fd, struct stat *st)
+{
+ if (fstat(fd, st))
+ return 0;
+
+ if (!S_ISCHR(st->st_mode))
+ return 0;
+
+ return st->st_rdev & 0x80;
+}
+
+static void init_xgl_dispatch_table(struct icd_dispatch_table *pDispatch)
+{
+#define LOAD(xglfunc, driverfunc) do { \
+ pDispatch->xglfunc = driverfunc; \
+} while (0)
+ LOAD(GetGpuInfo, gen7_GetGpuInfo);
+ LOAD(GetExtensionSupport, GetExtensionSupport);
+}
+
+static void init_validation_dispatch_table(struct icd_dispatch_table *pDispatch)
+{
+#define LOAD(xglfunc, driverfunc) do { \
+ pDispatch->xglfunc = driverfunc; \
+} while (0)
+ LOAD(GetGpuInfo, gen7_GetGpuInfo);
+ LOAD(GetExtensionSupport, GetExtensionSupport);
+}
+
+ICDENTRY XGL_RESULT XGLAPI xglInitAndEnumerateGpus(const XGL_APPLICATION_INFO *
+ pAppInfo,
+ const XGL_ALLOC_CALLBACKS *
+ pAllocCb, XGL_UINT maxGpus,
+ XGL_UINT * pGpuCount,
+ XGL_PHYSICAL_GPU * pGpus)
+{
+ struct udev *udev;
+ struct udev_enumerate *e;
+ struct udev_device *device, *parent;
+ struct udev_list_entry *entry;
+ const char *pci_id, *path;
+ const char *usub, *dnode;
+ int fd;
+ struct stat st;
+ char *pci_glob = "*:*";
+ XGL_RESULT ret = XGL_ERROR_UNAVAILABLE;
+ XGL_UINT count = 0;
+ struct _xgl_device *pXglDev;
+
+ // TODO: Do we need to keep track of previous calls to xglInitAndEnumerageGpus?
+ /*
+ * xglInitAndEnumerateGpus() can be called multiple times. Calling it more than once
+ * forces driver reinitialization.
+ */
+
+ if (icd_data.num_gpus > 0) {
+ /*
+ * When xglInitAndEnumerateGpus() is called multiple times,
+ * the same callbacks have to be provided on each invocation.
+ * Changing the callbacks on subsequent calls to xglInitAndEnumerateGpus()
+ * causes it to fail with XGL_ERROR_INVALID_POINTER error.
+ */
+ if (icd_data.UserDefinedAlloc
+ && (icd_data.xgl_alloc.pfnAlloc != pAllocCb->pfnAlloc
+ || icd_data.xgl_alloc.pfnFree != pAllocCb->pfnFree)) {
+ // TODO: Do we still re-initialize the structure?
+ return XGL_ERROR_INVALID_POINTER;
+ }
+ // TODO: Free resources and re-initialize
+ }
+ // TODO: Do we need any other validation for incoming pointers?
+
+ if (pAllocCb != XGL_NULL_HANDLE && pAllocCb->pfnAlloc != XGL_NULL_HANDLE) {
+ icd_data.UserDefinedAlloc = XGL_TRUE;
+ icd_data.xgl_alloc.pfnAlloc = pAllocCb->pfnAlloc;
+ icd_data.xgl_alloc.pfnFree = pAllocCb->pfnFree;
+ icd_data.xgl_alloc.pUserData = pAllocCb->pUserData;
+ } else {
+ icd_data.xgl_alloc.pfnAlloc = _xglAlloc;
+ icd_data.xgl_alloc.pfnFree = _xglFree;
+ icd_data.xgl_alloc.pUserData = XGL_NULL_HANDLE;
+ }
+
+ udev = udev_new();
+ if (udev == NULL) {
+ loader_err(0, "failed to initialize udev context");
+ abort();
+ }
+
+ memset(icd_data.gpu_info, 0,
+ sizeof(icd_data.gpu_info[XGL_MAX_PHYSICAL_GPUS]));
+ memset(icd_data.render_node_list, 0,
+ sizeof(icd_data.render_node_list[XGL_MAX_PHYSICAL_GPUS]));
+
+ fd = -1;
+ e = udev_enumerate_new(udev);
+ udev_enumerate_add_match_subsystem(e, "drm");
+ udev_enumerate_scan_devices(e);
+ udev_list_entry_foreach(entry, udev_enumerate_get_list_entry(e)) {
+ path = udev_list_entry_get_name(entry);
+ device = udev_device_new_from_syspath(udev, path);
+ parent = udev_device_get_parent(device);
+ usub = udev_device_get_subsystem(parent);
+ /* Filter out KMS output devices. */
+ if (!usub || (strcmp(usub, "pci") != 0))
+ continue;
+ pci_id = udev_device_get_property_value(parent, "PCI_ID");
+ if (fnmatch(pci_glob, pci_id, 0) != 0)
+ continue;
+ dnode = udev_device_get_devnode(device);
+ fd = open(dnode, O_RDWR);
+ if (fd < 0)
+ continue;
+ if (!is_render_node(fd, &st)) {
+ close(fd);
+ fd = -1;
+ continue;
+ }
+
+ pXglDev = &icd_data.gpu_info[count];
+
+ sscanf(pci_id, "%x:%x", &pXglDev->ven_id, &pXglDev->dev_id);
+ /*
+ * Currently only allowing Ivybridge and Haswell
+ */
+ if (!IS_HASWELL(pXglDev->dev_id) && !IS_IVYBRIDGE(pXglDev->dev_id)) {
+ close(fd);
+ fd = -1;
+ continue;
+ }
+
+ /*
+ * We'll keep the fd open for any subsequent
+ * xglGetGpuInfo calls.
+ */
+ pXglDev->fd = fd;
+ strncpy(pXglDev->device_path, dnode, XGL_MAX_PHYSICAL_GPU_NAME);
+ icd_data.render_node_list[count] = pXglDev;
+ init_xgl_dispatch_table(&pXglDev->xgl);
+ init_validation_dispatch_table(&pXglDev->validation);
+ pXglDev->exec = & pXglDev->xgl;
+
+ ret = XGL_SUCCESS;
+ count++;
+ }
+ icd_data.num_gpus = count;
+ udev_enumerate_unref(e);
+ udev_unref(udev);
+
+ if (ret == XGL_SUCCESS) {
+ *pGpuCount = icd_data.num_gpus;
+ memcpy(pGpus, icd_data.render_node_list,
+ (icd_data.num_gpus >
+ maxGpus ? maxGpus : icd_data.num_gpus) *
+ sizeof(XGL_PHYSICAL_GPU));
+ }
+
+ return ret;
+}
+
+XGL_RESULT XGLAPI GetExtensionSupport(XGL_PHYSICAL_GPU gpu, const XGL_CHAR* pExtName)
+{
+ // struct _xgl_device *pdev = (struct _xgl_device *) gpu;
+
+ // TODO: Check requested extension
+
+ return XGL_ERROR_INVALID_EXTENSION;
+}
diff --git a/drivers/intel/intel_chipset.h b/drivers/intel/intel_chipset.h
new file mode 100644
index 0000000..ac3b527
--- /dev/null
+++ b/drivers/intel/intel_chipset.h
@@ -0,0 +1,325 @@
+/*
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _INTEL_CHIPSET_H
+#define _INTEL_CHIPSET_H
+
+#define PCI_CHIP_I810 0x7121
+#define PCI_CHIP_I810_DC100 0x7123
+#define PCI_CHIP_I810_E 0x7125
+#define PCI_CHIP_I815 0x1132
+
+#define PCI_CHIP_I830_M 0x3577
+#define PCI_CHIP_845_G 0x2562
+#define PCI_CHIP_I855_GM 0x3582
+#define PCI_CHIP_I865_G 0x2572
+
+#define PCI_CHIP_I915_G 0x2582
+#define PCI_CHIP_E7221_G 0x258A
+#define PCI_CHIP_I915_GM 0x2592
+#define PCI_CHIP_I945_G 0x2772
+#define PCI_CHIP_I945_GM 0x27A2
+#define PCI_CHIP_I945_GME 0x27AE
+
+#define PCI_CHIP_Q35_G 0x29B2
+#define PCI_CHIP_G33_G 0x29C2
+#define PCI_CHIP_Q33_G 0x29D2
+
+#define PCI_CHIP_IGD_GM 0xA011
+#define PCI_CHIP_IGD_G 0xA001
+
+#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
+#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
+#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
+
+#define PCI_CHIP_I965_G 0x29A2
+#define PCI_CHIP_I965_Q 0x2992
+#define PCI_CHIP_I965_G_1 0x2982
+#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_I965_GME 0x2A12
+
+#define PCI_CHIP_GM45_GM 0x2A42
+
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G41_G 0x2E32
+
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
+
+#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
+#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
+#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
+
+#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
+#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
+#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
+#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
+#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
+#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
+
+#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_GT3 0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT3 0x042A
+#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
+#define PCI_CHIP_HASWELL_B_GT2 0x041B
+#define PCI_CHIP_HASWELL_B_GT3 0x042B
+#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
+#define PCI_CHIP_HASWELL_E_GT2 0x041E
+#define PCI_CHIP_HASWELL_E_GT3 0x042E
+#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
+#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
+#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
+#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
+#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
+#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
+#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
+#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
+#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
+#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
+#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
+#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
+#define BDW_SPARE 0x2
+#define BDW_ULT 0x6
+#define BDW_SERVER 0xa
+#define BDW_IRIS 0xb
+#define BDW_WORKSTATION 0xd
+#define BDW_ULX 0xe
+
+#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+#define PCI_CHIP_VALLEYVIEW_1 0x0f31
+#define PCI_CHIP_VALLEYVIEW_2 0x0f32
+#define PCI_CHIP_VALLEYVIEW_3 0x0f33
+
+#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
+ (devid) == PCI_CHIP_I915_GM || \
+ (devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME || \
+ (devid) == PCI_CHIP_I965_GM || \
+ (devid) == PCI_CHIP_I965_GME || \
+ (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
+
+#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
+ (devid) == PCI_CHIP_Q45_G || \
+ (devid) == PCI_CHIP_G45_G || \
+ (devid) == PCI_CHIP_G41_G)
+#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
+#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
+
+#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
+#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
+
+#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
+ (devid) == PCI_CHIP_E7221_G || \
+ (devid) == PCI_CHIP_I915_GM)
+
+#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME)
+
+#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
+ (devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME || \
+ IS_G33(devid))
+
+#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
+ (devid) == PCI_CHIP_Q33_G || \
+ (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
+
+#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
+ (devid) == PCI_CHIP_845_G || \
+ (devid) == PCI_CHIP_I855_GM || \
+ (devid) == PCI_CHIP_I865_G)
+
+#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
+
+#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
+ (devid) == PCI_CHIP_I965_Q || \
+ (devid) == PCI_CHIP_I965_G_1 || \
+ (devid) == PCI_CHIP_I965_GM || \
+ (devid) == PCI_CHIP_I965_GME || \
+ (devid) == PCI_CHIP_I946_GZ || \
+ IS_G4X(devid))
+
+#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
+
+#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_S)
+
+#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
+ IS_HASWELL(devid) || \
+ IS_VALLEYVIEW(devid))
+
+#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_S || \
+ (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
+
+#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
+ (devid) == PCI_CHIP_VALLEYVIEW_1 || \
+ (devid) == PCI_CHIP_VALLEYVIEW_2 || \
+ (devid) == PCI_CHIP_VALLEYVIEW_3)
+
+#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
+#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
+#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
+
+#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+ IS_HSW_GT2(devid) || \
+ IS_HSW_GT3(devid))
+
+#define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \
+ (((devid & 0x00f0) >> 4) > 3) ? 0 : \
+ ((devid & 0x000f) == BDW_SPARE) ? 1 : \
+ ((devid & 0x000f) == BDW_ULT) ? 1 : \
+ ((devid & 0x000f) == BDW_IRIS) ? 1 : \
+ ((devid & 0x000f) == BDW_SERVER) ? 1 : \
+ ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
+ ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
+
+
+#define IS_GEN8(devid) IS_BROADWELL(devid)
+
+#define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
+ IS_GEN5(dev) || \
+ IS_GEN6(dev) || \
+ IS_GEN7(dev) || \
+ IS_GEN8(dev))
+
+
+#endif /* _INTEL_CHIPSET_H */