blob: 21f7a7737a823a8641714208bf37533eb96ba9ac [file] [log] [blame]
Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wue09b5362014-08-07 09:25:14 +080026 */
27
Chia-I Wu3ad3c542014-08-25 11:09:17 +080028#include "genhw/genhw.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080029#include "kmd/winsys.h"
Chia-I Wu34f45182014-08-19 14:02:59 +080030#include "cmd.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080031#include "dev.h"
Chia-I Wuc5438c22014-08-19 14:03:06 +080032#include "fence.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080033#include "queue.h"
34
Chia-I Wu465fe212015-02-11 11:27:06 -070035static void queue_submit_hang(struct intel_queue *queue,
36 struct intel_cmd *cmd,
37 uint32_t active_lost,
38 uint32_t pending_lost)
39{
40 intel_cmd_decode(cmd, true);
41
42 intel_dev_log(queue->dev, XGL_DBG_MSG_ERROR,
43 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
44 "GPU hanged with %d/%d active/pending command buffers lost",
45 active_lost, pending_lost);
46}
47
Chia-I Wu94d2fba2014-08-25 11:38:08 +080048static XGL_RESULT queue_submit_bo(struct intel_queue *queue,
49 struct intel_bo *bo,
50 XGL_GPU_SIZE used)
51{
52 struct intel_winsys *winsys = queue->dev->winsys;
53 int err;
54
Chia-I Wu94d2fba2014-08-25 11:38:08 +080055 if (intel_debug & INTEL_DEBUG_NOHW)
56 err = 0;
57 else
58 err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0);
59
60 return (err) ? XGL_ERROR_UNKNOWN : XGL_SUCCESS;
61}
62
Chia-I Wuec841722014-08-25 22:36:01 +080063static struct intel_bo *queue_create_bo(struct intel_queue *queue,
64 XGL_GPU_SIZE size,
65 const void *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060066 size_t cmd_len)
Chia-I Wu3ad3c542014-08-25 11:09:17 +080067{
Chia-I Wuec841722014-08-25 22:36:01 +080068 struct intel_bo *bo;
69 void *ptr;
70
71 bo = intel_winsys_alloc_buffer(queue->dev->winsys,
Chia-I Wu32a22462014-08-26 14:13:46 +080072 "queue bo", size, true);
Chia-I Wuec841722014-08-25 22:36:01 +080073 if (!bo)
74 return NULL;
75
76 if (!cmd_len)
77 return bo;
78
79 ptr = intel_bo_map(bo, true);
80 if (!ptr) {
81 intel_bo_unreference(bo);
82 return NULL;
83 }
84
85 memcpy(ptr, cmd, cmd_len);
86 intel_bo_unmap(bo);
87
88 return bo;
89}
90
91static XGL_RESULT queue_select_pipeline(struct intel_queue *queue,
92 int pipeline_select)
93{
94 uint32_t pipeline_select_cmd[] = {
Chia-I Wu426072d2014-08-26 14:31:55 +080095 GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT),
96 GEN6_MI_CMD(MI_BATCH_BUFFER_END),
Chia-I Wuec841722014-08-25 22:36:01 +080097 };
98 struct intel_bo *bo;
99 XGL_RESULT ret;
100
101 if (queue->ring != INTEL_RING_RENDER ||
102 queue->last_pipeline_select == pipeline_select)
103 return XGL_SUCCESS;
104
105 switch (pipeline_select) {
106 case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
107 bo = queue->select_graphics_bo;
108 break;
109 case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
110 bo = queue->select_compute_bo;
111 break;
112 default:
113 return XGL_ERROR_INVALID_VALUE;
114 break;
115 }
116
117 if (!bo) {
118 pipeline_select_cmd[0] |= pipeline_select;
119 bo = queue_create_bo(queue, sizeof(pipeline_select_cmd),
120 pipeline_select_cmd, sizeof(pipeline_select_cmd));
121 if (!bo)
122 return XGL_ERROR_OUT_OF_GPU_MEMORY;
123
124 switch (pipeline_select) {
125 case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
126 queue->select_graphics_bo = bo;
127 break;
128 case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
129 queue->select_compute_bo = bo;
130 break;
131 default:
132 break;
133 }
134 }
135
136 ret = queue_submit_bo(queue, bo, sizeof(pipeline_select_cmd));
137 if (ret == XGL_SUCCESS)
138 queue->last_pipeline_select = pipeline_select;
139
140 return ret;
141}
142
143static XGL_RESULT queue_init_hw_and_atomic_bo(struct intel_queue *queue)
144{
145 const uint32_t ctx_init_cmd[] = {
Chia-I Wu63883292014-08-25 13:50:26 +0800146 /* STATE_SIP */
Chia-I Wu426072d2014-08-26 14:31:55 +0800147 GEN6_RENDER_CMD(COMMON, STATE_SIP),
Chia-I Wu63883292014-08-25 13:50:26 +0800148 0,
149 /* PIPELINE_SELECT */
Chia-I Wu426072d2014-08-26 14:31:55 +0800150 GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) |
Chia-I Wu63883292014-08-25 13:50:26 +0800151 GEN6_PIPELINE_SELECT_DW0_SELECT_3D,
152 /* 3DSTATE_VF_STATISTICS */
Chia-I Wu426072d2014-08-26 14:31:55 +0800153 GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS),
Chia-I Wu63883292014-08-25 13:50:26 +0800154 /* end */
Chia-I Wu426072d2014-08-26 14:31:55 +0800155 GEN6_MI_CMD(MI_BATCH_BUFFER_END),
156 GEN6_MI_CMD(MI_NOOP),
Chia-I Wu63883292014-08-25 13:50:26 +0800157 };
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800158 struct intel_bo *bo;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800159 XGL_RESULT ret;
160
Chia-I Wuec841722014-08-25 22:36:01 +0800161 if (queue->ring != INTEL_RING_RENDER) {
162 queue->last_pipeline_select = -1;
163 queue->atomic_bo = queue_create_bo(queue,
164 sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT,
165 NULL, 0);
166 return (queue->atomic_bo) ? XGL_SUCCESS : XGL_ERROR_OUT_OF_GPU_MEMORY;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800167 }
168
Chia-I Wuec841722014-08-25 22:36:01 +0800169 bo = queue_create_bo(queue,
170 sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT,
171 ctx_init_cmd, sizeof(ctx_init_cmd));
172 if (!bo)
173 return XGL_ERROR_OUT_OF_GPU_MEMORY;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800174
Chia-I Wuec841722014-08-25 22:36:01 +0800175 ret = queue_submit_bo(queue, bo, sizeof(ctx_init_cmd));
176 if (ret != XGL_SUCCESS) {
177 intel_bo_unreference(bo);
178 return ret;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800179 }
180
Chia-I Wuec841722014-08-25 22:36:01 +0800181 queue->last_pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
182 /* reuse */
183 queue->atomic_bo = bo;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800184
Chia-I Wuec841722014-08-25 22:36:01 +0800185 return XGL_SUCCESS;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800186}
187
Chia-I Wude6f9a72015-02-17 14:11:29 -0700188static XGL_RESULT queue_submit_cmd_prepare(struct intel_queue *queue,
189 struct intel_cmd *cmd)
190{
191 if (unlikely(cmd->result != XGL_SUCCESS)) {
192 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
193 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
194 "invalid command buffer submitted");
195 return cmd->result;
196 }
197
198 return queue_select_pipeline(queue, cmd->pipeline_select);
199}
200
201static XGL_RESULT queue_submit_cmd_debug(struct intel_queue *queue,
202 struct intel_cmd *cmd)
203{
204 uint32_t active[2], pending[2];
205 struct intel_bo *bo;
206 XGL_GPU_SIZE used;
207 XGL_RESULT ret;
208
209 ret = queue_submit_cmd_prepare(queue, cmd);
210 if (ret != XGL_SUCCESS)
211 return ret;
212
213 if (intel_debug & INTEL_DEBUG_HANG) {
214 intel_winsys_read_reset_stats(queue->dev->winsys,
215 &active[0], &pending[0]);
216 }
217
218 bo = intel_cmd_get_batch(cmd, &used);
219 ret = queue_submit_bo(queue, bo, used);
220 if (ret != XGL_SUCCESS)
221 return ret;
222
223 if (intel_debug & INTEL_DEBUG_HANG) {
224 intel_bo_wait(bo, -1);
225 intel_winsys_read_reset_stats(queue->dev->winsys,
226 &active[1], &pending[1]);
227
228 if (active[0] != active[1] || pending[0] != pending[1]) {
229 queue_submit_hang(queue, cmd, active[1] - active[0],
230 pending[1] - pending[0]);
231 }
232 }
233
234 if (intel_debug & INTEL_DEBUG_BATCH)
235 intel_cmd_decode(cmd, false);
236
237 return XGL_SUCCESS;
238}
239
240static XGL_RESULT queue_submit_cmd(struct intel_queue *queue,
241 struct intel_cmd *cmd)
242{
243 struct intel_bo *bo;
244 XGL_GPU_SIZE used;
245 XGL_RESULT ret;
246
247 ret = queue_submit_cmd_prepare(queue, cmd);
248 if (ret == XGL_SUCCESS) {
249 bo = intel_cmd_get_batch(cmd, &used);
250 ret = queue_submit_bo(queue, bo, used);
251 }
252
253 return ret;
254}
255
Chia-I Wu9ae59c12014-08-07 10:08:49 +0800256XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +0800257 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +0800258 struct intel_queue **queue_ret)
Chia-I Wue09b5362014-08-07 09:25:14 +0800259{
260 struct intel_queue *queue;
Chia-I Wuc5438c22014-08-19 14:03:06 +0800261 enum intel_ring_type ring;
262
Chia-I Wucdcff732014-08-19 14:44:15 +0800263 switch (engine) {
264 case INTEL_GPU_ENGINE_3D:
Chia-I Wuc5438c22014-08-19 14:03:06 +0800265 ring = INTEL_RING_RENDER;
266 break;
Chia-I Wuc5438c22014-08-19 14:03:06 +0800267 default:
268 return XGL_ERROR_INVALID_VALUE;
269 break;
270 }
Chia-I Wue09b5362014-08-07 09:25:14 +0800271
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600272 queue = (struct intel_queue *) intel_base_create(dev, sizeof(*queue),
Chia-I Wubbf2c932014-08-07 12:20:08 +0800273 dev->base.dbg, XGL_DBG_OBJECT_QUEUE, NULL, 0);
Chia-I Wue09b5362014-08-07 09:25:14 +0800274 if (!queue)
Chia-I Wu9ae59c12014-08-07 10:08:49 +0800275 return XGL_ERROR_OUT_OF_MEMORY;
Chia-I Wue09b5362014-08-07 09:25:14 +0800276
Chia-I Wue09b5362014-08-07 09:25:14 +0800277 queue->dev = dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +0800278 queue->ring = ring;
Chia-I Wue09b5362014-08-07 09:25:14 +0800279
Chia-I Wuec841722014-08-25 22:36:01 +0800280 if (queue_init_hw_and_atomic_bo(queue) != XGL_SUCCESS) {
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800281 intel_queue_destroy(queue);
Chia-I Wu63883292014-08-25 13:50:26 +0800282 return XGL_ERROR_INITIALIZATION_FAILED;
Chia-I Wu3ad3c542014-08-25 11:09:17 +0800283 }
284
Chia-I Wu9ae59c12014-08-07 10:08:49 +0800285 *queue_ret = queue;
286
287 return XGL_SUCCESS;
Chia-I Wue09b5362014-08-07 09:25:14 +0800288}
289
290void intel_queue_destroy(struct intel_queue *queue)
291{
Chia-I Wu63883292014-08-25 13:50:26 +0800292 if (queue->atomic_bo)
293 intel_bo_unreference(queue->atomic_bo);
294 if (queue->select_graphics_bo)
295 intel_bo_unreference(queue->select_graphics_bo);
296 if (queue->select_compute_bo)
297 intel_bo_unreference(queue->select_compute_bo);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800298 intel_base_destroy(&queue->base);
Chia-I Wue09b5362014-08-07 09:25:14 +0800299}
300
301XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout)
302{
Chia-I Wue24c3292014-08-21 14:05:23 +0800303 struct intel_bo *bo = (queue->last_submitted_cmd) ?
304 intel_cmd_get_batch(queue->last_submitted_cmd, NULL) : NULL;
Chia-I Wue09b5362014-08-07 09:25:14 +0800305
Chia-I Wue24c3292014-08-21 14:05:23 +0800306 return (!bo || intel_bo_wait(bo, timeout) == 0) ?
Chia-I Wue09b5362014-08-07 09:25:14 +0800307 XGL_SUCCESS : XGL_ERROR_UNKNOWN;
308}
309
Chia-I Wu96177272015-01-03 15:27:41 +0800310ICD_EXPORT XGL_RESULT XGLAPI xglQueueSetGlobalMemReferences(
Chia-I Wue09b5362014-08-07 09:25:14 +0800311 XGL_QUEUE queue,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600312 uint32_t memRefCount,
Chia-I Wue09b5362014-08-07 09:25:14 +0800313 const XGL_MEMORY_REF* pMemRefs)
314{
315 /*
316 * The winwys maintains the list of memory references. These are ignored
317 * until we move away from the winsys.
318 */
319 return XGL_SUCCESS;
320}
321
Chia-I Wu96177272015-01-03 15:27:41 +0800322ICD_EXPORT XGL_RESULT XGLAPI xglQueueWaitIdle(
Chia-I Wue09b5362014-08-07 09:25:14 +0800323 XGL_QUEUE queue_)
324{
325 struct intel_queue *queue = intel_queue(queue_);
326
327 return intel_queue_wait(queue, -1);
328}
Chia-I Wu251e7d92014-08-19 13:35:42 +0800329
Chia-I Wu96177272015-01-03 15:27:41 +0800330ICD_EXPORT XGL_RESULT XGLAPI xglQueueSubmit(
Chia-I Wuc5438c22014-08-19 14:03:06 +0800331 XGL_QUEUE queue_,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600332 uint32_t cmdBufferCount,
Chia-I Wu251e7d92014-08-19 13:35:42 +0800333 const XGL_CMD_BUFFER* pCmdBuffers,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600334 uint32_t memRefCount,
Chia-I Wu251e7d92014-08-19 13:35:42 +0800335 const XGL_MEMORY_REF* pMemRefs,
Chia-I Wuc5438c22014-08-19 14:03:06 +0800336 XGL_FENCE fence_)
Chia-I Wu251e7d92014-08-19 13:35:42 +0800337{
Chia-I Wuc5438c22014-08-19 14:03:06 +0800338 struct intel_queue *queue = intel_queue(queue_);
339 XGL_RESULT ret = XGL_SUCCESS;
Chia-I Wude6f9a72015-02-17 14:11:29 -0700340 struct intel_cmd *last_cmd;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600341 uint32_t i;
Chia-I Wuc5438c22014-08-19 14:03:06 +0800342
Chia-I Wuc5438c22014-08-19 14:03:06 +0800343 /* XGL_MEMORY_REFs are ignored as the winsys already knows them */
Chia-I Wude6f9a72015-02-17 14:11:29 -0700344 if (unlikely(intel_debug)) {
345 for (i = 0; i < cmdBufferCount; i++) {
346 struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
347 ret = queue_submit_cmd_debug(queue, cmd);
348 if (ret != XGL_SUCCESS)
349 break;
350 }
351 } else {
352 for (i = 0; i < cmdBufferCount; i++) {
353 struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
354 ret = queue_submit_cmd(queue, cmd);
355 if (ret != XGL_SUCCESS)
356 break;
357 }
358 }
359
360 /* no cmd submitted */
361 if (i == 0)
362 return ret;
363
364 last_cmd = intel_cmd(pCmdBuffers[i - 1]);
365
366 if (ret == XGL_SUCCESS) {
367 queue->last_submitted_cmd = last_cmd;
368
369 if (fence_ != XGL_NULL_HANDLE) {
370 struct intel_fence *fence = intel_fence(fence_);
371 intel_fence_set_cmd(fence, last_cmd);
372 }
373 } else {
374 struct intel_bo *last_bo;
375
376 /* unbusy submitted BOs */
377 last_bo = intel_cmd_get_batch(last_cmd, NULL);
378 intel_bo_wait(last_bo, -1);
379 }
Chia-I Wuc5438c22014-08-19 14:03:06 +0800380
381 return ret;
Chia-I Wu251e7d92014-08-19 13:35:42 +0800382}
383
Chia-I Wu96177272015-01-03 15:27:41 +0800384ICD_EXPORT XGL_RESULT XGLAPI xglOpenSharedQueueSemaphore(
Chia-I Wu251e7d92014-08-19 13:35:42 +0800385 XGL_DEVICE device,
386 const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo,
387 XGL_QUEUE_SEMAPHORE* pSemaphore)
388{
389 return XGL_ERROR_UNAVAILABLE;
390}
391
Chia-I Wu96177272015-01-03 15:27:41 +0800392ICD_EXPORT XGL_RESULT XGLAPI xglCreateQueueSemaphore(
Chia-I Wu251e7d92014-08-19 13:35:42 +0800393 XGL_DEVICE device,
394 const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo,
395 XGL_QUEUE_SEMAPHORE* pSemaphore)
396{
397 /*
398 * We want to find an unused semaphore register and initialize it. Signal
399 * will increment the register. Wait will atomically decrement it and
400 * block if the value is zero, or a large constant N if we do not want to
401 * go negative.
402 *
403 * XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility.
404 */
405 return XGL_ERROR_UNAVAILABLE;
406}
407
Chia-I Wu96177272015-01-03 15:27:41 +0800408ICD_EXPORT XGL_RESULT XGLAPI xglSignalQueueSemaphore(
Chia-I Wu251e7d92014-08-19 13:35:42 +0800409 XGL_QUEUE queue,
410 XGL_QUEUE_SEMAPHORE semaphore)
411{
412 return XGL_ERROR_UNAVAILABLE;
413}
414
Chia-I Wu96177272015-01-03 15:27:41 +0800415ICD_EXPORT XGL_RESULT XGLAPI xglWaitQueueSemaphore(
Chia-I Wu251e7d92014-08-19 13:35:42 +0800416 XGL_QUEUE queue,
417 XGL_QUEUE_SEMAPHORE semaphore)
418{
419 return XGL_ERROR_UNAVAILABLE;
420}