blob: 8792e917e9162d8c258f89fee358a02c0e7a7bcf [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
73 } mem_view;
74
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
87};
Chia-I Wu09142132014-08-11 15:42:55 +080088
Chia-I Wue24c3292014-08-21 14:05:23 +080089struct intel_cmd_writer {
90 struct intel_bo *bo;
91 void *ptr_opaque;
92
93 /* in DWords */
94 XGL_UINT size;
95 XGL_UINT used;
96};
97
Chia-I Wu730e5362014-08-19 12:15:09 +080098struct intel_cmd {
99 struct intel_obj obj;
100
101 struct intel_dev *dev;
102
Chia-I Wu343b1372014-08-20 16:39:20 +0800103 struct intel_cmd_reloc *relocs;
104 XGL_UINT reloc_count;
105
Chia-I Wu730e5362014-08-19 12:15:09 +0800106 XGL_FLAGS flags;
107
Chia-I Wue24c3292014-08-21 14:05:23 +0800108 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800109 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800110 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800111
Chia-I Wu343b1372014-08-20 16:39:20 +0800112 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800113 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800114
115 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800116};
117
118static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
119{
120 return (struct intel_cmd *) cmd;
121}
122
123static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
124{
125 return (struct intel_cmd *) obj;
126}
127
128XGL_RESULT intel_cmd_create(struct intel_dev *dev,
129 const XGL_CMD_BUFFER_CREATE_INFO *info,
130 struct intel_cmd **cmd_ret);
131void intel_cmd_destroy(struct intel_cmd *cmd);
132
133XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
134XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
135
Chia-I Wue24c3292014-08-21 14:05:23 +0800136static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
137 XGL_GPU_SIZE *used)
138{
139 const struct intel_cmd_writer *writer = &cmd->batch;
140
141 if (used)
142 *used = sizeof(uint32_t) * writer->used;
143
144 return writer->bo;
145}
146
Chia-I Wu09142132014-08-11 15:42:55 +0800147XGL_RESULT XGLAPI intelCreateCommandBuffer(
148 XGL_DEVICE device,
149 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
150 XGL_CMD_BUFFER* pCmdBuffer);
151
152XGL_RESULT XGLAPI intelBeginCommandBuffer(
153 XGL_CMD_BUFFER cmdBuffer,
154 XGL_FLAGS flags);
155
156XGL_RESULT XGLAPI intelEndCommandBuffer(
157 XGL_CMD_BUFFER cmdBuffer);
158
159XGL_RESULT XGLAPI intelResetCommandBuffer(
160 XGL_CMD_BUFFER cmdBuffer);
161
162XGL_VOID XGLAPI intelCmdBindPipeline(
163 XGL_CMD_BUFFER cmdBuffer,
164 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
165 XGL_PIPELINE pipeline);
166
167XGL_VOID XGLAPI intelCmdBindPipelineDelta(
168 XGL_CMD_BUFFER cmdBuffer,
169 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
170 XGL_PIPELINE_DELTA delta);
171
172XGL_VOID XGLAPI intelCmdBindStateObject(
173 XGL_CMD_BUFFER cmdBuffer,
174 XGL_STATE_BIND_POINT stateBindPoint,
175 XGL_STATE_OBJECT state);
176
177XGL_VOID XGLAPI intelCmdBindDescriptorSet(
178 XGL_CMD_BUFFER cmdBuffer,
179 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
180 XGL_UINT index,
181 XGL_DESCRIPTOR_SET descriptorSet,
182 XGL_UINT slotOffset);
183
184XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
185 XGL_CMD_BUFFER cmdBuffer,
186 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
187 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
188
189XGL_VOID XGLAPI intelCmdBindIndexData(
190 XGL_CMD_BUFFER cmdBuffer,
191 XGL_GPU_MEMORY mem,
192 XGL_GPU_SIZE offset,
193 XGL_INDEX_TYPE indexType);
194
195XGL_VOID XGLAPI intelCmdBindAttachments(
196 XGL_CMD_BUFFER cmdBuffer,
197 XGL_UINT colorAttachmentCount,
198 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
199 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
200
201XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
202 XGL_CMD_BUFFER cmdBuffer,
203 XGL_UINT transitionCount,
204 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
205
206XGL_VOID XGLAPI intelCmdPrepareImages(
207 XGL_CMD_BUFFER cmdBuffer,
208 XGL_UINT transitionCount,
209 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
210
211XGL_VOID XGLAPI intelCmdDraw(
212 XGL_CMD_BUFFER cmdBuffer,
213 XGL_UINT firstVertex,
214 XGL_UINT vertexCount,
215 XGL_UINT firstInstance,
216 XGL_UINT instanceCount);
217
218XGL_VOID XGLAPI intelCmdDrawIndexed(
219 XGL_CMD_BUFFER cmdBuffer,
220 XGL_UINT firstIndex,
221 XGL_UINT indexCount,
222 XGL_INT vertexOffset,
223 XGL_UINT firstInstance,
224 XGL_UINT instanceCount);
225
226XGL_VOID XGLAPI intelCmdDrawIndirect(
227 XGL_CMD_BUFFER cmdBuffer,
228 XGL_GPU_MEMORY mem,
229 XGL_GPU_SIZE offset,
230 XGL_UINT32 count,
231 XGL_UINT32 stride);
232
233XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
234 XGL_CMD_BUFFER cmdBuffer,
235 XGL_GPU_MEMORY mem,
236 XGL_GPU_SIZE offset,
237 XGL_UINT32 count,
238 XGL_UINT32 stride);
239
240XGL_VOID XGLAPI intelCmdDispatch(
241 XGL_CMD_BUFFER cmdBuffer,
242 XGL_UINT x,
243 XGL_UINT y,
244 XGL_UINT z);
245
246XGL_VOID XGLAPI intelCmdDispatchIndirect(
247 XGL_CMD_BUFFER cmdBuffer,
248 XGL_GPU_MEMORY mem,
249 XGL_GPU_SIZE offset);
250
251XGL_VOID XGLAPI intelCmdCopyMemory(
252 XGL_CMD_BUFFER cmdBuffer,
253 XGL_GPU_MEMORY srcMem,
254 XGL_GPU_MEMORY destMem,
255 XGL_UINT regionCount,
256 const XGL_MEMORY_COPY* pRegions);
257
258XGL_VOID XGLAPI intelCmdCopyImage(
259 XGL_CMD_BUFFER cmdBuffer,
260 XGL_IMAGE srcImage,
261 XGL_IMAGE destImage,
262 XGL_UINT regionCount,
263 const XGL_IMAGE_COPY* pRegions);
264
265XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
266 XGL_CMD_BUFFER cmdBuffer,
267 XGL_GPU_MEMORY srcMem,
268 XGL_IMAGE destImage,
269 XGL_UINT regionCount,
270 const XGL_MEMORY_IMAGE_COPY* pRegions);
271
272XGL_VOID XGLAPI intelCmdCopyImageToMemory(
273 XGL_CMD_BUFFER cmdBuffer,
274 XGL_IMAGE srcImage,
275 XGL_GPU_MEMORY destMem,
276 XGL_UINT regionCount,
277 const XGL_MEMORY_IMAGE_COPY* pRegions);
278
279XGL_VOID XGLAPI intelCmdCloneImageData(
280 XGL_CMD_BUFFER cmdBuffer,
281 XGL_IMAGE srcImage,
282 XGL_IMAGE_STATE srcImageState,
283 XGL_IMAGE destImage,
284 XGL_IMAGE_STATE destImageState);
285
286XGL_VOID XGLAPI intelCmdUpdateMemory(
287 XGL_CMD_BUFFER cmdBuffer,
288 XGL_GPU_MEMORY destMem,
289 XGL_GPU_SIZE destOffset,
290 XGL_GPU_SIZE dataSize,
291 const XGL_UINT32* pData);
292
293XGL_VOID XGLAPI intelCmdFillMemory(
294 XGL_CMD_BUFFER cmdBuffer,
295 XGL_GPU_MEMORY destMem,
296 XGL_GPU_SIZE destOffset,
297 XGL_GPU_SIZE fillSize,
298 XGL_UINT32 data);
299
300XGL_VOID XGLAPI intelCmdClearColorImage(
301 XGL_CMD_BUFFER cmdBuffer,
302 XGL_IMAGE image,
303 const XGL_FLOAT color[4],
304 XGL_UINT rangeCount,
305 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
306
307XGL_VOID XGLAPI intelCmdClearColorImageRaw(
308 XGL_CMD_BUFFER cmdBuffer,
309 XGL_IMAGE image,
310 const XGL_UINT32 color[4],
311 XGL_UINT rangeCount,
312 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
313
314XGL_VOID XGLAPI intelCmdClearDepthStencil(
315 XGL_CMD_BUFFER cmdBuffer,
316 XGL_IMAGE image,
317 XGL_FLOAT depth,
318 XGL_UINT32 stencil,
319 XGL_UINT rangeCount,
320 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
321
322XGL_VOID XGLAPI intelCmdResolveImage(
323 XGL_CMD_BUFFER cmdBuffer,
324 XGL_IMAGE srcImage,
325 XGL_IMAGE destImage,
326 XGL_UINT rectCount,
327 const XGL_IMAGE_RESOLVE* pRects);
328
329XGL_VOID XGLAPI intelCmdSetEvent(
330 XGL_CMD_BUFFER cmdBuffer,
331 XGL_EVENT event);
332
333XGL_VOID XGLAPI intelCmdResetEvent(
334 XGL_CMD_BUFFER cmdBuffer,
335 XGL_EVENT event);
336
337XGL_VOID XGLAPI intelCmdMemoryAtomic(
338 XGL_CMD_BUFFER cmdBuffer,
339 XGL_GPU_MEMORY destMem,
340 XGL_GPU_SIZE destOffset,
341 XGL_UINT64 srcData,
342 XGL_ATOMIC_OP atomicOp);
343
344XGL_VOID XGLAPI intelCmdBeginQuery(
345 XGL_CMD_BUFFER cmdBuffer,
346 XGL_QUERY_POOL queryPool,
347 XGL_UINT slot,
348 XGL_FLAGS flags);
349
350XGL_VOID XGLAPI intelCmdEndQuery(
351 XGL_CMD_BUFFER cmdBuffer,
352 XGL_QUERY_POOL queryPool,
353 XGL_UINT slot);
354
355XGL_VOID XGLAPI intelCmdResetQueryPool(
356 XGL_CMD_BUFFER cmdBuffer,
357 XGL_QUERY_POOL queryPool,
358 XGL_UINT startQuery,
359 XGL_UINT queryCount);
360
361XGL_VOID XGLAPI intelCmdWriteTimestamp(
362 XGL_CMD_BUFFER cmdBuffer,
363 XGL_TIMESTAMP_TYPE timestampType,
364 XGL_GPU_MEMORY destMem,
365 XGL_GPU_SIZE destOffset);
366
367XGL_VOID XGLAPI intelCmdInitAtomicCounters(
368 XGL_CMD_BUFFER cmdBuffer,
369 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
370 XGL_UINT startCounter,
371 XGL_UINT counterCount,
372 const XGL_UINT32* pData);
373
374XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
375 XGL_CMD_BUFFER cmdBuffer,
376 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
377 XGL_UINT startCounter,
378 XGL_UINT counterCount,
379 XGL_GPU_MEMORY srcMem,
380 XGL_GPU_SIZE srcOffset);
381
382XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
383 XGL_CMD_BUFFER cmdBuffer,
384 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
385 XGL_UINT startCounter,
386 XGL_UINT counterCount,
387 XGL_GPU_MEMORY destMem,
388 XGL_GPU_SIZE destOffset);
389
390XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
391 XGL_CMD_BUFFER cmdBuffer,
392 const XGL_CHAR* pMarker);
393
394XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
395 XGL_CMD_BUFFER cmdBuffer);
396
397#endif /* CMD_H */