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Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "kmd/winsys.h"
Chia-I Wu34f45182014-08-19 14:02:59 +080026#include "cmd.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080027#include "dev.h"
Chia-I Wuc5438c22014-08-19 14:03:06 +080028#include "fence.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080029#include "queue.h"
30
Chia-I Wu94d2fba2014-08-25 11:38:08 +080031static XGL_RESULT queue_submit_bo(struct intel_queue *queue,
32 struct intel_bo *bo,
33 XGL_GPU_SIZE used)
34{
35 struct intel_winsys *winsys = queue->dev->winsys;
36 int err;
37
38 if (intel_debug & INTEL_DEBUG_BATCH)
39 intel_winsys_decode_bo(winsys, bo, used);
40
41 if (intel_debug & INTEL_DEBUG_NOHW)
42 err = 0;
43 else
44 err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0);
45
46 return (err) ? XGL_ERROR_UNKNOWN : XGL_SUCCESS;
47}
48
Chia-I Wu9ae59c12014-08-07 10:08:49 +080049XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +080050 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +080051 struct intel_queue **queue_ret)
Chia-I Wue09b5362014-08-07 09:25:14 +080052{
53 struct intel_queue *queue;
Chia-I Wuc5438c22014-08-19 14:03:06 +080054 enum intel_ring_type ring;
55
Chia-I Wucdcff732014-08-19 14:44:15 +080056 switch (engine) {
57 case INTEL_GPU_ENGINE_3D:
Chia-I Wuc5438c22014-08-19 14:03:06 +080058 ring = INTEL_RING_RENDER;
59 break;
Chia-I Wuc5438c22014-08-19 14:03:06 +080060 default:
61 return XGL_ERROR_INVALID_VALUE;
62 break;
63 }
Chia-I Wue09b5362014-08-07 09:25:14 +080064
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060065 queue = (struct intel_queue *) intel_base_create(dev, sizeof(*queue),
Chia-I Wubbf2c932014-08-07 12:20:08 +080066 dev->base.dbg, XGL_DBG_OBJECT_QUEUE, NULL, 0);
Chia-I Wue09b5362014-08-07 09:25:14 +080067 if (!queue)
Chia-I Wu9ae59c12014-08-07 10:08:49 +080068 return XGL_ERROR_OUT_OF_MEMORY;
Chia-I Wue09b5362014-08-07 09:25:14 +080069
Chia-I Wue09b5362014-08-07 09:25:14 +080070 queue->dev = dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +080071 queue->ring = ring;
Chia-I Wue09b5362014-08-07 09:25:14 +080072
Chia-I Wu9ae59c12014-08-07 10:08:49 +080073 *queue_ret = queue;
74
75 return XGL_SUCCESS;
Chia-I Wue09b5362014-08-07 09:25:14 +080076}
77
78void intel_queue_destroy(struct intel_queue *queue)
79{
Chia-I Wubbf2c932014-08-07 12:20:08 +080080 intel_base_destroy(&queue->base);
Chia-I Wue09b5362014-08-07 09:25:14 +080081}
82
83XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout)
84{
Chia-I Wue24c3292014-08-21 14:05:23 +080085 struct intel_bo *bo = (queue->last_submitted_cmd) ?
86 intel_cmd_get_batch(queue->last_submitted_cmd, NULL) : NULL;
Chia-I Wue09b5362014-08-07 09:25:14 +080087
Chia-I Wue24c3292014-08-21 14:05:23 +080088 return (!bo || intel_bo_wait(bo, timeout) == 0) ?
Chia-I Wue09b5362014-08-07 09:25:14 +080089 XGL_SUCCESS : XGL_ERROR_UNKNOWN;
90}
91
92XGL_RESULT XGLAPI intelQueueSetGlobalMemReferences(
93 XGL_QUEUE queue,
94 XGL_UINT memRefCount,
95 const XGL_MEMORY_REF* pMemRefs)
96{
97 /*
98 * The winwys maintains the list of memory references. These are ignored
99 * until we move away from the winsys.
100 */
101 return XGL_SUCCESS;
102}
103
104XGL_RESULT XGLAPI intelQueueWaitIdle(
105 XGL_QUEUE queue_)
106{
107 struct intel_queue *queue = intel_queue(queue_);
108
109 return intel_queue_wait(queue, -1);
110}
Chia-I Wu251e7d92014-08-19 13:35:42 +0800111
112XGL_RESULT XGLAPI intelQueueSubmit(
Chia-I Wuc5438c22014-08-19 14:03:06 +0800113 XGL_QUEUE queue_,
Chia-I Wu251e7d92014-08-19 13:35:42 +0800114 XGL_UINT cmdBufferCount,
115 const XGL_CMD_BUFFER* pCmdBuffers,
116 XGL_UINT memRefCount,
117 const XGL_MEMORY_REF* pMemRefs,
Chia-I Wuc5438c22014-08-19 14:03:06 +0800118 XGL_FENCE fence_)
Chia-I Wu251e7d92014-08-19 13:35:42 +0800119{
Chia-I Wuc5438c22014-08-19 14:03:06 +0800120 struct intel_queue *queue = intel_queue(queue_);
121 XGL_RESULT ret = XGL_SUCCESS;
122 XGL_UINT i;
123
124 for (i = 0; i < cmdBufferCount; i++) {
125 struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
Chia-I Wu94d2fba2014-08-25 11:38:08 +0800126 struct intel_bo *bo;
127 XGL_GPU_SIZE used;
128 XGL_RESULT ret;
Chia-I Wuc5438c22014-08-19 14:03:06 +0800129
Chia-I Wu94d2fba2014-08-25 11:38:08 +0800130 bo = intel_cmd_get_batch(cmd, &used);
131 ret = queue_submit_bo(queue, bo, used);
132 queue->last_submitted_cmd = cmd;
133
Chia-I Wuc5438c22014-08-19 14:03:06 +0800134 if (ret != XGL_SUCCESS)
135 break;
136 }
137
138 if (ret == XGL_SUCCESS && fence_ != XGL_NULL_HANDLE) {
139 struct intel_fence *fence = intel_fence(fence_);
140 intel_fence_set_cmd(fence, queue->last_submitted_cmd);
141 }
142
143 /* XGL_MEMORY_REFs are ignored as the winsys already knows them */
144
145 return ret;
Chia-I Wu251e7d92014-08-19 13:35:42 +0800146}
147
148XGL_RESULT XGLAPI intelOpenSharedQueueSemaphore(
149 XGL_DEVICE device,
150 const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo,
151 XGL_QUEUE_SEMAPHORE* pSemaphore)
152{
153 return XGL_ERROR_UNAVAILABLE;
154}
155
156XGL_RESULT XGLAPI intelCreateQueueSemaphore(
157 XGL_DEVICE device,
158 const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo,
159 XGL_QUEUE_SEMAPHORE* pSemaphore)
160{
161 /*
162 * We want to find an unused semaphore register and initialize it. Signal
163 * will increment the register. Wait will atomically decrement it and
164 * block if the value is zero, or a large constant N if we do not want to
165 * go negative.
166 *
167 * XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility.
168 */
169 return XGL_ERROR_UNAVAILABLE;
170}
171
172XGL_RESULT XGLAPI intelSignalQueueSemaphore(
173 XGL_QUEUE queue,
174 XGL_QUEUE_SEMAPHORE semaphore)
175{
176 return XGL_ERROR_UNAVAILABLE;
177}
178
179XGL_RESULT XGLAPI intelWaitQueueSemaphore(
180 XGL_QUEUE queue,
181 XGL_QUEUE_SEMAPHORE semaphore)
182{
183 return XGL_ERROR_UNAVAILABLE;
184}