Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 28 | #include "genhw/genhw.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 29 | #include "kmd/winsys.h" |
Chia-I Wu | 34f4518 | 2014-08-19 14:02:59 +0800 | [diff] [blame] | 30 | #include "cmd.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 31 | #include "dev.h" |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 32 | #include "fence.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 33 | #include "queue.h" |
| 34 | |
Chia-I Wu | 465fe21 | 2015-02-11 11:27:06 -0700 | [diff] [blame] | 35 | static void queue_submit_hang(struct intel_queue *queue, |
| 36 | struct intel_cmd *cmd, |
| 37 | uint32_t active_lost, |
| 38 | uint32_t pending_lost) |
| 39 | { |
| 40 | intel_cmd_decode(cmd, true); |
| 41 | |
| 42 | intel_dev_log(queue->dev, XGL_DBG_MSG_ERROR, |
| 43 | XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0, |
| 44 | "GPU hanged with %d/%d active/pending command buffers lost", |
| 45 | active_lost, pending_lost); |
| 46 | } |
| 47 | |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 48 | static XGL_RESULT queue_submit_bo(struct intel_queue *queue, |
| 49 | struct intel_bo *bo, |
| 50 | XGL_GPU_SIZE used) |
| 51 | { |
| 52 | struct intel_winsys *winsys = queue->dev->winsys; |
| 53 | int err; |
| 54 | |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 55 | if (intel_debug & INTEL_DEBUG_NOHW) |
| 56 | err = 0; |
| 57 | else |
| 58 | err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0); |
| 59 | |
| 60 | return (err) ? XGL_ERROR_UNKNOWN : XGL_SUCCESS; |
| 61 | } |
| 62 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 63 | static struct intel_bo *queue_create_bo(struct intel_queue *queue, |
| 64 | XGL_GPU_SIZE size, |
| 65 | const void *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 66 | size_t cmd_len) |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 67 | { |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 68 | struct intel_bo *bo; |
| 69 | void *ptr; |
| 70 | |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 71 | bo = intel_winsys_alloc_bo(queue->dev->winsys, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 72 | "queue bo", size, true); |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 73 | if (!bo) |
| 74 | return NULL; |
| 75 | |
| 76 | if (!cmd_len) |
| 77 | return bo; |
| 78 | |
| 79 | ptr = intel_bo_map(bo, true); |
| 80 | if (!ptr) { |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 81 | intel_bo_unref(bo); |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 82 | return NULL; |
| 83 | } |
| 84 | |
| 85 | memcpy(ptr, cmd, cmd_len); |
| 86 | intel_bo_unmap(bo); |
| 87 | |
| 88 | return bo; |
| 89 | } |
| 90 | |
| 91 | static XGL_RESULT queue_select_pipeline(struct intel_queue *queue, |
| 92 | int pipeline_select) |
| 93 | { |
| 94 | uint32_t pipeline_select_cmd[] = { |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 95 | GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT), |
| 96 | GEN6_MI_CMD(MI_BATCH_BUFFER_END), |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 97 | }; |
| 98 | struct intel_bo *bo; |
| 99 | XGL_RESULT ret; |
| 100 | |
| 101 | if (queue->ring != INTEL_RING_RENDER || |
| 102 | queue->last_pipeline_select == pipeline_select) |
| 103 | return XGL_SUCCESS; |
| 104 | |
| 105 | switch (pipeline_select) { |
| 106 | case GEN6_PIPELINE_SELECT_DW0_SELECT_3D: |
| 107 | bo = queue->select_graphics_bo; |
| 108 | break; |
| 109 | case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA: |
| 110 | bo = queue->select_compute_bo; |
| 111 | break; |
| 112 | default: |
| 113 | return XGL_ERROR_INVALID_VALUE; |
| 114 | break; |
| 115 | } |
| 116 | |
| 117 | if (!bo) { |
| 118 | pipeline_select_cmd[0] |= pipeline_select; |
| 119 | bo = queue_create_bo(queue, sizeof(pipeline_select_cmd), |
| 120 | pipeline_select_cmd, sizeof(pipeline_select_cmd)); |
| 121 | if (!bo) |
| 122 | return XGL_ERROR_OUT_OF_GPU_MEMORY; |
| 123 | |
| 124 | switch (pipeline_select) { |
| 125 | case GEN6_PIPELINE_SELECT_DW0_SELECT_3D: |
| 126 | queue->select_graphics_bo = bo; |
| 127 | break; |
| 128 | case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA: |
| 129 | queue->select_compute_bo = bo; |
| 130 | break; |
| 131 | default: |
| 132 | break; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | ret = queue_submit_bo(queue, bo, sizeof(pipeline_select_cmd)); |
| 137 | if (ret == XGL_SUCCESS) |
| 138 | queue->last_pipeline_select = pipeline_select; |
| 139 | |
| 140 | return ret; |
| 141 | } |
| 142 | |
| 143 | static XGL_RESULT queue_init_hw_and_atomic_bo(struct intel_queue *queue) |
| 144 | { |
| 145 | const uint32_t ctx_init_cmd[] = { |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 146 | /* STATE_SIP */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 147 | GEN6_RENDER_CMD(COMMON, STATE_SIP), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 148 | 0, |
| 149 | /* PIPELINE_SELECT */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 150 | GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) | |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 151 | GEN6_PIPELINE_SELECT_DW0_SELECT_3D, |
| 152 | /* 3DSTATE_VF_STATISTICS */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 153 | GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 154 | /* end */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 155 | GEN6_MI_CMD(MI_BATCH_BUFFER_END), |
| 156 | GEN6_MI_CMD(MI_NOOP), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 157 | }; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 158 | struct intel_bo *bo; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 159 | XGL_RESULT ret; |
| 160 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 161 | if (queue->ring != INTEL_RING_RENDER) { |
| 162 | queue->last_pipeline_select = -1; |
| 163 | queue->atomic_bo = queue_create_bo(queue, |
| 164 | sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT, |
| 165 | NULL, 0); |
| 166 | return (queue->atomic_bo) ? XGL_SUCCESS : XGL_ERROR_OUT_OF_GPU_MEMORY; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 167 | } |
| 168 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 169 | bo = queue_create_bo(queue, |
| 170 | sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT, |
| 171 | ctx_init_cmd, sizeof(ctx_init_cmd)); |
| 172 | if (!bo) |
| 173 | return XGL_ERROR_OUT_OF_GPU_MEMORY; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 174 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 175 | ret = queue_submit_bo(queue, bo, sizeof(ctx_init_cmd)); |
| 176 | if (ret != XGL_SUCCESS) { |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 177 | intel_bo_unref(bo); |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 178 | return ret; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 179 | } |
| 180 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 181 | queue->last_pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D; |
| 182 | /* reuse */ |
| 183 | queue->atomic_bo = bo; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 184 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 185 | return XGL_SUCCESS; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 186 | } |
| 187 | |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 188 | static XGL_RESULT queue_submit_cmd_prepare(struct intel_queue *queue, |
| 189 | struct intel_cmd *cmd) |
| 190 | { |
| 191 | if (unlikely(cmd->result != XGL_SUCCESS)) { |
| 192 | intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR, |
| 193 | XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0, |
| 194 | "invalid command buffer submitted"); |
| 195 | return cmd->result; |
| 196 | } |
| 197 | |
| 198 | return queue_select_pipeline(queue, cmd->pipeline_select); |
| 199 | } |
| 200 | |
| 201 | static XGL_RESULT queue_submit_cmd_debug(struct intel_queue *queue, |
| 202 | struct intel_cmd *cmd) |
| 203 | { |
| 204 | uint32_t active[2], pending[2]; |
| 205 | struct intel_bo *bo; |
| 206 | XGL_GPU_SIZE used; |
| 207 | XGL_RESULT ret; |
| 208 | |
| 209 | ret = queue_submit_cmd_prepare(queue, cmd); |
| 210 | if (ret != XGL_SUCCESS) |
| 211 | return ret; |
| 212 | |
| 213 | if (intel_debug & INTEL_DEBUG_HANG) { |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 214 | intel_winsys_get_reset_stats(queue->dev->winsys, |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 215 | &active[0], &pending[0]); |
| 216 | } |
| 217 | |
| 218 | bo = intel_cmd_get_batch(cmd, &used); |
| 219 | ret = queue_submit_bo(queue, bo, used); |
| 220 | if (ret != XGL_SUCCESS) |
| 221 | return ret; |
| 222 | |
| 223 | if (intel_debug & INTEL_DEBUG_HANG) { |
| 224 | intel_bo_wait(bo, -1); |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 225 | intel_winsys_get_reset_stats(queue->dev->winsys, |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 226 | &active[1], &pending[1]); |
| 227 | |
| 228 | if (active[0] != active[1] || pending[0] != pending[1]) { |
| 229 | queue_submit_hang(queue, cmd, active[1] - active[0], |
| 230 | pending[1] - pending[0]); |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | if (intel_debug & INTEL_DEBUG_BATCH) |
| 235 | intel_cmd_decode(cmd, false); |
| 236 | |
| 237 | return XGL_SUCCESS; |
| 238 | } |
| 239 | |
| 240 | static XGL_RESULT queue_submit_cmd(struct intel_queue *queue, |
| 241 | struct intel_cmd *cmd) |
| 242 | { |
| 243 | struct intel_bo *bo; |
| 244 | XGL_GPU_SIZE used; |
| 245 | XGL_RESULT ret; |
| 246 | |
| 247 | ret = queue_submit_cmd_prepare(queue, cmd); |
| 248 | if (ret == XGL_SUCCESS) { |
| 249 | bo = intel_cmd_get_batch(cmd, &used); |
| 250 | ret = queue_submit_bo(queue, bo, used); |
| 251 | } |
| 252 | |
| 253 | return ret; |
| 254 | } |
| 255 | |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 256 | XGL_RESULT intel_queue_create(struct intel_dev *dev, |
Chia-I Wu | cdcff73 | 2014-08-19 14:44:15 +0800 | [diff] [blame] | 257 | enum intel_gpu_engine_type engine, |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 258 | struct intel_queue **queue_ret) |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 259 | { |
| 260 | struct intel_queue *queue; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 261 | enum intel_ring_type ring; |
| 262 | |
Chia-I Wu | cdcff73 | 2014-08-19 14:44:15 +0800 | [diff] [blame] | 263 | switch (engine) { |
| 264 | case INTEL_GPU_ENGINE_3D: |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 265 | ring = INTEL_RING_RENDER; |
| 266 | break; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 267 | default: |
| 268 | return XGL_ERROR_INVALID_VALUE; |
| 269 | break; |
| 270 | } |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 271 | |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 272 | queue = (struct intel_queue *) intel_base_create(&dev->base.handle, |
| 273 | sizeof(*queue), dev->base.dbg, XGL_DBG_OBJECT_QUEUE, NULL, 0); |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 274 | if (!queue) |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 275 | return XGL_ERROR_OUT_OF_MEMORY; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 276 | |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 277 | queue->dev = dev; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 278 | queue->ring = ring; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 279 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 280 | if (queue_init_hw_and_atomic_bo(queue) != XGL_SUCCESS) { |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 281 | intel_queue_destroy(queue); |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 282 | return XGL_ERROR_INITIALIZATION_FAILED; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 283 | } |
| 284 | |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 285 | *queue_ret = queue; |
| 286 | |
| 287 | return XGL_SUCCESS; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | void intel_queue_destroy(struct intel_queue *queue) |
| 291 | { |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 292 | intel_bo_unref(queue->seqno_bo); |
| 293 | intel_bo_unref(queue->atomic_bo); |
| 294 | intel_bo_unref(queue->select_graphics_bo); |
| 295 | intel_bo_unref(queue->select_compute_bo); |
Chia-I Wu | 046a7a9 | 2015-02-17 14:29:01 -0700 | [diff] [blame] | 296 | |
Chia-I Wu | bbf2c93 | 2014-08-07 12:20:08 +0800 | [diff] [blame] | 297 | intel_base_destroy(&queue->base); |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout) |
| 301 | { |
Chia-I Wu | 046a7a9 | 2015-02-17 14:29:01 -0700 | [diff] [blame] | 302 | if (!queue->seqno_bo) |
| 303 | return XGL_SUCCESS; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 304 | |
Chia-I Wu | 046a7a9 | 2015-02-17 14:29:01 -0700 | [diff] [blame] | 305 | return (intel_bo_wait(queue->seqno_bo, timeout) == 0) ? |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 306 | XGL_SUCCESS : XGL_ERROR_UNKNOWN; |
| 307 | } |
| 308 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 309 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueSetGlobalMemReferences( |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 310 | XGL_QUEUE queue, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 311 | uint32_t memRefCount, |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 312 | const XGL_MEMORY_REF* pMemRefs) |
| 313 | { |
| 314 | /* |
| 315 | * The winwys maintains the list of memory references. These are ignored |
| 316 | * until we move away from the winsys. |
| 317 | */ |
| 318 | return XGL_SUCCESS; |
| 319 | } |
| 320 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 321 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueWaitIdle( |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 322 | XGL_QUEUE queue_) |
| 323 | { |
| 324 | struct intel_queue *queue = intel_queue(queue_); |
| 325 | |
| 326 | return intel_queue_wait(queue, -1); |
| 327 | } |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 328 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 329 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueSubmit( |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 330 | XGL_QUEUE queue_, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 331 | uint32_t cmdBufferCount, |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 332 | const XGL_CMD_BUFFER* pCmdBuffers, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 333 | uint32_t memRefCount, |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 334 | const XGL_MEMORY_REF* pMemRefs, |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 335 | XGL_FENCE fence_) |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 336 | { |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 337 | struct intel_queue *queue = intel_queue(queue_); |
| 338 | XGL_RESULT ret = XGL_SUCCESS; |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 339 | struct intel_cmd *last_cmd; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 340 | uint32_t i; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 341 | |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 342 | /* XGL_MEMORY_REFs are ignored as the winsys already knows them */ |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 343 | if (unlikely(intel_debug)) { |
| 344 | for (i = 0; i < cmdBufferCount; i++) { |
| 345 | struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]); |
| 346 | ret = queue_submit_cmd_debug(queue, cmd); |
| 347 | if (ret != XGL_SUCCESS) |
| 348 | break; |
| 349 | } |
| 350 | } else { |
| 351 | for (i = 0; i < cmdBufferCount; i++) { |
| 352 | struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]); |
| 353 | ret = queue_submit_cmd(queue, cmd); |
| 354 | if (ret != XGL_SUCCESS) |
| 355 | break; |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | /* no cmd submitted */ |
| 360 | if (i == 0) |
| 361 | return ret; |
| 362 | |
| 363 | last_cmd = intel_cmd(pCmdBuffers[i - 1]); |
| 364 | |
| 365 | if (ret == XGL_SUCCESS) { |
Chia-I Wu | cb2dc0d | 2015-03-05 16:19:42 -0700 | [diff] [blame] | 366 | intel_bo_unref(queue->seqno_bo); |
| 367 | queue->seqno_bo = intel_bo_ref(intel_cmd_get_batch(last_cmd, NULL)); |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 368 | |
| 369 | if (fence_ != XGL_NULL_HANDLE) { |
| 370 | struct intel_fence *fence = intel_fence(fence_); |
Chia-I Wu | 046a7a9 | 2015-02-17 14:29:01 -0700 | [diff] [blame] | 371 | intel_fence_set_seqno(fence, queue->seqno_bo); |
Chia-I Wu | de6f9a7 | 2015-02-17 14:11:29 -0700 | [diff] [blame] | 372 | } |
| 373 | } else { |
| 374 | struct intel_bo *last_bo; |
| 375 | |
| 376 | /* unbusy submitted BOs */ |
| 377 | last_bo = intel_cmd_get_batch(last_cmd, NULL); |
| 378 | intel_bo_wait(last_bo, -1); |
| 379 | } |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 380 | |
| 381 | return ret; |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 382 | } |
| 383 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 384 | ICD_EXPORT XGL_RESULT XGLAPI xglOpenSharedQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 385 | XGL_DEVICE device, |
| 386 | const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo, |
| 387 | XGL_QUEUE_SEMAPHORE* pSemaphore) |
| 388 | { |
| 389 | return XGL_ERROR_UNAVAILABLE; |
| 390 | } |
| 391 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 392 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 393 | XGL_DEVICE device, |
| 394 | const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo, |
| 395 | XGL_QUEUE_SEMAPHORE* pSemaphore) |
| 396 | { |
| 397 | /* |
| 398 | * We want to find an unused semaphore register and initialize it. Signal |
| 399 | * will increment the register. Wait will atomically decrement it and |
| 400 | * block if the value is zero, or a large constant N if we do not want to |
| 401 | * go negative. |
| 402 | * |
| 403 | * XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility. |
| 404 | */ |
| 405 | return XGL_ERROR_UNAVAILABLE; |
| 406 | } |
| 407 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 408 | ICD_EXPORT XGL_RESULT XGLAPI xglSignalQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 409 | XGL_QUEUE queue, |
| 410 | XGL_QUEUE_SEMAPHORE semaphore) |
| 411 | { |
| 412 | return XGL_ERROR_UNAVAILABLE; |
| 413 | } |
| 414 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 415 | ICD_EXPORT XGL_RESULT XGLAPI xglWaitQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 416 | XGL_QUEUE queue, |
| 417 | XGL_QUEUE_SEMAPHORE semaphore) |
| 418 | { |
| 419 | return XGL_ERROR_UNAVAILABLE; |
| 420 | } |