Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 28 | #include "genhw/genhw.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 29 | #include "kmd/winsys.h" |
Chia-I Wu | 34f4518 | 2014-08-19 14:02:59 +0800 | [diff] [blame] | 30 | #include "cmd.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 31 | #include "dev.h" |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 32 | #include "fence.h" |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 33 | #include "queue.h" |
| 34 | |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 35 | static XGL_RESULT queue_submit_bo(struct intel_queue *queue, |
| 36 | struct intel_bo *bo, |
| 37 | XGL_GPU_SIZE used) |
| 38 | { |
| 39 | struct intel_winsys *winsys = queue->dev->winsys; |
| 40 | int err; |
| 41 | |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 42 | if (intel_debug & INTEL_DEBUG_NOHW) |
| 43 | err = 0; |
| 44 | else |
| 45 | err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0); |
| 46 | |
| 47 | return (err) ? XGL_ERROR_UNKNOWN : XGL_SUCCESS; |
| 48 | } |
| 49 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 50 | static struct intel_bo *queue_create_bo(struct intel_queue *queue, |
| 51 | XGL_GPU_SIZE size, |
| 52 | const void *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 53 | size_t cmd_len) |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 54 | { |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 55 | struct intel_bo *bo; |
| 56 | void *ptr; |
| 57 | |
| 58 | bo = intel_winsys_alloc_buffer(queue->dev->winsys, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 59 | "queue bo", size, true); |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 60 | if (!bo) |
| 61 | return NULL; |
| 62 | |
| 63 | if (!cmd_len) |
| 64 | return bo; |
| 65 | |
| 66 | ptr = intel_bo_map(bo, true); |
| 67 | if (!ptr) { |
| 68 | intel_bo_unreference(bo); |
| 69 | return NULL; |
| 70 | } |
| 71 | |
| 72 | memcpy(ptr, cmd, cmd_len); |
| 73 | intel_bo_unmap(bo); |
| 74 | |
| 75 | return bo; |
| 76 | } |
| 77 | |
| 78 | static XGL_RESULT queue_select_pipeline(struct intel_queue *queue, |
| 79 | int pipeline_select) |
| 80 | { |
| 81 | uint32_t pipeline_select_cmd[] = { |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 82 | GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT), |
| 83 | GEN6_MI_CMD(MI_BATCH_BUFFER_END), |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 84 | }; |
| 85 | struct intel_bo *bo; |
| 86 | XGL_RESULT ret; |
| 87 | |
| 88 | if (queue->ring != INTEL_RING_RENDER || |
| 89 | queue->last_pipeline_select == pipeline_select) |
| 90 | return XGL_SUCCESS; |
| 91 | |
| 92 | switch (pipeline_select) { |
| 93 | case GEN6_PIPELINE_SELECT_DW0_SELECT_3D: |
| 94 | bo = queue->select_graphics_bo; |
| 95 | break; |
| 96 | case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA: |
| 97 | bo = queue->select_compute_bo; |
| 98 | break; |
| 99 | default: |
| 100 | return XGL_ERROR_INVALID_VALUE; |
| 101 | break; |
| 102 | } |
| 103 | |
| 104 | if (!bo) { |
| 105 | pipeline_select_cmd[0] |= pipeline_select; |
| 106 | bo = queue_create_bo(queue, sizeof(pipeline_select_cmd), |
| 107 | pipeline_select_cmd, sizeof(pipeline_select_cmd)); |
| 108 | if (!bo) |
| 109 | return XGL_ERROR_OUT_OF_GPU_MEMORY; |
| 110 | |
| 111 | switch (pipeline_select) { |
| 112 | case GEN6_PIPELINE_SELECT_DW0_SELECT_3D: |
| 113 | queue->select_graphics_bo = bo; |
| 114 | break; |
| 115 | case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA: |
| 116 | queue->select_compute_bo = bo; |
| 117 | break; |
| 118 | default: |
| 119 | break; |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | ret = queue_submit_bo(queue, bo, sizeof(pipeline_select_cmd)); |
| 124 | if (ret == XGL_SUCCESS) |
| 125 | queue->last_pipeline_select = pipeline_select; |
| 126 | |
| 127 | return ret; |
| 128 | } |
| 129 | |
| 130 | static XGL_RESULT queue_init_hw_and_atomic_bo(struct intel_queue *queue) |
| 131 | { |
| 132 | const uint32_t ctx_init_cmd[] = { |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 133 | /* STATE_SIP */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 134 | GEN6_RENDER_CMD(COMMON, STATE_SIP), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 135 | 0, |
| 136 | /* PIPELINE_SELECT */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 137 | GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) | |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 138 | GEN6_PIPELINE_SELECT_DW0_SELECT_3D, |
| 139 | /* 3DSTATE_VF_STATISTICS */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 140 | GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 141 | /* end */ |
Chia-I Wu | 426072d | 2014-08-26 14:31:55 +0800 | [diff] [blame] | 142 | GEN6_MI_CMD(MI_BATCH_BUFFER_END), |
| 143 | GEN6_MI_CMD(MI_NOOP), |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 144 | }; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 145 | struct intel_bo *bo; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 146 | XGL_RESULT ret; |
| 147 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 148 | if (queue->ring != INTEL_RING_RENDER) { |
| 149 | queue->last_pipeline_select = -1; |
| 150 | queue->atomic_bo = queue_create_bo(queue, |
| 151 | sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT, |
| 152 | NULL, 0); |
| 153 | return (queue->atomic_bo) ? XGL_SUCCESS : XGL_ERROR_OUT_OF_GPU_MEMORY; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 154 | } |
| 155 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 156 | bo = queue_create_bo(queue, |
| 157 | sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT, |
| 158 | ctx_init_cmd, sizeof(ctx_init_cmd)); |
| 159 | if (!bo) |
| 160 | return XGL_ERROR_OUT_OF_GPU_MEMORY; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 161 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 162 | ret = queue_submit_bo(queue, bo, sizeof(ctx_init_cmd)); |
| 163 | if (ret != XGL_SUCCESS) { |
| 164 | intel_bo_unreference(bo); |
| 165 | return ret; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 166 | } |
| 167 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 168 | queue->last_pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D; |
| 169 | /* reuse */ |
| 170 | queue->atomic_bo = bo; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 171 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 172 | return XGL_SUCCESS; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 173 | } |
| 174 | |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 175 | XGL_RESULT intel_queue_create(struct intel_dev *dev, |
Chia-I Wu | cdcff73 | 2014-08-19 14:44:15 +0800 | [diff] [blame] | 176 | enum intel_gpu_engine_type engine, |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 177 | struct intel_queue **queue_ret) |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 178 | { |
| 179 | struct intel_queue *queue; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 180 | enum intel_ring_type ring; |
| 181 | |
Chia-I Wu | cdcff73 | 2014-08-19 14:44:15 +0800 | [diff] [blame] | 182 | switch (engine) { |
| 183 | case INTEL_GPU_ENGINE_3D: |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 184 | ring = INTEL_RING_RENDER; |
| 185 | break; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 186 | default: |
| 187 | return XGL_ERROR_INVALID_VALUE; |
| 188 | break; |
| 189 | } |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 190 | |
Courtney Goeltzenleuchter | fb4fb53 | 2014-08-14 09:35:21 -0600 | [diff] [blame] | 191 | queue = (struct intel_queue *) intel_base_create(dev, sizeof(*queue), |
Chia-I Wu | bbf2c93 | 2014-08-07 12:20:08 +0800 | [diff] [blame] | 192 | dev->base.dbg, XGL_DBG_OBJECT_QUEUE, NULL, 0); |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 193 | if (!queue) |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 194 | return XGL_ERROR_OUT_OF_MEMORY; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 195 | |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 196 | queue->dev = dev; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 197 | queue->ring = ring; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 198 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 199 | if (queue_init_hw_and_atomic_bo(queue) != XGL_SUCCESS) { |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 200 | intel_queue_destroy(queue); |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 201 | return XGL_ERROR_INITIALIZATION_FAILED; |
Chia-I Wu | 3ad3c54 | 2014-08-25 11:09:17 +0800 | [diff] [blame] | 202 | } |
| 203 | |
Chia-I Wu | 9ae59c1 | 2014-08-07 10:08:49 +0800 | [diff] [blame] | 204 | *queue_ret = queue; |
| 205 | |
| 206 | return XGL_SUCCESS; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | void intel_queue_destroy(struct intel_queue *queue) |
| 210 | { |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 211 | if (queue->atomic_bo) |
| 212 | intel_bo_unreference(queue->atomic_bo); |
| 213 | if (queue->select_graphics_bo) |
| 214 | intel_bo_unreference(queue->select_graphics_bo); |
| 215 | if (queue->select_compute_bo) |
| 216 | intel_bo_unreference(queue->select_compute_bo); |
Chia-I Wu | bbf2c93 | 2014-08-07 12:20:08 +0800 | [diff] [blame] | 217 | intel_base_destroy(&queue->base); |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout) |
| 221 | { |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 222 | struct intel_bo *bo = (queue->last_submitted_cmd) ? |
| 223 | intel_cmd_get_batch(queue->last_submitted_cmd, NULL) : NULL; |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 224 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 225 | return (!bo || intel_bo_wait(bo, timeout) == 0) ? |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 226 | XGL_SUCCESS : XGL_ERROR_UNKNOWN; |
| 227 | } |
| 228 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 229 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueSetGlobalMemReferences( |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 230 | XGL_QUEUE queue, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 231 | uint32_t memRefCount, |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 232 | const XGL_MEMORY_REF* pMemRefs) |
| 233 | { |
| 234 | /* |
| 235 | * The winwys maintains the list of memory references. These are ignored |
| 236 | * until we move away from the winsys. |
| 237 | */ |
| 238 | return XGL_SUCCESS; |
| 239 | } |
| 240 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 241 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueWaitIdle( |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 242 | XGL_QUEUE queue_) |
| 243 | { |
| 244 | struct intel_queue *queue = intel_queue(queue_); |
| 245 | |
| 246 | return intel_queue_wait(queue, -1); |
| 247 | } |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 248 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 249 | ICD_EXPORT XGL_RESULT XGLAPI xglQueueSubmit( |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 250 | XGL_QUEUE queue_, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 251 | uint32_t cmdBufferCount, |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 252 | const XGL_CMD_BUFFER* pCmdBuffers, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 253 | uint32_t memRefCount, |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 254 | const XGL_MEMORY_REF* pMemRefs, |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 255 | XGL_FENCE fence_) |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 256 | { |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 257 | struct intel_queue *queue = intel_queue(queue_); |
| 258 | XGL_RESULT ret = XGL_SUCCESS; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 259 | uint32_t i; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 260 | |
| 261 | for (i = 0; i < cmdBufferCount; i++) { |
| 262 | struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]); |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 263 | struct intel_bo *bo; |
| 264 | XGL_GPU_SIZE used; |
| 265 | XGL_RESULT ret; |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 266 | |
Chia-I Wu | ec84172 | 2014-08-25 22:36:01 +0800 | [diff] [blame] | 267 | ret = queue_select_pipeline(queue, cmd->pipeline_select); |
Chia-I Wu | 6388329 | 2014-08-25 13:50:26 +0800 | [diff] [blame] | 268 | if (ret != XGL_SUCCESS) |
| 269 | break; |
| 270 | |
Chia-I Wu | fb6d338 | 2015-02-11 11:23:52 -0700 | [diff] [blame] | 271 | if (cmd->result != XGL_SUCCESS) { |
| 272 | intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR, |
| 273 | XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0, |
| 274 | "invalid command buffer submitted"); |
| 275 | ret = cmd->result; |
| 276 | break; |
| 277 | } |
| 278 | |
Chia-I Wu | 94d2fba | 2014-08-25 11:38:08 +0800 | [diff] [blame] | 279 | bo = intel_cmd_get_batch(cmd, &used); |
| 280 | ret = queue_submit_bo(queue, bo, used); |
| 281 | queue->last_submitted_cmd = cmd; |
| 282 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 283 | if (intel_debug & INTEL_DEBUG_BATCH) |
| 284 | intel_cmd_decode(cmd); |
| 285 | |
Chia-I Wu | c5438c2 | 2014-08-19 14:03:06 +0800 | [diff] [blame] | 286 | if (ret != XGL_SUCCESS) |
| 287 | break; |
| 288 | } |
| 289 | |
| 290 | if (ret == XGL_SUCCESS && fence_ != XGL_NULL_HANDLE) { |
| 291 | struct intel_fence *fence = intel_fence(fence_); |
| 292 | intel_fence_set_cmd(fence, queue->last_submitted_cmd); |
| 293 | } |
| 294 | |
| 295 | /* XGL_MEMORY_REFs are ignored as the winsys already knows them */ |
| 296 | |
| 297 | return ret; |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 298 | } |
| 299 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 300 | ICD_EXPORT XGL_RESULT XGLAPI xglOpenSharedQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 301 | XGL_DEVICE device, |
| 302 | const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo, |
| 303 | XGL_QUEUE_SEMAPHORE* pSemaphore) |
| 304 | { |
| 305 | return XGL_ERROR_UNAVAILABLE; |
| 306 | } |
| 307 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 308 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 309 | XGL_DEVICE device, |
| 310 | const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo, |
| 311 | XGL_QUEUE_SEMAPHORE* pSemaphore) |
| 312 | { |
| 313 | /* |
| 314 | * We want to find an unused semaphore register and initialize it. Signal |
| 315 | * will increment the register. Wait will atomically decrement it and |
| 316 | * block if the value is zero, or a large constant N if we do not want to |
| 317 | * go negative. |
| 318 | * |
| 319 | * XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility. |
| 320 | */ |
| 321 | return XGL_ERROR_UNAVAILABLE; |
| 322 | } |
| 323 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 324 | ICD_EXPORT XGL_RESULT XGLAPI xglSignalQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 325 | XGL_QUEUE queue, |
| 326 | XGL_QUEUE_SEMAPHORE semaphore) |
| 327 | { |
| 328 | return XGL_ERROR_UNAVAILABLE; |
| 329 | } |
| 330 | |
Chia-I Wu | 9617727 | 2015-01-03 15:27:41 +0800 | [diff] [blame] | 331 | ICD_EXPORT XGL_RESULT XGLAPI xglWaitQueueSemaphore( |
Chia-I Wu | 251e7d9 | 2014-08-19 13:35:42 +0800 | [diff] [blame] | 332 | XGL_QUEUE queue, |
| 333 | XGL_QUEUE_SEMAPHORE semaphore) |
| 334 | { |
| 335 | return XGL_ERROR_UNAVAILABLE; |
| 336 | } |