blob: a7e6dc7e0baa502a2e962efca9c8eec6ba019439 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu730e5362014-08-19 12:15:09 +080025#include "genhw/genhw.h"
26#include "kmd/winsys.h"
27#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080028#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080030#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080031
Chia-I Wue24c3292014-08-21 14:05:23 +080032static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
33 struct intel_cmd_writer *writer,
34 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080035{
36 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080037 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080038 struct intel_bo *bo;
39 void *ptr;
40
41 bo = intel_winsys_alloc_buffer(winsys,
42 "batch buffer", bo_size, INTEL_DOMAIN_CPU);
43 if (!bo)
44 return XGL_ERROR_OUT_OF_GPU_MEMORY;
45
46 ptr = intel_bo_map(bo, true);
47 if (!bo) {
48 intel_bo_unreference(bo);
49 return XGL_ERROR_MEMORY_MAP_FAILED;
50 }
51
Chia-I Wue24c3292014-08-21 14:05:23 +080052 writer->bo = bo;
53 writer->ptr_opaque = ptr;
54 writer->size = size;
55 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080056
57 return XGL_SUCCESS;
58}
59
Chia-I Wu5e25c272014-08-21 20:19:12 +080060static void cmd_writer_copy(struct intel_cmd *cmd,
61 struct intel_cmd_writer *writer,
62 const uint32_t *vals, XGL_UINT len)
63{
64 assert(writer->used + len <= writer->size);
65 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
66 vals, sizeof(uint32_t) * len);
67 writer->used += len;
68}
69
70static void cmd_writer_patch(struct intel_cmd *cmd,
71 struct intel_cmd_writer *writer,
72 XGL_UINT pos, uint32_t val)
73{
74 assert(pos < writer->used);
75 ((uint32_t *) writer->ptr_opaque)[pos] = val;
76}
77
Chia-I Wue24c3292014-08-21 14:05:23 +080078void cmd_writer_grow(struct intel_cmd *cmd,
79 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +080080{
Chia-I Wue24c3292014-08-21 14:05:23 +080081 const XGL_UINT size = writer->size << 1;
82 const XGL_UINT old_used = writer->used;
83 struct intel_bo *old_bo = writer->bo;
84 void *old_ptr = writer->ptr_opaque;
85
86 if (size >= writer->size &&
87 cmd_writer_alloc_and_map(cmd, writer, size) == XGL_SUCCESS) {
88 cmd_writer_copy(cmd, writer, (const uint32_t *) old_ptr, old_used);
89
90 intel_bo_unmap(old_bo);
91 intel_bo_unreference(old_bo);
92 } else {
93 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
94 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
95 "failed to grow command buffer of size %u", writer->size);
96
97 /* wrap it and fail silently */
98 writer->used = 0;
99 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
100 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800101}
102
Chia-I Wue24c3292014-08-21 14:05:23 +0800103static void cmd_writer_unmap(struct intel_cmd *cmd,
104 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +0800105{
Chia-I Wue24c3292014-08-21 14:05:23 +0800106 intel_bo_unmap(writer->bo);
107 writer->ptr_opaque = NULL;
108}
109
110static void cmd_writer_free(struct intel_cmd *cmd,
111 struct intel_cmd_writer *writer)
112{
113 intel_bo_unreference(writer->bo);
114 writer->bo = NULL;
115}
116
117static void cmd_writer_reset(struct intel_cmd *cmd,
118 struct intel_cmd_writer *writer)
119{
120 /* do not reset writer->size as we want to know how big it has grown to */
121 writer->used = 0;
122
123 if (writer->ptr_opaque)
124 cmd_writer_unmap(cmd, writer);
125 if (writer->bo)
126 cmd_writer_free(cmd, writer);
127}
128
129static void cmd_unmap(struct intel_cmd *cmd)
130{
131 cmd_writer_unmap(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800132 cmd_writer_unmap(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800133 cmd_writer_unmap(cmd, &cmd->kernel);
Chia-I Wu730e5362014-08-19 12:15:09 +0800134}
135
136static void cmd_reset(struct intel_cmd *cmd)
137{
Chia-I Wue24c3292014-08-21 14:05:23 +0800138 cmd_writer_reset(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800139 cmd_writer_reset(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800140 cmd_writer_reset(cmd, &cmd->kernel);
Chia-I Wu343b1372014-08-20 16:39:20 +0800141 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800142 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800143}
144
145static void cmd_destroy(struct intel_obj *obj)
146{
147 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
148
149 intel_cmd_destroy(cmd);
150}
151
152XGL_RESULT intel_cmd_create(struct intel_dev *dev,
153 const XGL_CMD_BUFFER_CREATE_INFO *info,
154 struct intel_cmd **cmd_ret)
155{
Chia-I Wu63883292014-08-25 13:50:26 +0800156 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800157 struct intel_cmd *cmd;
158
Chia-I Wu63883292014-08-25 13:50:26 +0800159 switch (info->queueType) {
160 case XGL_QUEUE_TYPE_GRAPHICS:
161 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
162 break;
163 case XGL_QUEUE_TYPE_COMPUTE:
164 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
165 break;
166 case XGL_QUEUE_TYPE_DMA:
167 pipeline_select = -1;
168 break;
169 default:
170 return XGL_ERROR_INVALID_VALUE;
171 break;
172 }
173
Chia-I Wu730e5362014-08-19 12:15:09 +0800174 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
175 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
176 if (!cmd)
177 return XGL_ERROR_OUT_OF_MEMORY;
178
179 cmd->obj.destroy = cmd_destroy;
180
181 cmd->dev = dev;
Chia-I Wu63883292014-08-25 13:50:26 +0800182 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800183
Chia-I Wue0cdd832014-08-25 12:38:56 +0800184 /*
185 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
186 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
187 * and end offsets, for each referenced memories.
188 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800189 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
190 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
191 4096, XGL_SYSTEM_ALLOC_INTERNAL);
192 if (!cmd->relocs) {
193 intel_cmd_destroy(cmd);
194 return XGL_ERROR_OUT_OF_MEMORY;
195 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800196
197 *cmd_ret = cmd;
198
199 return XGL_SUCCESS;
200}
201
202void intel_cmd_destroy(struct intel_cmd *cmd)
203{
204 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800205
206 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800207 intel_base_destroy(&cmd->obj.base);
208}
209
210XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
211{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800212 XGL_RESULT ret;
Chia-I Wu730e5362014-08-19 12:15:09 +0800213
214 cmd_reset(cmd);
215
Chia-I Wu24565ee2014-08-21 20:24:31 +0800216 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800217 cmd->flags = flags;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800218 cmd->batch.size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800219 }
220
Chia-I Wu24565ee2014-08-21 20:24:31 +0800221 if (!cmd->batch.size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800222 const XGL_UINT size =
223 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
224 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800225
226 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
227 divider *= 4;
228
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800229 cmd->batch.size = size / divider;
230 cmd->state.size = size / divider;
231 cmd->kernel.size = 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800232 }
233
234 ret = cmd_writer_alloc_and_map(cmd, &cmd->batch, cmd->batch.size);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800235 if (ret == XGL_SUCCESS)
236 ret = cmd_writer_alloc_and_map(cmd, &cmd->state, cmd->state.size);
237 if (ret == XGL_SUCCESS)
238 ret = cmd_writer_alloc_and_map(cmd, &cmd->kernel, cmd->kernel.size);
239 if (ret != XGL_SUCCESS) {
240 cmd_reset(cmd);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800241 return ret;
242 }
243
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800244 cmd_batch_begin(cmd);
245
Chia-I Wu24565ee2014-08-21 20:24:31 +0800246 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800247}
248
249XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
250{
251 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800252 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800253
Chia-I Wue24c3292014-08-21 14:05:23 +0800254 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800255
Chia-I Wu343b1372014-08-20 16:39:20 +0800256 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800257 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800258 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
259 uint64_t presumed_offset;
260 int err;
261
Chia-I Wue24c3292014-08-21 14:05:23 +0800262 err = intel_bo_add_reloc(reloc->writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800263 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wue24c3292014-08-21 14:05:23 +0800264 reloc->read_domains, reloc->write_domain, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800265 if (err) {
266 cmd->result = XGL_ERROR_UNKNOWN;
267 break;
268 }
269
270 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wue24c3292014-08-21 14:05:23 +0800271 cmd_writer_patch(cmd, reloc->writer, reloc->pos,
272 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800273 }
274
Chia-I Wu730e5362014-08-19 12:15:09 +0800275 cmd_unmap(cmd);
276
Chia-I Wu04966702014-08-20 15:05:03 +0800277 if (cmd->result != XGL_SUCCESS)
278 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800279
280 if (intel_winsys_can_submit_bo(winsys, &cmd->batch.bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800281 return XGL_SUCCESS;
282 else
283 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
284}
285
Chia-I Wu09142132014-08-11 15:42:55 +0800286XGL_RESULT XGLAPI intelCreateCommandBuffer(
287 XGL_DEVICE device,
288 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
289 XGL_CMD_BUFFER* pCmdBuffer)
290{
Chia-I Wu730e5362014-08-19 12:15:09 +0800291 struct intel_dev *dev = intel_dev(device);
292
293 return intel_cmd_create(dev, pCreateInfo,
294 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800295}
296
297XGL_RESULT XGLAPI intelBeginCommandBuffer(
298 XGL_CMD_BUFFER cmdBuffer,
299 XGL_FLAGS flags)
300{
Chia-I Wu730e5362014-08-19 12:15:09 +0800301 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
302
303 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800304}
305
306XGL_RESULT XGLAPI intelEndCommandBuffer(
307 XGL_CMD_BUFFER cmdBuffer)
308{
Chia-I Wu730e5362014-08-19 12:15:09 +0800309 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
310
311 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800312}
313
314XGL_RESULT XGLAPI intelResetCommandBuffer(
315 XGL_CMD_BUFFER cmdBuffer)
316{
Chia-I Wu730e5362014-08-19 12:15:09 +0800317 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
318
319 cmd_reset(cmd);
320
321 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800322}
323
Chia-I Wu09142132014-08-11 15:42:55 +0800324XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
325 XGL_CMD_BUFFER cmdBuffer,
326 XGL_UINT transitionCount,
327 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions)
328{
329}
330
331XGL_VOID XGLAPI intelCmdPrepareImages(
332 XGL_CMD_BUFFER cmdBuffer,
333 XGL_UINT transitionCount,
334 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions)
335{
336}
337
Chia-I Wu09142132014-08-11 15:42:55 +0800338XGL_VOID XGLAPI intelCmdCopyMemory(
339 XGL_CMD_BUFFER cmdBuffer,
340 XGL_GPU_MEMORY srcMem,
341 XGL_GPU_MEMORY destMem,
342 XGL_UINT regionCount,
343 const XGL_MEMORY_COPY* pRegions)
344{
345}
346
347XGL_VOID XGLAPI intelCmdCopyImage(
348 XGL_CMD_BUFFER cmdBuffer,
349 XGL_IMAGE srcImage,
350 XGL_IMAGE destImage,
351 XGL_UINT regionCount,
352 const XGL_IMAGE_COPY* pRegions)
353{
354}
355
356XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
357 XGL_CMD_BUFFER cmdBuffer,
358 XGL_GPU_MEMORY srcMem,
359 XGL_IMAGE destImage,
360 XGL_UINT regionCount,
361 const XGL_MEMORY_IMAGE_COPY* pRegions)
362{
363}
364
365XGL_VOID XGLAPI intelCmdCopyImageToMemory(
366 XGL_CMD_BUFFER cmdBuffer,
367 XGL_IMAGE srcImage,
368 XGL_GPU_MEMORY destMem,
369 XGL_UINT regionCount,
370 const XGL_MEMORY_IMAGE_COPY* pRegions)
371{
372}
373
374XGL_VOID XGLAPI intelCmdCloneImageData(
375 XGL_CMD_BUFFER cmdBuffer,
376 XGL_IMAGE srcImage,
377 XGL_IMAGE_STATE srcImageState,
378 XGL_IMAGE destImage,
379 XGL_IMAGE_STATE destImageState)
380{
381}
382
383XGL_VOID XGLAPI intelCmdUpdateMemory(
384 XGL_CMD_BUFFER cmdBuffer,
385 XGL_GPU_MEMORY destMem,
386 XGL_GPU_SIZE destOffset,
387 XGL_GPU_SIZE dataSize,
388 const XGL_UINT32* pData)
389{
390}
391
392XGL_VOID XGLAPI intelCmdFillMemory(
393 XGL_CMD_BUFFER cmdBuffer,
394 XGL_GPU_MEMORY destMem,
395 XGL_GPU_SIZE destOffset,
396 XGL_GPU_SIZE fillSize,
397 XGL_UINT32 data)
398{
399}
400
401XGL_VOID XGLAPI intelCmdClearColorImage(
402 XGL_CMD_BUFFER cmdBuffer,
403 XGL_IMAGE image,
404 const XGL_FLOAT color[4],
405 XGL_UINT rangeCount,
406 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
407{
408}
409
410XGL_VOID XGLAPI intelCmdClearColorImageRaw(
411 XGL_CMD_BUFFER cmdBuffer,
412 XGL_IMAGE image,
413 const XGL_UINT32 color[4],
414 XGL_UINT rangeCount,
415 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
416{
417}
418
419XGL_VOID XGLAPI intelCmdClearDepthStencil(
420 XGL_CMD_BUFFER cmdBuffer,
421 XGL_IMAGE image,
422 XGL_FLOAT depth,
423 XGL_UINT32 stencil,
424 XGL_UINT rangeCount,
425 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
426{
427}
428
429XGL_VOID XGLAPI intelCmdResolveImage(
430 XGL_CMD_BUFFER cmdBuffer,
431 XGL_IMAGE srcImage,
432 XGL_IMAGE destImage,
433 XGL_UINT rectCount,
434 const XGL_IMAGE_RESOLVE* pRects)
435{
436}
437
438XGL_VOID XGLAPI intelCmdSetEvent(
439 XGL_CMD_BUFFER cmdBuffer,
440 XGL_EVENT event)
441{
442}
443
444XGL_VOID XGLAPI intelCmdResetEvent(
445 XGL_CMD_BUFFER cmdBuffer,
446 XGL_EVENT event)
447{
448}
449
450XGL_VOID XGLAPI intelCmdMemoryAtomic(
451 XGL_CMD_BUFFER cmdBuffer,
452 XGL_GPU_MEMORY destMem,
453 XGL_GPU_SIZE destOffset,
454 XGL_UINT64 srcData,
455 XGL_ATOMIC_OP atomicOp)
456{
457}
458
459XGL_VOID XGLAPI intelCmdBeginQuery(
460 XGL_CMD_BUFFER cmdBuffer,
461 XGL_QUERY_POOL queryPool,
462 XGL_UINT slot,
463 XGL_FLAGS flags)
464{
465}
466
467XGL_VOID XGLAPI intelCmdEndQuery(
468 XGL_CMD_BUFFER cmdBuffer,
469 XGL_QUERY_POOL queryPool,
470 XGL_UINT slot)
471{
472}
473
474XGL_VOID XGLAPI intelCmdResetQueryPool(
475 XGL_CMD_BUFFER cmdBuffer,
476 XGL_QUERY_POOL queryPool,
477 XGL_UINT startQuery,
478 XGL_UINT queryCount)
479{
480}
481
482XGL_VOID XGLAPI intelCmdWriteTimestamp(
483 XGL_CMD_BUFFER cmdBuffer,
484 XGL_TIMESTAMP_TYPE timestampType,
485 XGL_GPU_MEMORY destMem,
486 XGL_GPU_SIZE destOffset)
487{
488}
489
490XGL_VOID XGLAPI intelCmdInitAtomicCounters(
491 XGL_CMD_BUFFER cmdBuffer,
492 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
493 XGL_UINT startCounter,
494 XGL_UINT counterCount,
495 const XGL_UINT32* pData)
496{
497}
498
499XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
500 XGL_CMD_BUFFER cmdBuffer,
501 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
502 XGL_UINT startCounter,
503 XGL_UINT counterCount,
504 XGL_GPU_MEMORY srcMem,
505 XGL_GPU_SIZE srcOffset)
506{
507}
508
509XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
510 XGL_CMD_BUFFER cmdBuffer,
511 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
512 XGL_UINT startCounter,
513 XGL_UINT counterCount,
514 XGL_GPU_MEMORY destMem,
515 XGL_GPU_SIZE destOffset)
516{
517}
518
519XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
520 XGL_CMD_BUFFER cmdBuffer,
521 const XGL_CHAR* pMarker)
522{
523}
524
525XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
526 XGL_CMD_BUFFER cmdBuffer)
527{
528}