Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Mesa 3-D graphics library |
| 3 | * |
| 4 | * Copyright (C) 2012-2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
| 26 | */ |
| 27 | |
| 28 | #ifndef INTEL_WINSYS_H |
| 29 | #define INTEL_WINSYS_H |
| 30 | |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 31 | #include <stddef.h> |
Chia-I Wu | 770b309 | 2014-08-05 14:22:03 +0800 | [diff] [blame] | 32 | #include <stdint.h> |
| 33 | #include <stdbool.h> |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 34 | |
| 35 | /* this is compatible with i915_drm.h's definitions */ |
| 36 | enum intel_ring_type { |
| 37 | INTEL_RING_RENDER = 1, |
| 38 | INTEL_RING_BSD = 2, |
| 39 | INTEL_RING_BLT = 3, |
| 40 | INTEL_RING_VEBOX = 4, |
| 41 | }; |
| 42 | |
| 43 | /* this is compatible with i915_drm.h's definitions */ |
| 44 | enum intel_exec_flag { |
| 45 | INTEL_EXEC_GEN7_SOL_RESET = 1 << 8, |
| 46 | }; |
| 47 | |
| 48 | /* this is compatible with i915_drm.h's definitions */ |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 49 | enum intel_reloc_flag { |
| 50 | INTEL_RELOC_FENCE = 1 << 0, |
| 51 | INTEL_RELOC_GGTT = 1 << 1, |
| 52 | INTEL_RELOC_WRITE = 1 << 2, |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | /* this is compatible with i915_drm.h's definitions */ |
| 56 | enum intel_tiling_mode { |
| 57 | INTEL_TILING_NONE = 0, |
| 58 | INTEL_TILING_X = 1, |
| 59 | INTEL_TILING_Y = 2, |
| 60 | }; |
| 61 | |
Chia-I Wu | 770b309 | 2014-08-05 14:22:03 +0800 | [diff] [blame] | 62 | enum intel_winsys_handle_type { |
| 63 | INTEL_WINSYS_HANDLE_SHARED, |
| 64 | INTEL_WINSYS_HANDLE_KMS, |
| 65 | INTEL_WINSYS_HANDLE_FD, |
| 66 | }; |
| 67 | |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 68 | struct intel_winsys; |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 69 | struct intel_bo; |
| 70 | |
| 71 | struct intel_winsys_info { |
| 72 | int devid; |
| 73 | |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 74 | /* the sizes of the aperture in bytes */ |
| 75 | size_t aperture_total; |
| 76 | size_t aperture_mappable; |
| 77 | |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 78 | bool has_llc; |
| 79 | bool has_address_swizzling; |
| 80 | bool has_logical_context; |
| 81 | bool has_ppgtt; |
| 82 | |
| 83 | /* valid registers for intel_winsys_read_reg() */ |
| 84 | bool has_timestamp; |
| 85 | |
| 86 | /* valid flags for intel_winsys_submit_bo() */ |
| 87 | bool has_gen7_sol_reset; |
| 88 | }; |
| 89 | |
Chia-I Wu | 770b309 | 2014-08-05 14:22:03 +0800 | [diff] [blame] | 90 | struct intel_winsys_handle { |
| 91 | enum intel_winsys_handle_type type; |
| 92 | unsigned handle; |
| 93 | unsigned stride; |
| 94 | }; |
| 95 | |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 96 | struct intel_winsys * |
| 97 | intel_winsys_create_for_fd(int fd); |
| 98 | |
| 99 | void |
| 100 | intel_winsys_destroy(struct intel_winsys *winsys); |
| 101 | |
| 102 | const struct intel_winsys_info * |
| 103 | intel_winsys_get_info(const struct intel_winsys *winsys); |
| 104 | |
| 105 | /** |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 106 | * Read a register. Only registers that are considered safe, such as |
| 107 | * |
| 108 | * TIMESTAMP (0x2358) |
| 109 | * |
| 110 | * can be read. |
| 111 | */ |
| 112 | int |
| 113 | intel_winsys_read_reg(struct intel_winsys *winsys, |
| 114 | uint32_t reg, uint64_t *val); |
| 115 | |
| 116 | /** |
| 117 | * Allocate a buffer object. |
| 118 | * |
| 119 | * \param name Informative description of the bo. |
| 120 | * \param tiling Tiling mode. |
| 121 | * \param pitch Pitch of the bo. |
| 122 | * \param height Height of the bo. |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 123 | * \param cpu_init Will be initialized by CPU. |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 124 | */ |
| 125 | struct intel_bo * |
| 126 | intel_winsys_alloc_bo(struct intel_winsys *winsys, |
| 127 | const char *name, |
| 128 | enum intel_tiling_mode tiling, |
| 129 | unsigned long pitch, |
| 130 | unsigned long height, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 131 | bool cpu_init); |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 132 | |
| 133 | /** |
| 134 | * Allocate a linear buffer object. |
| 135 | */ |
| 136 | static inline struct intel_bo * |
| 137 | intel_winsys_alloc_buffer(struct intel_winsys *winsys, |
| 138 | const char *name, |
| 139 | unsigned long size, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 140 | bool cpu_init) |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 141 | { |
| 142 | return intel_winsys_alloc_bo(winsys, name, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 143 | INTEL_TILING_NONE, size, 1, cpu_init); |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | /** |
| 147 | * Create a bo from a winsys handle. |
| 148 | */ |
| 149 | struct intel_bo * |
| 150 | intel_winsys_import_handle(struct intel_winsys *winsys, |
| 151 | const char *name, |
Chia-I Wu | 770b309 | 2014-08-05 14:22:03 +0800 | [diff] [blame] | 152 | const struct intel_winsys_handle *handle, |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 153 | unsigned long height, |
| 154 | enum intel_tiling_mode *tiling, |
| 155 | unsigned long *pitch); |
| 156 | |
| 157 | /** |
| 158 | * Export \p bo as a winsys handle for inter-process sharing. |
| 159 | */ |
| 160 | int |
| 161 | intel_winsys_export_handle(struct intel_winsys *winsys, |
| 162 | struct intel_bo *bo, |
| 163 | enum intel_tiling_mode tiling, |
| 164 | unsigned long pitch, |
| 165 | unsigned long height, |
Chia-I Wu | 770b309 | 2014-08-05 14:22:03 +0800 | [diff] [blame] | 166 | struct intel_winsys_handle *handle); |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 167 | |
| 168 | /** |
| 169 | * Return true when buffer objects directly specified in \p bo_array, and |
| 170 | * those indirectly referenced by them, can fit in the aperture space. |
| 171 | */ |
| 172 | bool |
| 173 | intel_winsys_can_submit_bo(struct intel_winsys *winsys, |
| 174 | struct intel_bo **bo_array, |
| 175 | int count); |
| 176 | |
| 177 | /** |
| 178 | * Submit \p bo for execution. |
| 179 | * |
| 180 | * \p bo and all bos referenced by \p bo will be considered busy until all |
| 181 | * commands are parsed and executed. \p ctx is ignored when the bo is not |
| 182 | * submitted to the render ring. |
| 183 | */ |
| 184 | int |
| 185 | intel_winsys_submit_bo(struct intel_winsys *winsys, |
| 186 | enum intel_ring_type ring, |
| 187 | struct intel_bo *bo, int used, |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 188 | unsigned long flags); |
| 189 | |
| 190 | /** |
| 191 | * Decode the commands contained in \p bo. For debugging. |
| 192 | * |
| 193 | * \param bo Batch buffer to decode. |
| 194 | * \param used Size of the commands in bytes. |
| 195 | */ |
| 196 | void |
| 197 | intel_winsys_decode_bo(struct intel_winsys *winsys, |
| 198 | struct intel_bo *bo, int used); |
| 199 | |
Chia-I Wu | 242b35a | 2015-02-11 11:26:44 -0700 | [diff] [blame] | 200 | int |
| 201 | intel_winsys_read_reset_stats(struct intel_winsys *winsys, |
| 202 | uint32_t *active, uint32_t *pending); |
| 203 | |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 204 | /** |
| 205 | * Increase the reference count of \p bo. |
| 206 | */ |
| 207 | void |
| 208 | intel_bo_reference(struct intel_bo *bo); |
| 209 | |
| 210 | /** |
| 211 | * Decrease the reference count of \p bo. When the reference count reaches |
| 212 | * zero, \p bo is destroyed. |
| 213 | */ |
| 214 | void |
| 215 | intel_bo_unreference(struct intel_bo *bo); |
| 216 | |
| 217 | /** |
| 218 | * Map \p bo for CPU access. Recursive mapping is allowed. |
| 219 | * |
| 220 | * map() maps the backing store into CPU address space, cached. It will block |
| 221 | * if the bo is busy. This variant allows fastest random reads and writes, |
| 222 | * but the caller needs to handle tiling or swizzling manually if the bo is |
| 223 | * tiled or swizzled. If write is enabled and there is no shared last-level |
| 224 | * cache (LLC), the CPU cache will be flushed, which is expensive. |
| 225 | * |
| 226 | * map_gtt() maps the bo for MMIO access, uncached but write-combined. It |
| 227 | * will block if the bo is busy. This variant promises a reasonable speed for |
| 228 | * sequential writes, but reads would be very slow. Callers always have a |
| 229 | * linear view of the bo. |
| 230 | * |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 231 | * map_gtt_async() is similar to map_gtt(), except that it does not block. |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 232 | */ |
| 233 | void * |
| 234 | intel_bo_map(struct intel_bo *bo, bool write_enable); |
| 235 | |
| 236 | void * |
| 237 | intel_bo_map_gtt(struct intel_bo *bo); |
| 238 | |
| 239 | void * |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 240 | intel_bo_map_gtt_async(struct intel_bo *bo); |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 241 | |
| 242 | /** |
| 243 | * Unmap \p bo. |
| 244 | */ |
| 245 | void |
| 246 | intel_bo_unmap(struct intel_bo *bo); |
| 247 | |
| 248 | /** |
| 249 | * Write data to \p bo. |
| 250 | */ |
| 251 | int |
| 252 | intel_bo_pwrite(struct intel_bo *bo, unsigned long offset, |
| 253 | unsigned long size, const void *data); |
| 254 | |
| 255 | /** |
| 256 | * Read data from the bo. |
| 257 | */ |
| 258 | int |
| 259 | intel_bo_pread(struct intel_bo *bo, unsigned long offset, |
| 260 | unsigned long size, void *data); |
| 261 | |
| 262 | /** |
| 263 | * Add \p target_bo to the relocation list. |
| 264 | * |
| 265 | * When \p bo is submitted for execution, and if \p target_bo has moved, |
| 266 | * the kernel will patch \p bo at \p offset to \p target_bo->offset plus |
| 267 | * \p target_offset. |
| 268 | * |
| 269 | * \p presumed_offset should be written to \p bo at \p offset. |
| 270 | */ |
| 271 | int |
| 272 | intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset, |
| 273 | struct intel_bo *target_bo, uint32_t target_offset, |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 274 | uint32_t flags, uint64_t *presumed_offset); |
Chia-I Wu | 6464ff2 | 2014-08-05 11:59:54 +0800 | [diff] [blame] | 275 | |
| 276 | /** |
| 277 | * Return the current number of relocations. |
| 278 | */ |
| 279 | int |
| 280 | intel_bo_get_reloc_count(struct intel_bo *bo); |
| 281 | |
| 282 | /** |
| 283 | * Truncate all relocations except the first \p start ones. |
| 284 | * |
| 285 | * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the |
| 286 | * \p intel_bo_add_reloc() calls that were just made. |
| 287 | */ |
| 288 | void |
| 289 | intel_bo_truncate_relocs(struct intel_bo *bo, int start); |
| 290 | |
| 291 | /** |
| 292 | * Return true if \p target_bo is on the relocation list of \p bo, or on |
| 293 | * the relocation list of some bo that is referenced by \p bo. |
| 294 | */ |
| 295 | bool |
| 296 | intel_bo_has_reloc(struct intel_bo *bo, struct intel_bo *target_bo); |
| 297 | |
| 298 | /** |
| 299 | * Wait until \bo is idle, or \p timeout nanoseconds have passed. A |
| 300 | * negative timeout means to wait indefinitely. |
| 301 | * |
| 302 | * \return 0 only when \p bo is idle |
| 303 | */ |
| 304 | int |
| 305 | intel_bo_wait(struct intel_bo *bo, int64_t timeout); |
| 306 | |
| 307 | /** |
| 308 | * Return true if \p bo is busy. |
| 309 | */ |
| 310 | static inline bool |
| 311 | intel_bo_is_busy(struct intel_bo *bo) |
| 312 | { |
| 313 | return (intel_bo_wait(bo, 0) != 0); |
| 314 | } |
| 315 | |
| 316 | #endif /* INTEL_WINSYS_H */ |