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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
29#ifndef CMD_H
30#define CMD_H
31
32#include "intel.h"
33#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080034#include "view.h"
35
36struct intel_pipeline;
Chia-I Wuf2b6d722014-09-02 08:52:27 +080037struct intel_pipeline_shader;
Chia-I Wub2755562014-08-20 13:38:52 +080038struct intel_pipeline_delta;
39struct intel_viewport_state;
40struct intel_raster_state;
41struct intel_msaa_state;
42struct intel_blend_state;
43struct intel_ds_state;
44struct intel_dset;
45
Chia-I Wu00b51a82014-09-09 12:07:37 +080046struct intel_cmd_item;
Chia-I Wu958d1b72014-08-21 11:28:11 +080047struct intel_cmd_reloc;
Chia-I Wu6032b892014-10-17 14:47:18 +080048struct intel_cmd_meta;
Chia-I Wu958d1b72014-08-21 11:28:11 +080049
Chia-I Wu8370b402014-08-29 12:28:37 +080050/*
51 * We know what workarounds are needed for intel_pipeline. These are mostly
52 * for intel_pipeline_delta.
53 */
54enum intel_cmd_wa_flags {
55 /*
56 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
57 *
58 * "Before any depth stall flush (including those produced by
59 * non-pipelined state commands), software needs to first send a
60 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
61 */
62 INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE = 1 << 0,
63
64 /*
65 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
66 *
67 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
68 * field set (DW1 Bit 1), must be issued prior to any change to the
69 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
70 *
71 * From the Ivy Bridge PRM, volume 2 part 1, page 286:
72 *
73 * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
74 * between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
75 * Pixel Scoreboard set is required to be issued."
76 */
77 INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL = 1 << 1,
78
79 /*
80 * From the Ivy Bridge PRM, volume 2 part 1, page 106:
81 *
82 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
83 * stall needs to be sent just prior to any 3DSTATE_VS,
84 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
85 * 3DSTATE_BINDING_TABLE_POINTER_VS, 3DSTATE_SAMPLER_STATE_POINTER_VS
86 * command. Only one PIPE_CONTROL needs to be sent before any
87 * combination of VS associated 3DSTATE."
88 */
89 INTEL_CMD_WA_GEN7_PRE_VS_DEPTH_STALL_WRITE = 1 << 2,
90
91 /*
92 * From the Ivy Bridge PRM, volume 2 part 1, page 258:
93 *
94 * "Due to an HW issue driver needs to send a pipe control with stall
95 * when ever there is state change in depth bias related state"
96 *
97 * From the Ivy Bridge PRM, volume 2 part 1, page 292:
98 *
99 * "A PIPE_CONTOL command with the CS Stall bit set must be programmed
100 * in the ring after this instruction
101 * (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
102 */
103 INTEL_CMD_WA_GEN7_POST_COMMAND_CS_STALL = 1 << 3,
104
105 /*
106 * From the Ivy Bridge PRM, volume 2 part 1, page 276:
107 *
108 * "The driver must make sure a PIPE_CONTROL with the Depth Stall
109 * Enable bit set after all the following states are programmed:
110 *
111 * - 3DSTATE_PS
112 * - 3DSTATE_VIEWPORT_STATE_POINTERS_CC
113 * - 3DSTATE_CONSTANT_PS
114 * - 3DSTATE_BINDING_TABLE_POINTERS_PS
115 * - 3DSTATE_SAMPLER_STATE_POINTERS_PS
116 * - 3DSTATE_CC_STATE_POINTERS
117 * - 3DSTATE_BLEND_STATE_POINTERS
118 * - 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
119 */
120 INTEL_CMD_WA_GEN7_POST_COMMAND_DEPTH_STALL = 1 << 4,
121};
122
Chia-I Wu68f319d2014-09-09 09:43:21 +0800123enum intel_cmd_writer_type {
124 INTEL_CMD_WRITER_BATCH,
125 INTEL_CMD_WRITER_STATE,
126 INTEL_CMD_WRITER_INSTRUCTION,
127
128 INTEL_CMD_WRITER_COUNT,
129};
130
Chia-I Wua57761b2014-10-14 14:27:44 +0800131struct intel_cmd_shader_cache {
132 struct {
133 const void *shader;
134 uint32_t kernel_offset;
135 } *entries;
136
137 XGL_UINT count;
138 XGL_UINT used;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600139};
140
Chia-I Wub2755562014-08-20 13:38:52 +0800141/*
142 * States bounded to the command buffer. We want to write states directly to
143 * the command buffer when possible, and reduce this struct.
144 */
145struct intel_cmd_bind {
Chia-I Wu6032b892014-10-17 14:47:18 +0800146 const struct intel_cmd_meta *meta;
147
Chia-I Wua57761b2014-10-14 14:27:44 +0800148 struct intel_cmd_shader_cache shader_cache;
149
Chia-I Wub2755562014-08-20 13:38:52 +0800150 struct {
151 const struct intel_pipeline *graphics;
152 const struct intel_pipeline *compute;
153 const struct intel_pipeline_delta *graphics_delta;
154 const struct intel_pipeline_delta *compute_delta;
Chia-I Wua57761b2014-10-14 14:27:44 +0800155
156 uint32_t vs_offset;
157 uint32_t tcs_offset;
158 uint32_t tes_offset;
159 uint32_t gs_offset;
160 uint32_t fs_offset;
161 uint32_t cs_offset;
Chia-I Wub2755562014-08-20 13:38:52 +0800162 } pipeline;
163
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600164 struct {
Chia-I Wub2755562014-08-20 13:38:52 +0800165 const struct intel_viewport_state *viewport;
166 const struct intel_raster_state *raster;
167 const struct intel_msaa_state *msaa;
168 const struct intel_blend_state *blend;
169 const struct intel_ds_state *ds;
170 } state;
171
172 struct {
173 const struct intel_dset *graphics;
174 XGL_UINT graphics_offset;
175 const struct intel_dset *compute;
176 XGL_UINT compute_offset;
177 } dset;
178
179 struct {
180 struct intel_mem_view graphics;
181 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +0800182 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +0800183
184 struct {
185 const struct intel_mem *mem;
186 XGL_GPU_SIZE offset;
187 XGL_INDEX_TYPE type;
188 } index;
189
190 struct {
191 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
192 XGL_UINT rt_count;
193
194 const struct intel_ds_view *ds;
Chia-I Wu2e5ec9b2014-10-14 13:37:21 +0800195
196 XGL_UINT width, height;
Chia-I Wub2755562014-08-20 13:38:52 +0800197 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800198
Chia-I Wu707a29e2014-08-27 12:51:47 +0800199 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800200 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +0800201};
Chia-I Wu09142132014-08-11 15:42:55 +0800202
Chia-I Wue24c3292014-08-21 14:05:23 +0800203struct intel_cmd_writer {
Chia-I Wu72292b72014-09-09 10:48:33 +0800204 XGL_SIZE size;
Chia-I Wue24c3292014-08-21 14:05:23 +0800205 struct intel_bo *bo;
Chia-I Wu0f50ba82014-09-09 10:25:46 +0800206 void *ptr;
Chia-I Wue24c3292014-08-21 14:05:23 +0800207
Chia-I Wu72292b72014-09-09 10:48:33 +0800208 XGL_SIZE used;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800209
210 /* for decoding */
211 struct intel_cmd_item *items;
212 XGL_UINT item_alloc;
213 XGL_UINT item_used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800214};
215
Chia-I Wu730e5362014-08-19 12:15:09 +0800216struct intel_cmd {
217 struct intel_obj obj;
218
219 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800220 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800221 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800222
Chia-I Wu343b1372014-08-20 16:39:20 +0800223 struct intel_cmd_reloc *relocs;
224 XGL_UINT reloc_count;
225
Chia-I Wu730e5362014-08-19 12:15:09 +0800226 XGL_FLAGS flags;
227
Chia-I Wu68f319d2014-09-09 09:43:21 +0800228 struct intel_cmd_writer writers[INTEL_CMD_WRITER_COUNT];
Chia-I Wu730e5362014-08-19 12:15:09 +0800229
Chia-I Wu343b1372014-08-20 16:39:20 +0800230 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800231 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800232
233 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800234};
235
236static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
237{
238 return (struct intel_cmd *) cmd;
239}
240
241static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
242{
243 return (struct intel_cmd *) obj;
244}
245
246XGL_RESULT intel_cmd_create(struct intel_dev *dev,
247 const XGL_CMD_BUFFER_CREATE_INFO *info,
248 struct intel_cmd **cmd_ret);
249void intel_cmd_destroy(struct intel_cmd *cmd);
250
251XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
252XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
253
Chia-I Wu00b51a82014-09-09 12:07:37 +0800254void intel_cmd_decode(struct intel_cmd *cmd);
255
Chia-I Wue24c3292014-08-21 14:05:23 +0800256static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
257 XGL_GPU_SIZE *used)
258{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800259 const struct intel_cmd_writer *writer =
260 &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wue24c3292014-08-21 14:05:23 +0800261
262 if (used)
Chia-I Wu72292b72014-09-09 10:48:33 +0800263 *used = writer->used;
Chia-I Wue24c3292014-08-21 14:05:23 +0800264
265 return writer->bo;
266}
267
Chia-I Wu09142132014-08-11 15:42:55 +0800268XGL_RESULT XGLAPI intelCreateCommandBuffer(
269 XGL_DEVICE device,
270 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
271 XGL_CMD_BUFFER* pCmdBuffer);
272
273XGL_RESULT XGLAPI intelBeginCommandBuffer(
274 XGL_CMD_BUFFER cmdBuffer,
275 XGL_FLAGS flags);
276
277XGL_RESULT XGLAPI intelEndCommandBuffer(
278 XGL_CMD_BUFFER cmdBuffer);
279
280XGL_RESULT XGLAPI intelResetCommandBuffer(
281 XGL_CMD_BUFFER cmdBuffer);
282
283XGL_VOID XGLAPI intelCmdBindPipeline(
284 XGL_CMD_BUFFER cmdBuffer,
285 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
286 XGL_PIPELINE pipeline);
287
288XGL_VOID XGLAPI intelCmdBindPipelineDelta(
289 XGL_CMD_BUFFER cmdBuffer,
290 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
291 XGL_PIPELINE_DELTA delta);
292
293XGL_VOID XGLAPI intelCmdBindStateObject(
294 XGL_CMD_BUFFER cmdBuffer,
295 XGL_STATE_BIND_POINT stateBindPoint,
296 XGL_STATE_OBJECT state);
297
298XGL_VOID XGLAPI intelCmdBindDescriptorSet(
299 XGL_CMD_BUFFER cmdBuffer,
300 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
301 XGL_UINT index,
302 XGL_DESCRIPTOR_SET descriptorSet,
303 XGL_UINT slotOffset);
304
305XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
306 XGL_CMD_BUFFER cmdBuffer,
307 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
308 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
309
310XGL_VOID XGLAPI intelCmdBindIndexData(
311 XGL_CMD_BUFFER cmdBuffer,
312 XGL_GPU_MEMORY mem,
313 XGL_GPU_SIZE offset,
314 XGL_INDEX_TYPE indexType);
315
316XGL_VOID XGLAPI intelCmdBindAttachments(
317 XGL_CMD_BUFFER cmdBuffer,
318 XGL_UINT colorAttachmentCount,
319 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
320 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
321
322XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
323 XGL_CMD_BUFFER cmdBuffer,
324 XGL_UINT transitionCount,
325 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
326
327XGL_VOID XGLAPI intelCmdPrepareImages(
328 XGL_CMD_BUFFER cmdBuffer,
329 XGL_UINT transitionCount,
330 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
331
332XGL_VOID XGLAPI intelCmdDraw(
333 XGL_CMD_BUFFER cmdBuffer,
334 XGL_UINT firstVertex,
335 XGL_UINT vertexCount,
336 XGL_UINT firstInstance,
337 XGL_UINT instanceCount);
338
339XGL_VOID XGLAPI intelCmdDrawIndexed(
340 XGL_CMD_BUFFER cmdBuffer,
341 XGL_UINT firstIndex,
342 XGL_UINT indexCount,
343 XGL_INT vertexOffset,
344 XGL_UINT firstInstance,
345 XGL_UINT instanceCount);
346
347XGL_VOID XGLAPI intelCmdDrawIndirect(
348 XGL_CMD_BUFFER cmdBuffer,
349 XGL_GPU_MEMORY mem,
350 XGL_GPU_SIZE offset,
351 XGL_UINT32 count,
352 XGL_UINT32 stride);
353
354XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
355 XGL_CMD_BUFFER cmdBuffer,
356 XGL_GPU_MEMORY mem,
357 XGL_GPU_SIZE offset,
358 XGL_UINT32 count,
359 XGL_UINT32 stride);
360
361XGL_VOID XGLAPI intelCmdDispatch(
362 XGL_CMD_BUFFER cmdBuffer,
363 XGL_UINT x,
364 XGL_UINT y,
365 XGL_UINT z);
366
367XGL_VOID XGLAPI intelCmdDispatchIndirect(
368 XGL_CMD_BUFFER cmdBuffer,
369 XGL_GPU_MEMORY mem,
370 XGL_GPU_SIZE offset);
371
372XGL_VOID XGLAPI intelCmdCopyMemory(
373 XGL_CMD_BUFFER cmdBuffer,
374 XGL_GPU_MEMORY srcMem,
375 XGL_GPU_MEMORY destMem,
376 XGL_UINT regionCount,
377 const XGL_MEMORY_COPY* pRegions);
378
379XGL_VOID XGLAPI intelCmdCopyImage(
380 XGL_CMD_BUFFER cmdBuffer,
381 XGL_IMAGE srcImage,
382 XGL_IMAGE destImage,
383 XGL_UINT regionCount,
384 const XGL_IMAGE_COPY* pRegions);
385
386XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
387 XGL_CMD_BUFFER cmdBuffer,
388 XGL_GPU_MEMORY srcMem,
389 XGL_IMAGE destImage,
390 XGL_UINT regionCount,
391 const XGL_MEMORY_IMAGE_COPY* pRegions);
392
393XGL_VOID XGLAPI intelCmdCopyImageToMemory(
394 XGL_CMD_BUFFER cmdBuffer,
395 XGL_IMAGE srcImage,
396 XGL_GPU_MEMORY destMem,
397 XGL_UINT regionCount,
398 const XGL_MEMORY_IMAGE_COPY* pRegions);
399
400XGL_VOID XGLAPI intelCmdCloneImageData(
401 XGL_CMD_BUFFER cmdBuffer,
402 XGL_IMAGE srcImage,
403 XGL_IMAGE_STATE srcImageState,
404 XGL_IMAGE destImage,
405 XGL_IMAGE_STATE destImageState);
406
407XGL_VOID XGLAPI intelCmdUpdateMemory(
408 XGL_CMD_BUFFER cmdBuffer,
409 XGL_GPU_MEMORY destMem,
410 XGL_GPU_SIZE destOffset,
411 XGL_GPU_SIZE dataSize,
412 const XGL_UINT32* pData);
413
414XGL_VOID XGLAPI intelCmdFillMemory(
415 XGL_CMD_BUFFER cmdBuffer,
416 XGL_GPU_MEMORY destMem,
417 XGL_GPU_SIZE destOffset,
418 XGL_GPU_SIZE fillSize,
419 XGL_UINT32 data);
420
421XGL_VOID XGLAPI intelCmdClearColorImage(
422 XGL_CMD_BUFFER cmdBuffer,
423 XGL_IMAGE image,
424 const XGL_FLOAT color[4],
425 XGL_UINT rangeCount,
426 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
427
428XGL_VOID XGLAPI intelCmdClearColorImageRaw(
429 XGL_CMD_BUFFER cmdBuffer,
430 XGL_IMAGE image,
431 const XGL_UINT32 color[4],
432 XGL_UINT rangeCount,
433 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
434
435XGL_VOID XGLAPI intelCmdClearDepthStencil(
436 XGL_CMD_BUFFER cmdBuffer,
437 XGL_IMAGE image,
438 XGL_FLOAT depth,
439 XGL_UINT32 stencil,
440 XGL_UINT rangeCount,
441 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
442
443XGL_VOID XGLAPI intelCmdResolveImage(
444 XGL_CMD_BUFFER cmdBuffer,
445 XGL_IMAGE srcImage,
446 XGL_IMAGE destImage,
447 XGL_UINT rectCount,
448 const XGL_IMAGE_RESOLVE* pRects);
449
450XGL_VOID XGLAPI intelCmdSetEvent(
451 XGL_CMD_BUFFER cmdBuffer,
452 XGL_EVENT event);
453
454XGL_VOID XGLAPI intelCmdResetEvent(
455 XGL_CMD_BUFFER cmdBuffer,
456 XGL_EVENT event);
457
458XGL_VOID XGLAPI intelCmdMemoryAtomic(
459 XGL_CMD_BUFFER cmdBuffer,
460 XGL_GPU_MEMORY destMem,
461 XGL_GPU_SIZE destOffset,
462 XGL_UINT64 srcData,
463 XGL_ATOMIC_OP atomicOp);
464
465XGL_VOID XGLAPI intelCmdBeginQuery(
466 XGL_CMD_BUFFER cmdBuffer,
467 XGL_QUERY_POOL queryPool,
468 XGL_UINT slot,
469 XGL_FLAGS flags);
470
471XGL_VOID XGLAPI intelCmdEndQuery(
472 XGL_CMD_BUFFER cmdBuffer,
473 XGL_QUERY_POOL queryPool,
474 XGL_UINT slot);
475
476XGL_VOID XGLAPI intelCmdResetQueryPool(
477 XGL_CMD_BUFFER cmdBuffer,
478 XGL_QUERY_POOL queryPool,
479 XGL_UINT startQuery,
480 XGL_UINT queryCount);
481
482XGL_VOID XGLAPI intelCmdWriteTimestamp(
483 XGL_CMD_BUFFER cmdBuffer,
484 XGL_TIMESTAMP_TYPE timestampType,
485 XGL_GPU_MEMORY destMem,
486 XGL_GPU_SIZE destOffset);
487
488XGL_VOID XGLAPI intelCmdInitAtomicCounters(
489 XGL_CMD_BUFFER cmdBuffer,
490 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
491 XGL_UINT startCounter,
492 XGL_UINT counterCount,
493 const XGL_UINT32* pData);
494
495XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
496 XGL_CMD_BUFFER cmdBuffer,
497 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
498 XGL_UINT startCounter,
499 XGL_UINT counterCount,
500 XGL_GPU_MEMORY srcMem,
501 XGL_GPU_SIZE srcOffset);
502
503XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
504 XGL_CMD_BUFFER cmdBuffer,
505 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
506 XGL_UINT startCounter,
507 XGL_UINT counterCount,
508 XGL_GPU_MEMORY destMem,
509 XGL_GPU_SIZE destOffset);
510
511XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
512 XGL_CMD_BUFFER cmdBuffer,
513 const XGL_CHAR* pMarker);
514
515XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
516 XGL_CMD_BUFFER cmdBuffer);
517
518#endif /* CMD_H */