Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2015 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
| 26 | */ |
| 27 | |
| 28 | #include "buf.h" |
| 29 | #include "cmd.h" |
| 30 | #include "dev.h" |
| 31 | #include "gpu.h" |
| 32 | #include "img.h" |
| 33 | #include "sampler.h" |
| 34 | #include "view.h" |
| 35 | #include "desc.h" |
| 36 | |
| 37 | enum intel_desc_surface_type { |
| 38 | INTEL_DESC_SURFACE_UNUSED, |
| 39 | INTEL_DESC_SURFACE_BUF, |
| 40 | INTEL_DESC_SURFACE_IMG, |
| 41 | }; |
| 42 | |
| 43 | struct intel_desc_surface { |
| 44 | const struct intel_mem *mem; |
| 45 | bool read_only; |
| 46 | |
| 47 | enum intel_desc_surface_type type; |
| 48 | union { |
| 49 | const void *unused; |
| 50 | const struct intel_buf_view *buf; |
| 51 | const struct intel_img_view *img; |
| 52 | } u; |
| 53 | }; |
| 54 | |
| 55 | struct intel_desc_sampler { |
| 56 | const struct intel_sampler *sampler; |
| 57 | }; |
| 58 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 59 | static bool desc_region_init_desc_sizes(struct intel_desc_region *region, |
| 60 | const struct intel_gpu *gpu) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 61 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 62 | region->surface_desc_size = sizeof(struct intel_desc_surface); |
| 63 | region->sampler_desc_size = sizeof(struct intel_desc_sampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 64 | |
| 65 | return true; |
| 66 | } |
| 67 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 68 | XGL_RESULT intel_desc_region_create(struct intel_dev *dev, |
| 69 | struct intel_desc_region **region_ret) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 70 | { |
| 71 | const uint32_t surface_count = 16384; |
| 72 | const uint32_t sampler_count = 16384; |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 73 | struct intel_desc_region *region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 74 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 75 | region = intel_alloc(dev, sizeof(*region), 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 76 | if (!region) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 77 | return XGL_ERROR_OUT_OF_MEMORY; |
| 78 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 79 | memset(region, 0, sizeof(*region)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 80 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 81 | if (!desc_region_init_desc_sizes(region, dev->gpu)) { |
| 82 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 83 | return XGL_ERROR_UNKNOWN; |
| 84 | } |
| 85 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 86 | intel_desc_offset_set(®ion->size, |
| 87 | region->surface_desc_size * surface_count, |
| 88 | region->sampler_desc_size * sampler_count); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 89 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 90 | region->surfaces = intel_alloc(dev, region->size.surface, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 91 | 64, XGL_SYSTEM_ALLOC_INTERNAL); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 92 | if (!region->surfaces) { |
| 93 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 94 | return XGL_ERROR_OUT_OF_MEMORY; |
| 95 | } |
| 96 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 97 | region->samplers = intel_alloc(dev, region->size.sampler, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 98 | 64, XGL_SYSTEM_ALLOC_INTERNAL); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 99 | if (!region->samplers) { |
| 100 | intel_free(dev, region->surfaces); |
| 101 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 102 | return XGL_ERROR_OUT_OF_MEMORY; |
| 103 | } |
| 104 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 105 | *region_ret = region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 106 | |
| 107 | return XGL_SUCCESS; |
| 108 | } |
| 109 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 110 | void intel_desc_region_destroy(struct intel_dev *dev, |
| 111 | struct intel_desc_region *region) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 112 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 113 | intel_free(dev, region->samplers); |
| 114 | intel_free(dev, region->surfaces); |
| 115 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /** |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 119 | * Get the size of a descriptor in the region. |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 120 | */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 121 | static XGL_RESULT desc_region_get_desc_size(const struct intel_desc_region *region, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 122 | XGL_DESCRIPTOR_TYPE type, |
| 123 | struct intel_desc_offset *size) |
| 124 | { |
| 125 | uint32_t surface_size = 0, sampler_size = 0; |
| 126 | |
| 127 | switch (type) { |
| 128 | case XGL_DESCRIPTOR_TYPE_SAMPLER: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 129 | sampler_size = region->sampler_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 130 | break; |
| 131 | case XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 132 | surface_size = region->surface_desc_size; |
| 133 | sampler_size = region->sampler_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 134 | break; |
| 135 | case XGL_DESCRIPTOR_TYPE_TEXTURE: |
| 136 | case XGL_DESCRIPTOR_TYPE_TEXTURE_BUFFER: |
| 137 | case XGL_DESCRIPTOR_TYPE_IMAGE: |
| 138 | case XGL_DESCRIPTOR_TYPE_IMAGE_BUFFER: |
| 139 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER: |
| 140 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER: |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 141 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: |
| 142 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 143 | surface_size = region->surface_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 144 | break; |
| 145 | default: |
| 146 | assert(!"unknown descriptor type"); |
| 147 | return XGL_ERROR_INVALID_VALUE; |
| 148 | break; |
| 149 | } |
| 150 | |
| 151 | intel_desc_offset_set(size, surface_size, sampler_size); |
| 152 | |
| 153 | return XGL_SUCCESS; |
| 154 | } |
| 155 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 156 | XGL_RESULT intel_desc_region_alloc(struct intel_desc_region *region, |
| 157 | const XGL_DESCRIPTOR_POOL_CREATE_INFO *info, |
| 158 | struct intel_desc_offset *begin, |
| 159 | struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 160 | { |
| 161 | uint32_t surface_size = 0, sampler_size = 0; |
| 162 | struct intel_desc_offset alloc; |
| 163 | uint32_t i; |
| 164 | |
| 165 | /* calculate sizes needed */ |
| 166 | for (i = 0; i < info->count; i++) { |
| 167 | const XGL_DESCRIPTOR_TYPE_COUNT *tc = &info->pTypeCount[i]; |
| 168 | struct intel_desc_offset size; |
| 169 | XGL_RESULT ret; |
| 170 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 171 | ret = desc_region_get_desc_size(region, tc->type, &size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 172 | if (ret != XGL_SUCCESS) |
| 173 | return ret; |
| 174 | |
| 175 | surface_size += size.surface * tc->count; |
| 176 | sampler_size += size.sampler * tc->count; |
| 177 | } |
| 178 | |
| 179 | intel_desc_offset_set(&alloc, surface_size, sampler_size); |
| 180 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 181 | *begin = region->cur; |
| 182 | intel_desc_offset_add(end, ®ion->cur, &alloc); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 183 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 184 | if (!intel_desc_offset_within(end, ®ion->size)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 185 | return XGL_ERROR_OUT_OF_MEMORY; |
| 186 | |
| 187 | /* increment the writer pointer */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 188 | region->cur = *end; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 189 | |
| 190 | return XGL_SUCCESS; |
| 191 | } |
| 192 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 193 | static void desc_region_validate_begin_end(const struct intel_desc_region *region, |
| 194 | const struct intel_desc_offset *begin, |
| 195 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 196 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 197 | assert(begin->surface % region->surface_desc_size == 0 && |
| 198 | begin->sampler % region->sampler_desc_size == 0); |
| 199 | assert(end->surface % region->surface_desc_size == 0 && |
| 200 | end->sampler % region->sampler_desc_size == 0); |
| 201 | assert(intel_desc_offset_within(end, ®ion->size)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 202 | } |
| 203 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 204 | void intel_desc_region_free(struct intel_desc_region *region, |
| 205 | const struct intel_desc_offset *begin, |
| 206 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 207 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 208 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 209 | |
| 210 | /* is it ok not to reclaim? */ |
| 211 | } |
| 212 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 213 | XGL_RESULT intel_desc_region_begin_update(struct intel_desc_region *region, |
| 214 | XGL_DESCRIPTOR_UPDATE_MODE mode) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 215 | { |
| 216 | /* no-op */ |
| 217 | return XGL_SUCCESS; |
| 218 | } |
| 219 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 220 | XGL_RESULT intel_desc_region_end_update(struct intel_desc_region *region, |
| 221 | struct intel_cmd *cmd) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 222 | { |
| 223 | /* No pipelined update. cmd_draw() will do the work. */ |
| 224 | return XGL_SUCCESS; |
| 225 | } |
| 226 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 227 | void intel_desc_region_clear(struct intel_desc_region *region, |
| 228 | const struct intel_desc_offset *begin, |
| 229 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 230 | { |
| 231 | uint32_t i; |
| 232 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 233 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 234 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 235 | for (i = begin->surface; i < end->surface; i += region->surface_desc_size) { |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 236 | struct intel_desc_surface *desc = (struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 237 | ((char *) region->surfaces + i); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 238 | |
| 239 | desc->mem = NULL; |
| 240 | desc->type = INTEL_DESC_SURFACE_UNUSED; |
| 241 | desc->u.unused = NULL; |
| 242 | } |
| 243 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 244 | for (i = begin->sampler; i < end->sampler; i += region->sampler_desc_size) { |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 245 | struct intel_desc_sampler *desc = (struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 246 | ((char *) region->samplers + i); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 247 | |
| 248 | desc->sampler = NULL; |
| 249 | } |
| 250 | } |
| 251 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 252 | void intel_desc_region_update(struct intel_desc_region *region, |
| 253 | const struct intel_desc_offset *begin, |
| 254 | const struct intel_desc_offset *end, |
| 255 | const struct intel_desc_surface *surfaces, |
| 256 | const struct intel_desc_sampler *samplers) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 257 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 258 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 259 | |
| 260 | if (begin->surface < end->surface) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 261 | memcpy((char *) region->surfaces + begin->surface, surfaces, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 262 | end->surface - begin->surface); |
| 263 | } |
| 264 | |
| 265 | if (begin->sampler < end->sampler) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 266 | memcpy((char *) region->samplers + begin->sampler, samplers, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 267 | end->sampler - begin->sampler); |
| 268 | } |
| 269 | } |
| 270 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 271 | void intel_desc_region_copy(struct intel_desc_region *region, |
| 272 | const struct intel_desc_offset *begin, |
| 273 | const struct intel_desc_offset *end, |
| 274 | const struct intel_desc_offset *src) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 275 | { |
| 276 | struct intel_desc_offset src_end; |
| 277 | const struct intel_desc_surface *surfaces; |
| 278 | const struct intel_desc_sampler *samplers; |
| 279 | |
| 280 | /* no overlap */ |
| 281 | assert(intel_desc_offset_within(src, begin) || |
| 282 | intel_desc_offset_within(end, src)); |
| 283 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 284 | /* no read past region */ |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 285 | intel_desc_offset_sub(&src_end, end, begin); |
| 286 | intel_desc_offset_add(&src_end, src, &src_end); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 287 | assert(intel_desc_offset_within(&src_end, ®ion->size)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 288 | |
| 289 | surfaces = (const struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 290 | ((const char *) region->surfaces + src->surface); |
Tony Barbour | 379e0a7 | 2015-02-05 11:09:34 -0700 | [diff] [blame] | 291 | samplers = (const struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 292 | ((const char *) region->samplers + src->sampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 293 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 294 | intel_desc_region_update(region, begin, end, surfaces, samplers); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 295 | } |
| 296 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 297 | static void desc_pool_destroy(struct intel_obj *obj) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 298 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 299 | struct intel_desc_pool *pool = intel_desc_pool_from_obj(obj); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 300 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 301 | intel_desc_pool_destroy(pool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 302 | } |
| 303 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 304 | XGL_RESULT intel_desc_pool_create(struct intel_dev *dev, |
| 305 | XGL_DESCRIPTOR_POOL_USAGE usage, |
| 306 | uint32_t max_sets, |
| 307 | const XGL_DESCRIPTOR_POOL_CREATE_INFO *info, |
| 308 | struct intel_desc_pool **pool_ret) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 309 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 310 | struct intel_desc_pool *pool; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 311 | XGL_RESULT ret; |
| 312 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 313 | pool = (struct intel_desc_pool *) intel_base_create(&dev->base.handle, |
| 314 | sizeof(*pool), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_POOL, |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 315 | info, 0); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 316 | if (!pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 317 | return XGL_ERROR_OUT_OF_MEMORY; |
| 318 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 319 | pool->dev = dev; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 320 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 321 | ret = intel_desc_region_alloc(dev->desc_region, info, |
| 322 | &pool->region_begin, &pool->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 323 | if (ret != XGL_SUCCESS) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 324 | intel_base_destroy(&pool->obj.base); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 325 | return ret; |
| 326 | } |
| 327 | |
| 328 | /* point to head */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 329 | pool->cur = pool->region_begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 330 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 331 | pool->obj.destroy = desc_pool_destroy; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 332 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 333 | *pool_ret = pool; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 334 | |
| 335 | return XGL_SUCCESS; |
| 336 | } |
| 337 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 338 | void intel_desc_pool_destroy(struct intel_desc_pool *pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 339 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 340 | intel_desc_region_free(pool->dev->desc_region, |
| 341 | &pool->region_begin, &pool->region_end); |
| 342 | intel_base_destroy(&pool->obj.base); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 343 | } |
| 344 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 345 | XGL_RESULT intel_desc_pool_alloc(struct intel_desc_pool *pool, |
| 346 | const struct intel_desc_layout *layout, |
| 347 | struct intel_desc_offset *begin, |
| 348 | struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 349 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 350 | *begin = pool->cur; |
| 351 | intel_desc_offset_add(end, &pool->cur, &layout->region_size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 352 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 353 | if (!intel_desc_offset_within(end, &pool->region_end)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 354 | return XGL_ERROR_OUT_OF_MEMORY; |
| 355 | |
| 356 | /* increment the writer pointer */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 357 | pool->cur = *end; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 358 | |
| 359 | return XGL_SUCCESS; |
| 360 | } |
| 361 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 362 | void intel_desc_pool_reset(struct intel_desc_pool *pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 363 | { |
| 364 | /* reset to head */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 365 | pool->cur = pool->region_begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static void desc_set_destroy(struct intel_obj *obj) |
| 369 | { |
| 370 | struct intel_desc_set *set = intel_desc_set_from_obj(obj); |
| 371 | |
| 372 | intel_desc_set_destroy(set); |
| 373 | } |
| 374 | |
| 375 | XGL_RESULT intel_desc_set_create(struct intel_dev *dev, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 376 | struct intel_desc_pool *pool, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 377 | XGL_DESCRIPTOR_SET_USAGE usage, |
| 378 | const struct intel_desc_layout *layout, |
| 379 | struct intel_desc_set **set_ret) |
| 380 | { |
| 381 | struct intel_desc_set *set; |
| 382 | XGL_RESULT ret; |
| 383 | |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 384 | set = (struct intel_desc_set *) intel_base_create(&dev->base.handle, |
| 385 | sizeof(*set), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_SET, |
| 386 | NULL, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 387 | if (!set) |
| 388 | return XGL_ERROR_OUT_OF_MEMORY; |
| 389 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 390 | set->region = dev->desc_region; |
| 391 | ret = intel_desc_pool_alloc(pool, layout, |
| 392 | &set->region_begin, &set->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 393 | if (ret != XGL_SUCCESS) { |
| 394 | intel_base_destroy(&set->obj.base); |
| 395 | return ret; |
| 396 | } |
| 397 | |
| 398 | set->layout = layout; |
| 399 | |
| 400 | set->obj.destroy = desc_set_destroy; |
| 401 | |
| 402 | *set_ret = set; |
| 403 | |
| 404 | return XGL_SUCCESS; |
| 405 | } |
| 406 | |
| 407 | void intel_desc_set_destroy(struct intel_desc_set *set) |
| 408 | { |
| 409 | intel_base_destroy(&set->obj.base); |
| 410 | } |
| 411 | |
| 412 | static void desc_set_update(struct intel_desc_set *set, |
| 413 | const struct intel_desc_layout_iter *iter, |
| 414 | const struct intel_desc_surface *surfaces, |
| 415 | const struct intel_desc_sampler *samplers) |
| 416 | { |
| 417 | struct intel_desc_offset begin, end; |
| 418 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 419 | intel_desc_offset_add(&begin, &set->region_begin, &iter->offset_begin); |
| 420 | intel_desc_offset_add(&end, &set->region_begin, &iter->offset_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 421 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 422 | intel_desc_region_update(set->region, &begin, &end, surfaces, samplers); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static bool desc_set_img_layout_read_only(XGL_IMAGE_LAYOUT layout) |
| 426 | { |
| 427 | switch (layout) { |
| 428 | case XGL_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL: |
| 429 | case XGL_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL: |
| 430 | case XGL_IMAGE_LAYOUT_TRANSFER_SOURCE_OPTIMAL: |
| 431 | return true; |
| 432 | default: |
| 433 | return false; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | void intel_desc_set_update_samplers(struct intel_desc_set *set, |
| 438 | const XGL_UPDATE_SAMPLERS *update) |
| 439 | { |
| 440 | struct intel_desc_layout_iter iter; |
| 441 | uint32_t i; |
| 442 | |
| 443 | if (!intel_desc_layout_find_index(set->layout, update->index, &iter)) |
| 444 | return; |
| 445 | |
| 446 | for (i = 0; i < update->count; i++) { |
| 447 | const struct intel_sampler *sampler = |
| 448 | intel_sampler((XGL_SAMPLER) update->pSamplers[i]); |
| 449 | struct intel_desc_sampler desc; |
| 450 | |
| 451 | if (iter.type != XGL_DESCRIPTOR_TYPE_SAMPLER) |
| 452 | break; |
| 453 | |
| 454 | desc.sampler = sampler; |
| 455 | desc_set_update(set, &iter, NULL, &desc); |
| 456 | |
| 457 | if (!intel_desc_layout_advance_iter(set->layout, &iter)) |
| 458 | break; |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | void intel_desc_set_update_sampler_textures(struct intel_desc_set *set, |
| 463 | const XGL_UPDATE_SAMPLER_TEXTURES *update) |
| 464 | { |
| 465 | struct intel_desc_layout_iter iter; |
| 466 | const struct intel_sampler *immutable_sampler = NULL; |
| 467 | uint32_t i; |
| 468 | |
| 469 | if (!intel_desc_layout_find_index(set->layout, update->index, &iter)) |
| 470 | return; |
| 471 | |
| 472 | for (i = 0; i < update->count; i++) { |
| 473 | const struct intel_sampler *sampler = |
| 474 | intel_sampler(update->pSamplerImageViews[i].pSampler); |
| 475 | const XGL_IMAGE_VIEW_ATTACH_INFO *info = |
| 476 | update->pSamplerImageViews[i].pImageView; |
| 477 | const struct intel_img_view *view = intel_img_view(info->view); |
| 478 | struct intel_desc_surface view_desc; |
| 479 | struct intel_desc_sampler sampler_desc; |
| 480 | |
| 481 | if (iter.type != XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE) |
| 482 | return; |
| 483 | |
| 484 | /* update every immutable sampler once */ |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 485 | if (immutable_sampler != iter.binding->immutable_sampler) { |
| 486 | immutable_sampler = iter.binding->immutable_sampler; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 487 | |
| 488 | if (immutable_sampler) { |
| 489 | struct intel_desc_offset begin, end; |
| 490 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 491 | intel_desc_offset_add(&begin, &set->region_begin, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 492 | &iter.offset_begin); |
| 493 | intel_desc_offset_set(&end, begin.surface, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 494 | begin.sampler + set->region->sampler_desc_size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 495 | |
| 496 | sampler_desc.sampler = immutable_sampler; |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 497 | intel_desc_region_update(set->region, &begin, &end, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 498 | NULL, &sampler_desc); |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | view_desc.mem = view->img->obj.mem; |
| 503 | view_desc.read_only = desc_set_img_layout_read_only(info->layout); |
| 504 | view_desc.type = INTEL_DESC_SURFACE_IMG; |
| 505 | view_desc.u.img = view; |
| 506 | |
| 507 | sampler_desc.sampler = sampler; |
| 508 | |
| 509 | desc_set_update(set, &iter, &view_desc, &sampler_desc); |
| 510 | |
| 511 | if (!intel_desc_layout_advance_iter(set->layout, &iter)) |
| 512 | break; |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | void intel_desc_set_update_images(struct intel_desc_set *set, |
| 517 | const XGL_UPDATE_IMAGES *update) |
| 518 | { |
| 519 | struct intel_desc_layout_iter iter; |
| 520 | uint32_t i; |
| 521 | |
| 522 | if (!intel_desc_layout_find_index(set->layout, update->index, &iter)) |
| 523 | return; |
| 524 | |
| 525 | for (i = 0; i < update->count; i++) { |
| 526 | const XGL_IMAGE_VIEW_ATTACH_INFO *info = update->pImageViews[i]; |
| 527 | const struct intel_img_view *view = intel_img_view(info->view); |
| 528 | struct intel_desc_surface desc; |
| 529 | |
| 530 | if (iter.type != update->descriptorType) |
| 531 | break; |
| 532 | |
| 533 | desc.mem = view->img->obj.mem; |
| 534 | desc.read_only = desc_set_img_layout_read_only(info->layout); |
| 535 | desc.type = INTEL_DESC_SURFACE_IMG; |
| 536 | desc.u.img = view; |
| 537 | desc_set_update(set, &iter, &desc, NULL); |
| 538 | |
| 539 | if (!intel_desc_layout_advance_iter(set->layout, &iter)) |
| 540 | break; |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | void intel_desc_set_update_buffers(struct intel_desc_set *set, |
| 545 | const XGL_UPDATE_BUFFERS *update) |
| 546 | { |
| 547 | struct intel_desc_layout_iter iter; |
| 548 | uint32_t i; |
| 549 | |
| 550 | if (!intel_desc_layout_find_index(set->layout, update->index, &iter)) |
| 551 | return; |
| 552 | |
| 553 | for (i = 0; i < update->count; i++) { |
| 554 | const XGL_BUFFER_VIEW_ATTACH_INFO *info = update->pBufferViews[i]; |
| 555 | const struct intel_buf_view *view = intel_buf_view(info->view); |
| 556 | struct intel_desc_surface desc; |
| 557 | |
| 558 | if (iter.type != update->descriptorType) |
| 559 | break; |
| 560 | |
| 561 | desc.mem = view->buf->obj.mem; |
| 562 | desc.read_only = false; |
| 563 | desc.type = INTEL_DESC_SURFACE_BUF; |
| 564 | desc.u.buf = view; |
| 565 | desc_set_update(set, &iter, &desc, NULL); |
| 566 | |
| 567 | if (!intel_desc_layout_advance_iter(set->layout, &iter)) |
| 568 | break; |
| 569 | } |
| 570 | } |
| 571 | |
| 572 | void intel_desc_set_update_as_copy(struct intel_desc_set *set, |
| 573 | const XGL_UPDATE_AS_COPY *update) |
| 574 | { |
| 575 | const struct intel_desc_set *src_set = |
| 576 | intel_desc_set(update->descriptorSet); |
| 577 | struct intel_desc_layout_iter iter, src_iter; |
| 578 | struct intel_desc_offset begin, end, src_begin; |
| 579 | uint32_t i; |
| 580 | |
| 581 | /* disallow combined sampler textures */ |
| 582 | if (update->descriptorType == XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE) |
| 583 | return; |
| 584 | |
| 585 | /* no update->index? */ |
| 586 | if (!intel_desc_layout_find_index(set->layout, 0, &iter)) |
| 587 | return; |
| 588 | if (!intel_desc_layout_find_index(src_set->layout, |
| 589 | update->descriptorIndex, &src_iter)) |
| 590 | return; |
| 591 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 592 | intel_desc_offset_add(&begin, &set->region_begin, &iter.offset_begin); |
| 593 | intel_desc_offset_add(&src_begin, &src_set->region_begin, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 594 | &src_iter.offset_end); |
| 595 | |
| 596 | /* advance to end */ |
| 597 | for (i = 0; i < update->count; i++) { |
| 598 | if (iter.type != update->descriptorType || |
| 599 | src_iter.type != update->descriptorType || |
| 600 | !intel_desc_layout_advance_iter(set->layout, &iter) || |
| 601 | !intel_desc_layout_advance_iter(src_set->layout, &src_iter)) |
| 602 | break; |
| 603 | } |
| 604 | if (i < update->count) |
| 605 | return; |
| 606 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 607 | intel_desc_offset_add(&end, &src_set->region_begin, &iter.offset_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 608 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 609 | intel_desc_region_copy(src_set->region, &begin, &end, &src_begin); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 610 | } |
| 611 | |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 612 | static void desc_set_read(const struct intel_desc_set *set, |
| 613 | const struct intel_desc_offset *offset, |
| 614 | const struct intel_desc_surface **surface, |
| 615 | const struct intel_desc_sampler **sampler) |
| 616 | { |
| 617 | struct intel_desc_offset begin, end; |
| 618 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 619 | intel_desc_offset_add(&begin, &set->region_begin, offset); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 620 | intel_desc_offset_set(&end, 0, 0); |
| 621 | |
| 622 | if (surface) { |
| 623 | *surface = (const struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 624 | ((const char *) set->region->surfaces + begin.surface); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 625 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 626 | end.surface = set->region->surface_desc_size; |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | if (sampler) { |
| 630 | *sampler = (const struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 631 | ((const char *) set->region->samplers + begin.sampler); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 632 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 633 | end.sampler = set->region->sampler_desc_size; |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | intel_desc_offset_add(&end, &begin, &end); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 637 | desc_region_validate_begin_end(set->region, &begin, &end); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | void intel_desc_set_read_surface(const struct intel_desc_set *set, |
| 641 | const struct intel_desc_offset *offset, |
| 642 | XGL_PIPELINE_SHADER_STAGE stage, |
| 643 | const struct intel_mem **mem, |
| 644 | bool *read_only, |
| 645 | const uint32_t **cmd, |
| 646 | uint32_t *cmd_len) |
| 647 | { |
| 648 | const struct intel_desc_surface *desc; |
| 649 | |
| 650 | desc_set_read(set, offset, &desc, NULL); |
| 651 | |
| 652 | *mem = desc->mem; |
| 653 | *read_only = desc->read_only; |
| 654 | switch (desc->type) { |
| 655 | case INTEL_DESC_SURFACE_BUF: |
| 656 | *cmd = (stage == XGL_SHADER_STAGE_FRAGMENT) ? |
| 657 | desc->u.buf->fs_cmd : desc->u.buf->cmd; |
| 658 | *cmd_len = desc->u.buf->cmd_len; |
| 659 | break; |
| 660 | case INTEL_DESC_SURFACE_IMG: |
| 661 | *cmd = desc->u.img->cmd; |
| 662 | *cmd_len = desc->u.img->cmd_len; |
| 663 | break; |
| 664 | case INTEL_DESC_SURFACE_UNUSED: |
| 665 | default: |
| 666 | *cmd = NULL; |
| 667 | *cmd_len = 0; |
| 668 | break; |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | void intel_desc_set_read_sampler(const struct intel_desc_set *set, |
| 673 | const struct intel_desc_offset *offset, |
| 674 | const struct intel_sampler **sampler) |
| 675 | { |
| 676 | const struct intel_desc_sampler *desc; |
| 677 | |
| 678 | desc_set_read(set, offset, NULL, &desc); |
| 679 | |
| 680 | *sampler = desc->sampler; |
| 681 | } |
| 682 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 683 | static void desc_layout_destroy(struct intel_obj *obj) |
| 684 | { |
| 685 | struct intel_desc_layout *layout = intel_desc_layout_from_obj(obj); |
| 686 | |
| 687 | intel_desc_layout_destroy(layout); |
| 688 | } |
| 689 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 690 | static XGL_RESULT desc_layout_init_bindings(struct intel_desc_layout *layout, |
| 691 | const struct intel_desc_region *region, |
| 692 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 693 | { |
| 694 | struct intel_desc_offset offset; |
| 695 | uint32_t index, i; |
| 696 | XGL_RESULT ret; |
| 697 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 698 | if (layout->prior_layout) { |
| 699 | index = layout->prior_layout->end; |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 700 | offset = layout->prior_layout->region_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 701 | } else { |
| 702 | index = 0; |
| 703 | intel_desc_offset_set(&offset, 0, 0); |
| 704 | } |
| 705 | |
| 706 | layout->begin = index; |
| 707 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 708 | /* allocate bindings */ |
| 709 | layout->bindings = intel_alloc(layout, sizeof(layout->bindings[0]) * |
| 710 | info->count, 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 711 | if (!layout->bindings) |
| 712 | return XGL_ERROR_OUT_OF_MEMORY; |
| 713 | |
| 714 | memset(layout->bindings, 0, sizeof(layout->bindings[0]) * info->count); |
| 715 | layout->binding_count = info->count; |
| 716 | |
| 717 | /* initialize bindings */ |
| 718 | for (i = 0; i < info->count; i++) { |
| 719 | const XGL_DESCRIPTOR_SET_LAYOUT_BINDING *lb = &info->pBinding[i]; |
| 720 | struct intel_desc_layout_binding *binding = &layout->bindings[i]; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 721 | struct intel_desc_offset size; |
| 722 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 723 | switch (lb->descriptorType) { |
| 724 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: |
| 725 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC: |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 726 | layout->dynamic_desc_count += lb->count; |
| 727 | break; |
| 728 | default: |
| 729 | break; |
| 730 | } |
| 731 | |
| 732 | ret = desc_region_get_desc_size(region, |
| 733 | lb->descriptorType, &size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 734 | if (ret != XGL_SUCCESS) |
| 735 | return ret; |
| 736 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 737 | /* lb->stageFlags does not gain us anything */ |
| 738 | binding->type = lb->descriptorType; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 739 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 740 | binding->begin = index; |
| 741 | binding->offset = offset; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 742 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 743 | if (lb->immutableSampler != XGL_NULL_HANDLE) { |
| 744 | binding->immutable_sampler = intel_sampler(lb->immutableSampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 745 | /* do not increment sampler offset */ |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 746 | intel_desc_offset_set(&binding->increment, size.surface, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 747 | } else { |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 748 | binding->immutable_sampler = NULL; |
| 749 | binding->increment = size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | /* increment index and offset */ |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 753 | index += lb->count; |
| 754 | intel_desc_offset_mad(&size, &binding->increment, &size, |
| 755 | lb->count - 1); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 756 | intel_desc_offset_add(&offset, &offset, &size); |
| 757 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 758 | binding->end = index; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | layout->end = index; |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 762 | layout->region_size = offset; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 763 | |
| 764 | return XGL_SUCCESS; |
| 765 | } |
| 766 | |
| 767 | static XGL_RESULT desc_layout_init_bind_points(struct intel_desc_layout *layout, |
| 768 | XGL_FLAGS stage_flags, |
| 769 | const uint32_t *bind_points) |
| 770 | { |
| 771 | if (!bind_points) |
| 772 | return XGL_ERROR_INVALID_POINTER; |
| 773 | |
| 774 | layout->stage_flags = stage_flags; |
| 775 | |
| 776 | if (stage_flags == XGL_SHADER_STAGE_FLAGS_ALL) { |
| 777 | layout->bind_point_vs = *bind_points; |
| 778 | layout->bind_point_tcs = *bind_points; |
| 779 | layout->bind_point_tes = *bind_points; |
| 780 | layout->bind_point_gs = *bind_points; |
| 781 | layout->bind_point_fs = *bind_points; |
| 782 | layout->bind_point_cs = *bind_points; |
| 783 | } else { |
| 784 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_VERTEX_BIT) |
| 785 | layout->bind_point_vs = *bind_points++; |
| 786 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_TESS_CONTROL_BIT) |
| 787 | layout->bind_point_tcs = *bind_points++; |
| 788 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_TESS_EVALUATION_BIT) |
| 789 | layout->bind_point_tes = *bind_points++; |
| 790 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_GEOMETRY_BIT) |
| 791 | layout->bind_point_gs = *bind_points++; |
| 792 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_FRAGMENT_BIT) |
| 793 | layout->bind_point_fs = *bind_points++; |
| 794 | if (stage_flags & XGL_SHADER_STAGE_FLAGS_COMPUTE_BIT) |
| 795 | layout->bind_point_cs = *bind_points++; |
| 796 | } |
| 797 | |
| 798 | return XGL_SUCCESS; |
| 799 | } |
| 800 | |
| 801 | XGL_RESULT intel_desc_layout_create(struct intel_dev *dev, |
| 802 | XGL_FLAGS stage_flags, |
| 803 | const uint32_t *bind_points, |
| 804 | const struct intel_desc_layout *prior_layout, |
| 805 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info, |
| 806 | struct intel_desc_layout **layout_ret) |
| 807 | { |
| 808 | struct intel_desc_layout *layout; |
| 809 | XGL_RESULT ret; |
| 810 | |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 811 | layout = (struct intel_desc_layout *) intel_base_create(&dev->base.handle, |
| 812 | sizeof(*layout), dev->base.dbg, |
| 813 | XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT, info, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 814 | if (!layout) |
| 815 | return XGL_ERROR_OUT_OF_MEMORY; |
| 816 | |
| 817 | layout->prior_layout = prior_layout; |
| 818 | |
| 819 | ret = desc_layout_init_bind_points(layout, stage_flags, bind_points); |
| 820 | if (ret == XGL_SUCCESS) |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 821 | ret = desc_layout_init_bindings(layout, dev->desc_region, info); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 822 | if (ret != XGL_SUCCESS) { |
| 823 | intel_desc_layout_destroy(layout); |
| 824 | return ret; |
| 825 | } |
| 826 | |
| 827 | layout->obj.destroy = desc_layout_destroy; |
| 828 | |
| 829 | *layout_ret = layout; |
| 830 | |
| 831 | return XGL_SUCCESS; |
| 832 | } |
| 833 | |
| 834 | void intel_desc_layout_destroy(struct intel_desc_layout *layout) |
| 835 | { |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 836 | intel_free(layout, layout->bindings); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 837 | intel_base_destroy(&layout->obj.base); |
| 838 | } |
| 839 | |
| 840 | static void desc_layout_init_iter(const struct intel_desc_layout *sublayout, |
| 841 | uint32_t index, |
| 842 | struct intel_desc_layout_iter *iter) |
| 843 | { |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 844 | const struct intel_desc_layout_binding *binding; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 845 | |
| 846 | assert(index >= sublayout->begin && index < sublayout->end); |
| 847 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 848 | /* find the binding the index is in */ |
| 849 | for (binding = sublayout->bindings;; binding++) { |
| 850 | assert(binding < sublayout->bindings + sublayout->binding_count); |
| 851 | if (index < binding->end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 852 | break; |
| 853 | } |
| 854 | |
| 855 | /* current position */ |
| 856 | iter->sublayout = sublayout; |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 857 | iter->binding = binding; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 858 | iter->index = index; |
| 859 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 860 | iter->type = iter->binding->type; |
| 861 | intel_desc_offset_mad(&iter->offset_begin, &binding->increment, |
| 862 | &binding->offset, iter->index - binding->begin); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 863 | intel_desc_offset_add(&iter->offset_end, &iter->offset_begin, |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 864 | &binding->increment); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 865 | } |
| 866 | |
| 867 | bool intel_desc_layout_find_bind_point(const struct intel_desc_layout *layout, |
| 868 | XGL_PIPELINE_SHADER_STAGE stage, |
| 869 | uint32_t set, uint32_t binding, |
| 870 | struct intel_desc_layout_iter *iter) |
| 871 | { |
| 872 | /* find the layout at the bind point */ |
| 873 | switch (stage) { |
| 874 | #define CASE(stage, s) \ |
| 875 | case XGL_SHADER_STAGE_ ##stage: \ |
| 876 | while (layout) { \ |
| 877 | if ((layout->stage_flags & \ |
| 878 | XGL_SHADER_STAGE_FLAGS_ ##stage## _BIT) && \ |
| 879 | layout->bind_point_ ##s == set) \ |
| 880 | break; \ |
| 881 | layout = layout->prior_layout; \ |
| 882 | } \ |
| 883 | break |
| 884 | CASE(VERTEX, vs); |
| 885 | CASE(TESS_CONTROL, tcs); |
| 886 | CASE(TESS_EVALUATION, tes); |
| 887 | CASE(GEOMETRY, gs); |
| 888 | CASE(FRAGMENT, fs); |
| 889 | CASE(COMPUTE, cs); |
| 890 | #undef CASE |
| 891 | default: |
| 892 | assert(!"unknown shader stage"); |
| 893 | layout = NULL; |
| 894 | break; |
| 895 | } |
| 896 | |
| 897 | if (!layout || layout->begin + binding >= layout->end) { |
| 898 | memset(iter, 0, sizeof(*iter)); |
| 899 | return false; |
| 900 | } |
| 901 | |
| 902 | desc_layout_init_iter(layout, layout->begin + binding, iter); |
| 903 | |
| 904 | return true; |
| 905 | } |
| 906 | |
| 907 | bool intel_desc_layout_find_index(const struct intel_desc_layout *layout, |
| 908 | uint32_t index, |
| 909 | struct intel_desc_layout_iter *iter) |
| 910 | { |
| 911 | if (index >= layout->begin) { |
| 912 | /* out of bound */ |
| 913 | if (index >= layout->end) |
| 914 | layout = NULL; |
| 915 | } else { |
| 916 | while (true) { |
| 917 | layout = layout->prior_layout; |
| 918 | if (index >= layout->begin) { |
| 919 | assert(index < layout->end); |
| 920 | break; |
| 921 | } |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | if (!layout) { |
| 926 | memset(iter, 0, sizeof(*iter)); |
| 927 | return false; |
| 928 | } |
| 929 | |
| 930 | desc_layout_init_iter(layout, index, iter); |
| 931 | |
| 932 | return true; |
| 933 | } |
| 934 | |
| 935 | bool intel_desc_layout_advance_iter(const struct intel_desc_layout *layout, |
| 936 | struct intel_desc_layout_iter *iter) |
| 937 | { |
| 938 | /* all descriptors traversed */ |
| 939 | if (!iter->sublayout) |
| 940 | return false; |
| 941 | |
| 942 | iter->index++; |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 943 | if (iter->index >= iter->binding->end) { |
| 944 | /* move to the next binding */ |
| 945 | iter->binding++; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 946 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 947 | if (iter->binding >= iter->sublayout->bindings + |
| 948 | iter->sublayout->binding_count) { |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 949 | /* find again as the chain is not doubly-linked */ |
| 950 | const bool ret = intel_desc_layout_find_index(layout, |
| 951 | iter->index, iter); |
| 952 | if (!ret) { |
| 953 | iter->sublayout = NULL; |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 954 | iter->binding = NULL; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 955 | } |
| 956 | |
| 957 | return ret; |
| 958 | } |
| 959 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 960 | iter->type = iter->binding->type; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | iter->offset_begin = iter->offset_end; |
| 964 | intel_desc_offset_add(&iter->offset_end, &iter->offset_end, |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 965 | &iter->binding->increment); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 966 | |
| 967 | return true; |
| 968 | } |
| 969 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 970 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayout( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 971 | XGL_DEVICE device, |
| 972 | XGL_FLAGS stageFlags, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 973 | const uint32_t* pSetBindPoints, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 974 | XGL_DESCRIPTOR_SET_LAYOUT priorSetLayout, |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 975 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO* pCreateInfo, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 976 | XGL_DESCRIPTOR_SET_LAYOUT* pSetLayout) |
| 977 | { |
| 978 | struct intel_dev *dev = intel_dev(device); |
| 979 | struct intel_desc_layout *prior_layout = intel_desc_layout(priorSetLayout); |
| 980 | |
| 981 | return intel_desc_layout_create(dev, stageFlags, pSetBindPoints, |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 982 | prior_layout, pCreateInfo, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 983 | (struct intel_desc_layout **) pSetLayout); |
| 984 | } |
| 985 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 986 | ICD_EXPORT XGL_RESULT XGLAPI xglBeginDescriptorPoolUpdate( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 987 | XGL_DEVICE device, |
| 988 | XGL_DESCRIPTOR_UPDATE_MODE updateMode) |
| 989 | { |
| 990 | struct intel_dev *dev = intel_dev(device); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 991 | struct intel_desc_region *region = dev->desc_region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 992 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 993 | return intel_desc_region_begin_update(region, updateMode); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 994 | } |
| 995 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 996 | ICD_EXPORT XGL_RESULT XGLAPI xglEndDescriptorPoolUpdate( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 997 | XGL_DEVICE device, |
| 998 | XGL_CMD_BUFFER cmd_) |
| 999 | { |
| 1000 | struct intel_dev *dev = intel_dev(device); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1001 | struct intel_desc_region *region = dev->desc_region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1002 | struct intel_cmd *cmd = intel_cmd(cmd_); |
| 1003 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1004 | return intel_desc_region_end_update(region, cmd); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1005 | } |
| 1006 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1007 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorPool( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1008 | XGL_DEVICE device, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1009 | XGL_DESCRIPTOR_POOL_USAGE poolUsage, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1010 | uint32_t maxSets, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1011 | const XGL_DESCRIPTOR_POOL_CREATE_INFO* pCreateInfo, |
| 1012 | XGL_DESCRIPTOR_POOL* pDescriptorPool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1013 | { |
| 1014 | struct intel_dev *dev = intel_dev(device); |
| 1015 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1016 | return intel_desc_pool_create(dev, poolUsage, maxSets, pCreateInfo, |
| 1017 | (struct intel_desc_pool **) pDescriptorPool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1018 | } |
| 1019 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 1020 | ICD_EXPORT XGL_RESULT XGLAPI xglResetDescriptorPool( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1021 | XGL_DESCRIPTOR_POOL descriptorPool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1022 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1023 | struct intel_desc_pool *pool = intel_desc_pool(descriptorPool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1024 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 1025 | intel_desc_pool_reset(pool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1026 | |
| 1027 | return XGL_SUCCESS; |
| 1028 | } |
| 1029 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 1030 | ICD_EXPORT XGL_RESULT XGLAPI xglAllocDescriptorSets( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1031 | XGL_DESCRIPTOR_POOL descriptorPool, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1032 | XGL_DESCRIPTOR_SET_USAGE setUsage, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1033 | uint32_t count, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1034 | const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayouts, |
| 1035 | XGL_DESCRIPTOR_SET* pDescriptorSets, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1036 | uint32_t* pCount) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1037 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1038 | struct intel_desc_pool *pool = intel_desc_pool(descriptorPool); |
| 1039 | struct intel_dev *dev = pool->dev; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1040 | XGL_RESULT ret = XGL_SUCCESS; |
| 1041 | uint32_t i; |
| 1042 | |
| 1043 | for (i = 0; i < count; i++) { |
| 1044 | const struct intel_desc_layout *layout = |
| 1045 | intel_desc_layout((XGL_DESCRIPTOR_SET_LAYOUT) pSetLayouts[i]); |
| 1046 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1047 | ret = intel_desc_set_create(dev, pool, setUsage, layout, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1048 | (struct intel_desc_set **) &pDescriptorSets[i]); |
| 1049 | if (ret != XGL_SUCCESS) |
| 1050 | break; |
| 1051 | } |
| 1052 | |
| 1053 | if (pCount) |
| 1054 | *pCount = i; |
| 1055 | |
| 1056 | return ret; |
| 1057 | } |
| 1058 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 1059 | ICD_EXPORT void XGLAPI xglClearDescriptorSets( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1060 | XGL_DESCRIPTOR_POOL descriptorPool, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1061 | uint32_t count, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1062 | const XGL_DESCRIPTOR_SET* pDescriptorSets) |
| 1063 | { |
| 1064 | uint32_t i; |
| 1065 | |
| 1066 | for (i = 0; i < count; i++) { |
| 1067 | struct intel_desc_set *set = |
| 1068 | intel_desc_set((XGL_DESCRIPTOR_SET) pDescriptorSets[i]); |
| 1069 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 1070 | intel_desc_region_clear(set->region, &set->region_begin, &set->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1071 | } |
| 1072 | } |
| 1073 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 1074 | ICD_EXPORT void XGLAPI xglUpdateDescriptors( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1075 | XGL_DESCRIPTOR_SET descriptorSet, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1076 | const void* pUpdateChain) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1077 | { |
| 1078 | struct intel_desc_set *set = intel_desc_set(descriptorSet); |
| 1079 | const union { |
| 1080 | struct { |
| 1081 | XGL_STRUCTURE_TYPE sType; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 1082 | const void* pNext; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1083 | } common; |
| 1084 | |
| 1085 | XGL_UPDATE_SAMPLERS samplers; |
| 1086 | XGL_UPDATE_SAMPLER_TEXTURES sampler_textures; |
| 1087 | XGL_UPDATE_IMAGES images; |
| 1088 | XGL_UPDATE_BUFFERS buffers; |
| 1089 | XGL_UPDATE_AS_COPY as_copy; |
| 1090 | } *u = pUpdateChain; |
| 1091 | |
| 1092 | while (u) { |
| 1093 | switch (u->common.sType) { |
| 1094 | case XGL_STRUCTURE_TYPE_UPDATE_SAMPLERS: |
| 1095 | intel_desc_set_update_samplers(set, &u->samplers); |
| 1096 | break; |
| 1097 | case XGL_STRUCTURE_TYPE_UPDATE_SAMPLER_TEXTURES: |
| 1098 | intel_desc_set_update_sampler_textures(set, &u->sampler_textures); |
| 1099 | break; |
| 1100 | case XGL_STRUCTURE_TYPE_UPDATE_IMAGES: |
| 1101 | intel_desc_set_update_images(set, &u->images); |
| 1102 | break; |
| 1103 | case XGL_STRUCTURE_TYPE_UPDATE_BUFFERS: |
| 1104 | intel_desc_set_update_buffers(set, &u->buffers); |
| 1105 | break; |
| 1106 | case XGL_STRUCTURE_TYPE_UPDATE_AS_COPY: |
| 1107 | intel_desc_set_update_as_copy(set, &u->as_copy); |
| 1108 | break; |
| 1109 | default: |
| 1110 | assert(!"unknown descriptor update"); |
| 1111 | break; |
| 1112 | } |
| 1113 | |
| 1114 | u = u->common.pNext; |
| 1115 | } |
| 1116 | } |