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Chia-I Wuf8385062015-01-04 16:27:24 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2015 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#ifndef DESC_H
29#define DESC_H
30
31#include "intel.h"
32#include "obj.h"
33
34struct intel_cmd;
35struct intel_dev;
36
37/**
38 * Opaque descriptors.
39 */
40struct intel_desc_surface;
41struct intel_desc_sampler;
42
43/**
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080044 * Descriptor region offset (or size) in bytes.
Chia-I Wuf8385062015-01-04 16:27:24 +080045 */
46struct intel_desc_offset {
47 uint32_t surface;
48 uint32_t sampler;
49};
50
51/**
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080052 * Per-device descriptor region.
Chia-I Wuf8385062015-01-04 16:27:24 +080053 */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080054struct intel_desc_region {
Chia-I Wuf8385062015-01-04 16:27:24 +080055 /* this is not an intel_obj */
56
57 uint32_t surface_desc_size;
58 uint32_t sampler_desc_size;
59
60 /* surface descriptors (in system memory until RS is enabled) */
61 struct intel_desc_surface *surfaces;
62 /* sampler desciptors */
63 struct intel_desc_sampler *samplers;
64
65 struct intel_desc_offset size;
66 struct intel_desc_offset cur;
67};
68
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080069struct intel_desc_pool {
Chia-I Wuf8385062015-01-04 16:27:24 +080070 struct intel_obj obj;
71
72 struct intel_dev *dev;
73
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080074 /* point to a continuous area in the device's region */
75 struct intel_desc_offset region_begin;
76 struct intel_desc_offset region_end;
Chia-I Wuf8385062015-01-04 16:27:24 +080077
78 struct intel_desc_offset cur;
79};
80
81struct intel_desc_layout;
82
83struct intel_desc_set {
84 struct intel_obj obj;
85
Chia-I Wu8d24b3b2015-03-26 13:14:16 +080086 /* suballocated from a pool */
87 struct intel_desc_region *region;
88 struct intel_desc_offset region_begin;
89 struct intel_desc_offset region_end;
Chia-I Wuf8385062015-01-04 16:27:24 +080090
91 const struct intel_desc_layout *layout;
92};
93
94struct intel_desc_layout {
95 struct intel_obj obj;
96
97 /* a chain of layouts actually */
98 const struct intel_desc_layout *prior_layout;
99
100 /* where this layout binds to in shader stages */
101 XGL_FLAGS stage_flags;
102 uint32_t bind_point_vs;
103 uint32_t bind_point_tcs;
104 uint32_t bind_point_tes;
105 uint32_t bind_point_gs;
106 uint32_t bind_point_fs;
107 uint32_t bind_point_cs;
108
109 /* the continuous area in the descriptor set this layout is for */
110 uint32_t begin;
111 uint32_t end;
112
Chia-I Wufc9d9132015-03-26 15:04:41 +0800113 /* homogeneous bindings in this layout */
114 struct intel_desc_layout_binding {
Chia-I Wuf8385062015-01-04 16:27:24 +0800115 XGL_DESCRIPTOR_TYPE type;
116 const struct intel_sampler *immutable_sampler;
117
118 /* to speed up intel_desc_layout_advance() */
119 uint32_t begin;
120 uint32_t end;
121 struct intel_desc_offset offset;
122 struct intel_desc_offset increment;
Chia-I Wufc9d9132015-03-26 15:04:41 +0800123 } *bindings;
124 uint32_t binding_count;
Chia-I Wuf8385062015-01-04 16:27:24 +0800125
126 /* count of _DYNAMIC descriptors */
127 uint32_t dynamic_desc_count;
128
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800129 /* the size of the entire layout chain in the region */
130 struct intel_desc_offset region_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800131};
132
133struct intel_desc_layout_iter {
134 /* current position in the chain of layouts */
135 const struct intel_desc_layout *sublayout;
Chia-I Wufc9d9132015-03-26 15:04:41 +0800136 const struct intel_desc_layout_binding *binding;
Chia-I Wuf8385062015-01-04 16:27:24 +0800137 uint32_t index;
138
139 XGL_DESCRIPTOR_TYPE type;
140 struct intel_desc_offset offset_begin;
141 struct intel_desc_offset offset_end;
142};
143
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800144static inline struct intel_desc_pool *intel_desc_pool(XGL_DESCRIPTOR_POOL pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800145{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800146 return (struct intel_desc_pool *) pool;
Chia-I Wuf8385062015-01-04 16:27:24 +0800147}
148
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800149static inline struct intel_desc_pool *intel_desc_pool_from_obj(struct intel_obj *obj)
Chia-I Wuf8385062015-01-04 16:27:24 +0800150{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800151 return (struct intel_desc_pool *) obj;
Chia-I Wuf8385062015-01-04 16:27:24 +0800152}
153
154static inline struct intel_desc_set *intel_desc_set(XGL_DESCRIPTOR_SET set)
155{
156 return (struct intel_desc_set *) set;
157}
158
159static inline struct intel_desc_set *intel_desc_set_from_obj(struct intel_obj *obj)
160{
161 return (struct intel_desc_set *) obj;
162}
163
164static inline struct intel_desc_layout *intel_desc_layout(XGL_DESCRIPTOR_SET_LAYOUT layout)
165{
166 return (struct intel_desc_layout *) layout;
167}
168
169static inline struct intel_desc_layout *intel_desc_layout_from_obj(struct intel_obj *obj)
170{
171 return (struct intel_desc_layout *) obj;
172}
173
174static inline void intel_desc_offset_set(struct intel_desc_offset *offset,
175 uint32_t surface_offset,
176 uint32_t sampler_offset)
177{
178 offset->surface = surface_offset;
179 offset->sampler = sampler_offset;
180}
181
182static inline void intel_desc_offset_add(struct intel_desc_offset *offset,
183 const struct intel_desc_offset *lhs,
184 const struct intel_desc_offset *rhs)
185{
186 offset->surface = lhs->surface + rhs->surface;
187 offset->sampler = lhs->sampler + rhs->sampler;
188}
189
190static inline void intel_desc_offset_sub(struct intel_desc_offset *offset,
191 const struct intel_desc_offset *lhs,
192 const struct intel_desc_offset *rhs)
193{
194 offset->surface = lhs->surface - rhs->surface;
195 offset->sampler = lhs->sampler - rhs->sampler;
196}
197
198static inline void intel_desc_offset_mad(struct intel_desc_offset *offset,
199 const struct intel_desc_offset *lhs,
200 const struct intel_desc_offset *rhs,
201 uint32_t lhs_scale)
202{
203 offset->surface = lhs->surface * lhs_scale + rhs->surface;
204 offset->sampler = lhs->sampler * lhs_scale + rhs->sampler;
205}
206
207static inline bool intel_desc_offset_within(const struct intel_desc_offset *offset,
208 const struct intel_desc_offset *other)
209{
210 return (offset->surface <= other->surface &&
211 offset->sampler <= other->sampler);
212}
213
Chia-I Wuf8385062015-01-04 16:27:24 +0800214XGL_RESULT intel_desc_region_create(struct intel_dev *dev,
Chia-I Wuf8385062015-01-04 16:27:24 +0800215 struct intel_desc_region **region_ret);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800216void intel_desc_region_destroy(struct intel_dev *dev,
217 struct intel_desc_region *region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800218
219XGL_RESULT intel_desc_region_alloc(struct intel_desc_region *region,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800220 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
Chia-I Wuf8385062015-01-04 16:27:24 +0800221 struct intel_desc_offset *begin,
222 struct intel_desc_offset *end);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800223void intel_desc_region_free(struct intel_desc_region *region,
224 const struct intel_desc_offset *begin,
225 const struct intel_desc_offset *end);
226
227XGL_RESULT intel_desc_region_begin_update(struct intel_desc_region *region,
228 XGL_DESCRIPTOR_UPDATE_MODE mode);
229XGL_RESULT intel_desc_region_end_update(struct intel_desc_region *region,
230 struct intel_cmd *cmd);
231
232void intel_desc_region_clear(struct intel_desc_region *region,
233 const struct intel_desc_offset *begin,
234 const struct intel_desc_offset *end);
235
236void intel_desc_region_update(struct intel_desc_region *region,
237 const struct intel_desc_offset *begin,
238 const struct intel_desc_offset *end,
239 const struct intel_desc_surface *surfaces,
240 const struct intel_desc_sampler *samplers);
241
242void intel_desc_region_copy(struct intel_desc_region *region,
243 const struct intel_desc_offset *begin,
244 const struct intel_desc_offset *end,
245 const struct intel_desc_offset *src);
246
247XGL_RESULT intel_desc_pool_create(struct intel_dev *dev,
248 XGL_DESCRIPTOR_POOL_USAGE usage,
249 uint32_t max_sets,
250 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
251 struct intel_desc_pool **pool_ret);
252void intel_desc_pool_destroy(struct intel_desc_pool *pool);
253
254XGL_RESULT intel_desc_pool_alloc(struct intel_desc_pool *pool,
255 const struct intel_desc_layout *layout,
256 struct intel_desc_offset *begin,
257 struct intel_desc_offset *end);
Chia-I Wudee95612015-03-26 15:23:52 +0800258void intel_desc_pool_reset(struct intel_desc_pool *pool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800259
260XGL_RESULT intel_desc_set_create(struct intel_dev *dev,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800261 struct intel_desc_pool *pool,
Chia-I Wuf8385062015-01-04 16:27:24 +0800262 XGL_DESCRIPTOR_SET_USAGE usage,
263 const struct intel_desc_layout *layout,
264 struct intel_desc_set **set_ret);
265void intel_desc_set_destroy(struct intel_desc_set *set);
266
267void intel_desc_set_update_samplers(struct intel_desc_set *set,
268 const XGL_UPDATE_SAMPLERS *update);
269void intel_desc_set_update_sampler_textures(struct intel_desc_set *set,
270 const XGL_UPDATE_SAMPLER_TEXTURES *update);
271void intel_desc_set_update_images(struct intel_desc_set *set,
272 const XGL_UPDATE_IMAGES *update);
273void intel_desc_set_update_buffers(struct intel_desc_set *set,
274 const XGL_UPDATE_BUFFERS *update);
275void intel_desc_set_update_as_copy(struct intel_desc_set *set,
276 const XGL_UPDATE_AS_COPY *update);
277
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700278void intel_desc_set_read_surface(const struct intel_desc_set *set,
279 const struct intel_desc_offset *offset,
280 XGL_PIPELINE_SHADER_STAGE stage,
281 const struct intel_mem **mem,
282 bool *read_only,
283 const uint32_t **cmd,
284 uint32_t *cmd_len);
285void intel_desc_set_read_sampler(const struct intel_desc_set *set,
286 const struct intel_desc_offset *offset,
287 const struct intel_sampler **sampler);
288
Chia-I Wuf8385062015-01-04 16:27:24 +0800289XGL_RESULT intel_desc_layout_create(struct intel_dev *dev,
290 XGL_FLAGS stage_flags,
291 const uint32_t *bind_points,
292 const struct intel_desc_layout *prior_layout,
293 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info,
294 struct intel_desc_layout **layout_ret);
295void intel_desc_layout_destroy(struct intel_desc_layout *layout);
296
297bool intel_desc_layout_find_bind_point(const struct intel_desc_layout *layout,
298 XGL_PIPELINE_SHADER_STAGE stage,
299 uint32_t set, uint32_t binding,
300 struct intel_desc_layout_iter *iter);
301
302bool intel_desc_layout_find_index(const struct intel_desc_layout *layout,
303 uint32_t index,
304 struct intel_desc_layout_iter *iter);
305
306bool intel_desc_layout_advance_iter(const struct intel_desc_layout *layout,
307 struct intel_desc_layout_iter *iter);
308
309#endif /* DESC_H */