blob: e408700583bbe96672d86963b5e3ce87dba61237 [file] [log] [blame]
Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "kmd/winsys.h"
Chia-I Wu34f45182014-08-19 14:02:59 +080026#include "cmd.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080027#include "dev.h"
Chia-I Wuc5438c22014-08-19 14:03:06 +080028#include "fence.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080029#include "queue.h"
30
Chia-I Wu9ae59c12014-08-07 10:08:49 +080031XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +080032 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +080033 struct intel_queue **queue_ret)
Chia-I Wue09b5362014-08-07 09:25:14 +080034{
35 struct intel_queue *queue;
Chia-I Wuc5438c22014-08-19 14:03:06 +080036 enum intel_ring_type ring;
37
Chia-I Wucdcff732014-08-19 14:44:15 +080038 switch (engine) {
39 case INTEL_GPU_ENGINE_3D:
Chia-I Wuc5438c22014-08-19 14:03:06 +080040 ring = INTEL_RING_RENDER;
41 break;
Chia-I Wuc5438c22014-08-19 14:03:06 +080042 default:
43 return XGL_ERROR_INVALID_VALUE;
44 break;
45 }
Chia-I Wue09b5362014-08-07 09:25:14 +080046
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060047 queue = (struct intel_queue *) intel_base_create(dev, sizeof(*queue),
Chia-I Wubbf2c932014-08-07 12:20:08 +080048 dev->base.dbg, XGL_DBG_OBJECT_QUEUE, NULL, 0);
Chia-I Wue09b5362014-08-07 09:25:14 +080049 if (!queue)
Chia-I Wu9ae59c12014-08-07 10:08:49 +080050 return XGL_ERROR_OUT_OF_MEMORY;
Chia-I Wue09b5362014-08-07 09:25:14 +080051
Chia-I Wue09b5362014-08-07 09:25:14 +080052 queue->dev = dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +080053 queue->ring = ring;
Chia-I Wue09b5362014-08-07 09:25:14 +080054
Chia-I Wu9ae59c12014-08-07 10:08:49 +080055 *queue_ret = queue;
56
57 return XGL_SUCCESS;
Chia-I Wue09b5362014-08-07 09:25:14 +080058}
59
60void intel_queue_destroy(struct intel_queue *queue)
61{
Chia-I Wubbf2c932014-08-07 12:20:08 +080062 intel_base_destroy(&queue->base);
Chia-I Wue09b5362014-08-07 09:25:14 +080063}
64
65XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout)
66{
Chia-I Wue24c3292014-08-21 14:05:23 +080067 struct intel_bo *bo = (queue->last_submitted_cmd) ?
68 intel_cmd_get_batch(queue->last_submitted_cmd, NULL) : NULL;
Chia-I Wue09b5362014-08-07 09:25:14 +080069
Chia-I Wue24c3292014-08-21 14:05:23 +080070 return (!bo || intel_bo_wait(bo, timeout) == 0) ?
Chia-I Wue09b5362014-08-07 09:25:14 +080071 XGL_SUCCESS : XGL_ERROR_UNKNOWN;
72}
73
Chia-I Wuc5438c22014-08-19 14:03:06 +080074XGL_RESULT intel_queue_submit(struct intel_queue *queue,
75 struct intel_cmd *cmd)
76{
77 struct intel_winsys *winsys = queue->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080078 struct intel_bo *bo;
79 XGL_GPU_SIZE used;
Chia-I Wuc5438c22014-08-19 14:03:06 +080080 int err;
81
Chia-I Wue24c3292014-08-21 14:05:23 +080082 bo = intel_cmd_get_batch(cmd, &used);
Courtney Goeltzenleuchterbc407eb2014-08-22 17:54:03 -060083
Chia-I Wu1c527012014-08-23 14:57:35 +080084 if (intel_debug & INTEL_DEBUG_BATCH)
85 intel_winsys_decode_bo(winsys, bo, used);
Courtney Goeltzenleuchterbc407eb2014-08-22 17:54:03 -060086
Chia-I Wue24c3292014-08-21 14:05:23 +080087 err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0);
Chia-I Wuc5438c22014-08-19 14:03:06 +080088
89 queue->last_submitted_cmd = cmd;
90
91 return (err) ? XGL_ERROR_UNKNOWN : XGL_SUCCESS;
92}
93
Chia-I Wue09b5362014-08-07 09:25:14 +080094XGL_RESULT XGLAPI intelQueueSetGlobalMemReferences(
95 XGL_QUEUE queue,
96 XGL_UINT memRefCount,
97 const XGL_MEMORY_REF* pMemRefs)
98{
99 /*
100 * The winwys maintains the list of memory references. These are ignored
101 * until we move away from the winsys.
102 */
103 return XGL_SUCCESS;
104}
105
106XGL_RESULT XGLAPI intelQueueWaitIdle(
107 XGL_QUEUE queue_)
108{
109 struct intel_queue *queue = intel_queue(queue_);
110
111 return intel_queue_wait(queue, -1);
112}
Chia-I Wu251e7d92014-08-19 13:35:42 +0800113
114XGL_RESULT XGLAPI intelQueueSubmit(
Chia-I Wuc5438c22014-08-19 14:03:06 +0800115 XGL_QUEUE queue_,
Chia-I Wu251e7d92014-08-19 13:35:42 +0800116 XGL_UINT cmdBufferCount,
117 const XGL_CMD_BUFFER* pCmdBuffers,
118 XGL_UINT memRefCount,
119 const XGL_MEMORY_REF* pMemRefs,
Chia-I Wuc5438c22014-08-19 14:03:06 +0800120 XGL_FENCE fence_)
Chia-I Wu251e7d92014-08-19 13:35:42 +0800121{
Chia-I Wuc5438c22014-08-19 14:03:06 +0800122 struct intel_queue *queue = intel_queue(queue_);
123 XGL_RESULT ret = XGL_SUCCESS;
124 XGL_UINT i;
125
126 for (i = 0; i < cmdBufferCount; i++) {
127 struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
128
129 ret = intel_queue_submit(queue, cmd);
130 if (ret != XGL_SUCCESS)
131 break;
132 }
133
134 if (ret == XGL_SUCCESS && fence_ != XGL_NULL_HANDLE) {
135 struct intel_fence *fence = intel_fence(fence_);
136 intel_fence_set_cmd(fence, queue->last_submitted_cmd);
137 }
138
139 /* XGL_MEMORY_REFs are ignored as the winsys already knows them */
140
141 return ret;
Chia-I Wu251e7d92014-08-19 13:35:42 +0800142}
143
144XGL_RESULT XGLAPI intelOpenSharedQueueSemaphore(
145 XGL_DEVICE device,
146 const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo,
147 XGL_QUEUE_SEMAPHORE* pSemaphore)
148{
149 return XGL_ERROR_UNAVAILABLE;
150}
151
152XGL_RESULT XGLAPI intelCreateQueueSemaphore(
153 XGL_DEVICE device,
154 const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo,
155 XGL_QUEUE_SEMAPHORE* pSemaphore)
156{
157 /*
158 * We want to find an unused semaphore register and initialize it. Signal
159 * will increment the register. Wait will atomically decrement it and
160 * block if the value is zero, or a large constant N if we do not want to
161 * go negative.
162 *
163 * XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility.
164 */
165 return XGL_ERROR_UNAVAILABLE;
166}
167
168XGL_RESULT XGLAPI intelSignalQueueSemaphore(
169 XGL_QUEUE queue,
170 XGL_QUEUE_SEMAPHORE semaphore)
171{
172 return XGL_ERROR_UNAVAILABLE;
173}
174
175XGL_RESULT XGLAPI intelWaitQueueSemaphore(
176 XGL_QUEUE queue,
177 XGL_QUEUE_SEMAPHORE semaphore)
178{
179 return XGL_ERROR_UNAVAILABLE;
180}