blob: b7cdef36177cb00d5a75cff0d73188a97abcf293 [file] [log] [blame]
Chia-I Wu82f50aa2014-08-05 10:43:03 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "dispatch_tables.h"
26#include "gpu.h"
27#include "obj.h"
28
29/**
30 * Return true if an (not so) arbitrary pointer casted to intel_base points to
31 * a valid intel_base. This assumes at least the first sizeof(void*) bytes of
32 * the address are accessible, and they does not happen to be our magic
33 * values.
34 */
35bool intel_base_is_valid(const struct intel_base *base)
36{
37 if (base->dispatch != &intel_normal_dispatch_table &&
38 base->dispatch != &intel_debug_dispatch_table)
39 return false;
40
41 return !intel_gpu_is_valid((const struct intel_gpu *) base);
42}
43
Chia-I Wu26f0bd02014-08-07 10:38:40 +080044XGL_RESULT intel_base_get_info(struct intel_base *base, int type,
45 XGL_SIZE *size, XGL_VOID *data)
46{
47 XGL_RESULT ret = XGL_SUCCESS;
48 XGL_SIZE s;
49
50 switch (type) {
51 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
52 s = sizeof(XGL_MEMORY_REQUIREMENTS);
53 memset(data, 0, s);
54 *size = s;
55 break;
56 default:
57 ret = XGL_ERROR_INVALID_VALUE;
58 break;
59 }
60
61 return ret;
62}
63
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080064static bool base_dbg_copy_create_info(struct intel_base_dbg *dbg,
65 const void *create_info)
66{
67 const union {
68 const void *ptr;
69 const struct {
70 XGL_STRUCTURE_TYPE struct_type;
71 XGL_VOID *next;
72 } *header;
73 } info = { .ptr = create_info };
74 XGL_SIZE shallow_copy = 0;
75
76 if (!create_info)
77 return true;
78
79 switch (info.header->struct_type) {
80 case XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO:
81 assert(dbg->type == XGL_DBG_OBJECT_DEVICE);
82 break;
83 case XGL_STRUCTURE_TYPE_MEMORY_ALLOC_INFO:
84 assert(dbg->type == XGL_DBG_OBJECT_GPU_MEMORY);
85 shallow_copy = sizeof(XGL_MEMORY_ALLOC_INFO);
86 break;
87 case XGL_STRUCTURE_TYPE_EVENT_CREATE_INFO:
88 assert(dbg->type == XGL_DBG_OBJECT_EVENT);
89 shallow_copy = sizeof(XGL_EVENT_CREATE_INFO);
90 break;
91 case XGL_STRUCTURE_TYPE_FENCE_CREATE_INFO:
92 assert(dbg->type == XGL_DBG_OBJECT_FENCE);
93 shallow_copy = sizeof(XGL_FENCE_CREATE_INFO);
94 break;
95 default:
96 return false;
97 break;
98 }
99
100 if (shallow_copy) {
101 assert(!info.header->next);
102
103 dbg->create_info = icd_alloc(shallow_copy, 0, XGL_SYSTEM_ALLOC_DEBUG);
104 if (!dbg->create_info)
105 return false;
106
107 memcpy(dbg->create_info, create_info, shallow_copy);
108 } else if (info.header->struct_type ==
109 XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO) {
110 const XGL_DEVICE_CREATE_INFO *src = info.ptr;
111 XGL_DEVICE_CREATE_INFO *dst;
112 uint8_t *d;
113 XGL_SIZE size;
114 XGL_UINT i;
115
116 size = sizeof(*src);
117 size += sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
118 size += sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
119 for (i = 0; i < src->extensionCount; i++) {
120 size += 1 +
121 strlen((const char *) src->ppEnabledExtensionNames[i]);
122 }
123
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800124 dst = icd_alloc(size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800125 if (!dst)
126 return false;
127
128 memcpy(dst, src, sizeof(*src));
129
130 d = (uint8_t *) dst;
131 d += sizeof(*src);
132
133 size = sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
134 memcpy(d, src->pRequestedQueues, size);
135 dst->pRequestedQueues = (const XGL_DEVICE_QUEUE_CREATE_INFO *) d;
136 d += size;
137
138 size = sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
139 dst->ppEnabledExtensionNames = (const XGL_CHAR * const *) d;
140
141 for (i = 0; i < src->extensionCount; i++) {
142 const XGL_SIZE len =
143 strlen((const char *) src->ppEnabledExtensionNames[i]);
144
145 memcpy(d + size, src->ppEnabledExtensionNames[i], len + 1);
146 ((const XGL_CHAR **) d)[i] = (const XGL_CHAR *) (d + size);
147
148 size += len + 1;
149 }
150 }
151
152 return true;
153}
154
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800155/**
Chia-I Wu660caf82014-08-07 10:54:26 +0800156 * Create an intel_base_dbg. When alloc_size is non-zero, a buffer of that
157 * size is allocated and zeroed.
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800158 */
Chia-I Wu660caf82014-08-07 10:54:26 +0800159struct intel_base_dbg *intel_base_dbg_create(XGL_DBG_OBJECT_TYPE type,
160 const void *create_info,
Chia-I Wu660caf82014-08-07 10:54:26 +0800161 XGL_SIZE alloc_size)
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800162{
Chia-I Wu660caf82014-08-07 10:54:26 +0800163 struct intel_base_dbg *dbg;
164
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800165 if (!alloc_size)
Chia-I Wu660caf82014-08-07 10:54:26 +0800166 alloc_size = sizeof(*dbg);
167
168 assert(alloc_size >= sizeof(*dbg));
169
170 dbg = icd_alloc(alloc_size, 0, XGL_SYSTEM_ALLOC_DEBUG);
171 if (!dbg)
172 return NULL;
173
174 memset(dbg, 0, alloc_size);
175
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800176 dbg->alloc_id = icd_get_allocator_id();
177 dbg->type = type;
178
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800179 if (!base_dbg_copy_create_info(dbg, create_info)) {
180 icd_free(dbg);
181 return NULL;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800182 }
183
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800184 return dbg;
185}
186
187void intel_base_dbg_destroy(struct intel_base_dbg *dbg)
188{
Chia-I Wu660caf82014-08-07 10:54:26 +0800189 if (dbg->tag)
190 icd_free(dbg->tag);
191
192 if (dbg->create_info)
193 icd_free(dbg->create_info);
194
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800195 icd_free(dbg);
196}
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800197
198XGL_RESULT XGLAPI intelDestroyObject(
199 XGL_OBJECT object)
200{
201 struct intel_obj *obj = intel_obj(object);
202
203 obj->destroy(obj);
204
205 return XGL_SUCCESS;
206}
207
208XGL_RESULT XGLAPI intelGetObjectInfo(
209 XGL_BASE_OBJECT object,
210 XGL_OBJECT_INFO_TYPE infoType,
211 XGL_SIZE* pDataSize,
212 XGL_VOID* pData)
213{
214 struct intel_base *base = intel_base(object);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800215
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800216 return base->get_info(base, infoType, pDataSize, pData);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800217}
218
219XGL_RESULT XGLAPI intelBindObjectMemory(
220 XGL_OBJECT object,
221 XGL_GPU_MEMORY mem,
222 XGL_GPU_SIZE offset)
223{
224 struct intel_obj *obj = intel_obj(object);
225
226 obj->mem = mem;
227 obj->offset = offset;
228
229 return XGL_SUCCESS;
230}