blob: 419b2672e9b6c070eb8c12aa065a2b3663bc446e [file] [log] [blame]
Chia-I Wue54854a2014-08-05 10:23:50 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wue54854a2014-08-05 10:23:50 +080026 */
27
28#ifndef DEV_H
29#define DEV_H
30
Chia-I Wue09b5362014-08-07 09:25:14 +080031#include "intel.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080032#include "gpu.h"
Chia-I Wua2161db2014-08-15 16:34:34 +080033#include "obj.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080034
Chia-I Wue54854a2014-08-05 10:23:50 +080035struct intel_queue;
36struct intel_winsys;
37
38struct intel_dev_dbg_msg_filter {
39 XGL_INT msg_code;
40 XGL_DBG_MSG_FILTER filter;
41 bool triggered;
42
43 struct intel_dev_dbg_msg_filter *next;
44};
45
46struct intel_dev_dbg {
47 struct intel_base_dbg base;
48
Chia-I Wu069f30f2014-08-21 13:45:20 +080049 XGL_VALIDATION_LEVEL validation_level;
50 bool disable_pipeline_loads;
51 bool force_object_memory_reqs;
52 bool force_large_image_alignment;
53
Chia-I Wue54854a2014-08-05 10:23:50 +080054 struct intel_dev_dbg_msg_filter *filters;
55};
56
57struct intel_dev {
58 struct intel_base base;
59
Chia-I Wu1db76e02014-09-15 14:21:14 +080060 bool exts[INTEL_EXT_COUNT];
61
Chia-I Wue54854a2014-08-05 10:23:50 +080062 struct intel_gpu *gpu;
63 struct intel_winsys *winsys;
Chia-I Wu0b784442014-08-25 22:54:16 +080064 struct intel_bo *cmd_scratch_bo;
65
Chia-I Wue54854a2014-08-05 10:23:50 +080066 struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT];
67};
68
Chia-I Wue54854a2014-08-05 10:23:50 +080069static inline struct intel_dev *intel_dev(XGL_DEVICE dev)
70{
71 return (struct intel_dev *) dev;
72}
73
74static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev)
75{
76 return (struct intel_dev_dbg *) dev->base.dbg;
77}
78
Chia-I Wue54854a2014-08-05 10:23:50 +080079XGL_RESULT intel_dev_create(struct intel_gpu *gpu,
80 const XGL_DEVICE_CREATE_INFO *info,
81 struct intel_dev **dev_ret);
82void intel_dev_destroy(struct intel_dev *dev);
83
84void intel_dev_get_heap_props(const struct intel_dev *dev,
85 XGL_MEMORY_HEAP_PROPERTIES *props);
86
87XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev,
88 XGL_INT msg_code,
89 XGL_DBG_MSG_FILTER filter);
90
91void intel_dev_remove_msg_filter(struct intel_dev *dev,
92 XGL_INT msg_code);
93
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080094void intel_dev_log(struct intel_dev *dev,
95 XGL_DBG_MSG_TYPE msg_type,
96 XGL_VALIDATION_LEVEL validation_level,
Chia-I Wuaabb3602014-08-19 14:18:23 +080097 struct intel_base *src_object,
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080098 XGL_SIZE location,
99 XGL_INT msg_code,
100 const char *format, ...);
101
Chia-I Wua207aba2014-08-05 15:13:37 +0800102XGL_RESULT XGLAPI intelCreateDevice(
103 XGL_PHYSICAL_GPU gpu,
104 const XGL_DEVICE_CREATE_INFO* pCreateInfo,
105 XGL_DEVICE* pDevice);
106
107XGL_RESULT XGLAPI intelDestroyDevice(
108 XGL_DEVICE device);
109
110XGL_RESULT XGLAPI intelGetMemoryHeapCount(
111 XGL_DEVICE device,
112 XGL_UINT* pCount);
113
114XGL_RESULT XGLAPI intelGetMemoryHeapInfo(
115 XGL_DEVICE device,
116 XGL_UINT heapId,
117 XGL_MEMORY_HEAP_INFO_TYPE infoType,
118 XGL_SIZE* pDataSize,
119 XGL_VOID* pData);
120
Chia-I Wu49dbee82014-08-06 12:48:47 +0800121XGL_RESULT XGLAPI intelGetDeviceQueue(
122 XGL_DEVICE device,
123 XGL_QUEUE_TYPE queueType,
124 XGL_UINT queueIndex,
125 XGL_QUEUE* pQueue);
126
Chia-I Wu49dbee82014-08-06 12:48:47 +0800127XGL_RESULT XGLAPI intelDeviceWaitIdle(
128 XGL_DEVICE device);
129
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800130XGL_RESULT XGLAPI intelDbgSetValidationLevel(
131 XGL_DEVICE device,
132 XGL_VALIDATION_LEVEL validationLevel);
133
134XGL_RESULT XGLAPI intelDbgSetMessageFilter(
135 XGL_DEVICE device,
136 XGL_INT msgCode,
137 XGL_DBG_MSG_FILTER filter);
138
139XGL_RESULT XGLAPI intelDbgSetDeviceOption(
140 XGL_DEVICE device,
141 XGL_DBG_DEVICE_OPTION dbgOption,
142 XGL_SIZE dataSize,
143 const XGL_VOID* pData);
144
Chia-I Wue54854a2014-08-05 10:23:50 +0800145#endif /* DEV_H */