Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #ifndef DEV_H |
| 26 | #define DEV_H |
| 27 | |
Chia-I Wu | e09b536 | 2014-08-07 09:25:14 +0800 | [diff] [blame] | 28 | #include "intel.h" |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 29 | #include "gpu.h" |
Chia-I Wu | a2161db | 2014-08-15 16:34:34 +0800 | [diff] [blame] | 30 | #include "obj.h" |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 31 | |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 32 | struct intel_queue; |
| 33 | struct intel_winsys; |
| 34 | |
| 35 | struct intel_dev_dbg_msg_filter { |
| 36 | XGL_INT msg_code; |
| 37 | XGL_DBG_MSG_FILTER filter; |
| 38 | bool triggered; |
| 39 | |
| 40 | struct intel_dev_dbg_msg_filter *next; |
| 41 | }; |
| 42 | |
| 43 | struct intel_dev_dbg { |
| 44 | struct intel_base_dbg base; |
| 45 | |
| 46 | struct intel_dev_dbg_msg_filter *filters; |
| 47 | }; |
| 48 | |
| 49 | struct intel_dev { |
| 50 | struct intel_base base; |
| 51 | |
| 52 | struct intel_gpu *gpu; |
| 53 | struct intel_winsys *winsys; |
| 54 | struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT]; |
Chia-I Wu | 7ec9f34 | 2014-08-19 10:47:53 +0800 | [diff] [blame] | 55 | |
| 56 | XGL_VALIDATION_LEVEL validation_level; |
| 57 | bool disable_pipeline_loads; |
| 58 | bool force_object_memory_reqs; |
| 59 | bool force_large_image_alignment; |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 60 | }; |
| 61 | |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 62 | static inline struct intel_dev *intel_dev(XGL_DEVICE dev) |
| 63 | { |
| 64 | return (struct intel_dev *) dev; |
| 65 | } |
| 66 | |
| 67 | static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev) |
| 68 | { |
| 69 | return (struct intel_dev_dbg *) dev->base.dbg; |
| 70 | } |
| 71 | |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 72 | XGL_RESULT intel_dev_create(struct intel_gpu *gpu, |
| 73 | const XGL_DEVICE_CREATE_INFO *info, |
| 74 | struct intel_dev **dev_ret); |
| 75 | void intel_dev_destroy(struct intel_dev *dev); |
| 76 | |
| 77 | void intel_dev_get_heap_props(const struct intel_dev *dev, |
| 78 | XGL_MEMORY_HEAP_PROPERTIES *props); |
| 79 | |
| 80 | XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev, |
| 81 | XGL_INT msg_code, |
| 82 | XGL_DBG_MSG_FILTER filter); |
| 83 | |
| 84 | void intel_dev_remove_msg_filter(struct intel_dev *dev, |
| 85 | XGL_INT msg_code); |
| 86 | |
Chia-I Wu | 82d3d8b | 2014-08-09 13:07:44 +0800 | [diff] [blame] | 87 | void intel_dev_log(struct intel_dev *dev, |
| 88 | XGL_DBG_MSG_TYPE msg_type, |
| 89 | XGL_VALIDATION_LEVEL validation_level, |
Chia-I Wu | aabb360 | 2014-08-19 14:18:23 +0800 | [diff] [blame^] | 90 | struct intel_base *src_object, |
Chia-I Wu | 82d3d8b | 2014-08-09 13:07:44 +0800 | [diff] [blame] | 91 | XGL_SIZE location, |
| 92 | XGL_INT msg_code, |
| 93 | const char *format, ...); |
| 94 | |
Chia-I Wu | a207aba | 2014-08-05 15:13:37 +0800 | [diff] [blame] | 95 | XGL_RESULT XGLAPI intelCreateDevice( |
| 96 | XGL_PHYSICAL_GPU gpu, |
| 97 | const XGL_DEVICE_CREATE_INFO* pCreateInfo, |
| 98 | XGL_DEVICE* pDevice); |
| 99 | |
| 100 | XGL_RESULT XGLAPI intelDestroyDevice( |
| 101 | XGL_DEVICE device); |
| 102 | |
| 103 | XGL_RESULT XGLAPI intelGetMemoryHeapCount( |
| 104 | XGL_DEVICE device, |
| 105 | XGL_UINT* pCount); |
| 106 | |
| 107 | XGL_RESULT XGLAPI intelGetMemoryHeapInfo( |
| 108 | XGL_DEVICE device, |
| 109 | XGL_UINT heapId, |
| 110 | XGL_MEMORY_HEAP_INFO_TYPE infoType, |
| 111 | XGL_SIZE* pDataSize, |
| 112 | XGL_VOID* pData); |
| 113 | |
Chia-I Wu | 49dbee8 | 2014-08-06 12:48:47 +0800 | [diff] [blame] | 114 | XGL_RESULT XGLAPI intelGetDeviceQueue( |
| 115 | XGL_DEVICE device, |
| 116 | XGL_QUEUE_TYPE queueType, |
| 117 | XGL_UINT queueIndex, |
| 118 | XGL_QUEUE* pQueue); |
| 119 | |
Chia-I Wu | 49dbee8 | 2014-08-06 12:48:47 +0800 | [diff] [blame] | 120 | XGL_RESULT XGLAPI intelDeviceWaitIdle( |
| 121 | XGL_DEVICE device); |
| 122 | |
Chia-I Wu | 7ec9f34 | 2014-08-19 10:47:53 +0800 | [diff] [blame] | 123 | XGL_RESULT XGLAPI intelDbgSetValidationLevel( |
| 124 | XGL_DEVICE device, |
| 125 | XGL_VALIDATION_LEVEL validationLevel); |
| 126 | |
| 127 | XGL_RESULT XGLAPI intelDbgSetMessageFilter( |
| 128 | XGL_DEVICE device, |
| 129 | XGL_INT msgCode, |
| 130 | XGL_DBG_MSG_FILTER filter); |
| 131 | |
| 132 | XGL_RESULT XGLAPI intelDbgSetDeviceOption( |
| 133 | XGL_DEVICE device, |
| 134 | XGL_DBG_DEVICE_OPTION dbgOption, |
| 135 | XGL_SIZE dataSize, |
| 136 | const XGL_VOID* pData); |
| 137 | |
Chia-I Wu | e54854a | 2014-08-05 10:23:50 +0800 | [diff] [blame] | 138 | #endif /* DEV_H */ |