blob: 9037b8d115ce1fafe8d77ab70687d653330f1418 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070035#include "fb.h"
Chia-I Wu09142132014-08-11 15:42:55 +080036
Chia-I Wu3c3edc02014-09-09 10:32:59 +080037/**
38 * Free all resources used by a writer. Note that the initial size is not
39 * reset.
40 */
41static void cmd_writer_reset(struct intel_cmd *cmd,
42 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080043{
Chia-I Wu68f319d2014-09-09 09:43:21 +080044 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080045
Chia-I Wu3c3edc02014-09-09 10:32:59 +080046 if (writer->ptr) {
47 intel_bo_unmap(writer->bo);
48 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080049 }
50
Chia-I Wucb2dc0d2015-03-05 16:19:42 -070051 intel_bo_unref(writer->bo);
52 writer->bo = NULL;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080053
Chia-I Wue24c3292014-08-21 14:05:23 +080054 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080055
Chia-I Wuf98dd882015-02-10 04:17:47 +080056 writer->sba_offset = 0;
57
Chia-I Wu00b51a82014-09-09 12:07:37 +080058 if (writer->items) {
Chia-I Wuf9c81ef2015-02-22 13:49:15 +080059 intel_free(cmd, writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060060 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080061 writer->item_alloc = 0;
62 writer->item_used = 0;
63 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080064}
65
66/**
67 * Discard everything written so far.
68 */
69static void cmd_writer_discard(struct intel_cmd *cmd,
70 enum intel_cmd_writer_type which)
71{
72 struct intel_cmd_writer *writer = &cmd->writers[which];
73
74 intel_bo_truncate_relocs(writer->bo, 0);
75 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080076 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080077}
78
79static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
80 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060081 size_t size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080082{
83 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
84 [INTEL_CMD_WRITER_BATCH] = "batch",
Chia-I Wu15cccf72015-02-10 04:07:40 +080085 [INTEL_CMD_WRITER_SURFACE] = "surface",
86 [INTEL_CMD_WRITER_STATE] = "state",
Chia-I Wu3c3edc02014-09-09 10:32:59 +080087 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
88 };
89
Chia-I Wucb2dc0d2015-03-05 16:19:42 -070090 return intel_winsys_alloc_bo(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080091}
92
93/**
94 * Allocate and map the buffer for writing.
95 */
96static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
97 enum intel_cmd_writer_type which)
98{
99 struct intel_cmd_writer *writer = &cmd->writers[which];
100 struct intel_bo *bo;
101
102 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
103 if (bo) {
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700104 intel_bo_unref(writer->bo);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800105 writer->bo = bo;
106 } else if (writer->bo) {
107 /* reuse the old bo */
108 cmd_writer_discard(cmd, which);
109 } else {
110 return XGL_ERROR_OUT_OF_GPU_MEMORY;
111 }
112
113 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800114 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800115
116 writer->ptr = intel_bo_map(writer->bo, true);
117 if (!writer->ptr)
118 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800119
120 return XGL_SUCCESS;
121}
122
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800123/**
124 * Unmap the buffer for submission.
125 */
126static void cmd_writer_unmap(struct intel_cmd *cmd,
127 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800128{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800129 struct intel_cmd_writer *writer = &cmd->writers[which];
130
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800131 intel_bo_unmap(writer->bo);
132 writer->ptr = NULL;
133}
134
135/**
136 * Grow a mapped writer to at least \p new_size. Failures are handled
137 * silently.
138 */
139void cmd_writer_grow(struct intel_cmd *cmd,
140 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600141 size_t new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800142{
143 struct intel_cmd_writer *writer = &cmd->writers[which];
144 struct intel_bo *new_bo;
145 void *new_ptr;
146
147 if (new_size < writer->size << 1)
148 new_size = writer->size << 1;
149 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800150 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800151
152 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
153 if (!new_bo) {
154 cmd_writer_discard(cmd, which);
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700155 cmd_fail(cmd, XGL_ERROR_OUT_OF_GPU_MEMORY);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800156 return;
157 }
158
159 /* map and copy the data over */
160 new_ptr = intel_bo_map(new_bo, true);
161 if (!new_ptr) {
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700162 intel_bo_unref(new_bo);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800163 cmd_writer_discard(cmd, which);
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700164 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800165 return;
166 }
167
Chia-I Wu72292b72014-09-09 10:48:33 +0800168 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800169
170 intel_bo_unmap(writer->bo);
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700171 intel_bo_unref(writer->bo);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800172
173 writer->size = new_size;
174 writer->bo = new_bo;
175 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800176}
177
Chia-I Wu00b51a82014-09-09 12:07:37 +0800178/**
179 * Record an item for later decoding.
180 */
181void cmd_writer_record(struct intel_cmd *cmd,
182 enum intel_cmd_writer_type which,
183 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600184 size_t offset, size_t size)
Chia-I Wu00b51a82014-09-09 12:07:37 +0800185{
186 struct intel_cmd_writer *writer = &cmd->writers[which];
187 struct intel_cmd_item *item;
188
189 if (writer->item_used == writer->item_alloc) {
190 const unsigned new_alloc = (writer->item_alloc) ?
191 writer->item_alloc << 1 : 256;
192 struct intel_cmd_item *items;
193
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800194 items = intel_alloc(cmd, sizeof(writer->items[0]) * new_alloc,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800195 0, XGL_SYSTEM_ALLOC_DEBUG);
196 if (!items) {
197 writer->item_used = 0;
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700198 cmd_fail(cmd, XGL_ERROR_OUT_OF_MEMORY);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800199 return;
200 }
201
202 memcpy(items, writer->items,
203 sizeof(writer->items[0]) * writer->item_alloc);
204
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800205 intel_free(cmd, writer->items);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800206
207 writer->items = items;
208 writer->item_alloc = new_alloc;
209 }
210
211 item = &writer->items[writer->item_used++];
212 item->type = type;
213 item->offset = offset;
214 item->size = size;
215}
216
Chia-I Wu5e25c272014-08-21 20:19:12 +0800217static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800218 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600219 size_t offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800220{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800221 struct intel_cmd_writer *writer = &cmd->writers[which];
222
Chia-I Wu72292b72014-09-09 10:48:33 +0800223 assert(offset + sizeof(val) <= writer->used);
224 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800225}
226
Chia-I Wu730e5362014-08-19 12:15:09 +0800227static void cmd_reset(struct intel_cmd *cmd)
228{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600229 uint32_t i;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800230
231 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
232 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800233
Chia-I Wua57761b2014-10-14 14:27:44 +0800234 if (cmd->bind.shader_cache.entries)
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800235 intel_free(cmd, cmd->bind.shader_cache.entries);
Chia-I Wua57761b2014-10-14 14:27:44 +0800236
Chia-I Wuf8385062015-01-04 16:27:24 +0800237 if (cmd->bind.dset.graphics_dynamic_offsets)
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800238 intel_free(cmd, cmd->bind.dset.graphics_dynamic_offsets);
Chia-I Wuf8385062015-01-04 16:27:24 +0800239 if (cmd->bind.dset.compute_dynamic_offsets)
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800240 intel_free(cmd, cmd->bind.dset.compute_dynamic_offsets);
Chia-I Wuf8385062015-01-04 16:27:24 +0800241
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800242 memset(&cmd->bind, 0, sizeof(cmd->bind));
243
Chia-I Wu343b1372014-08-20 16:39:20 +0800244 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800245 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800246}
247
248static void cmd_destroy(struct intel_obj *obj)
249{
250 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
251
252 intel_cmd_destroy(cmd);
253}
254
255XGL_RESULT intel_cmd_create(struct intel_dev *dev,
256 const XGL_CMD_BUFFER_CREATE_INFO *info,
257 struct intel_cmd **cmd_ret)
258{
Chia-I Wu63883292014-08-25 13:50:26 +0800259 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800260 struct intel_cmd *cmd;
261
Chia-I Wu63883292014-08-25 13:50:26 +0800262 switch (info->queueType) {
263 case XGL_QUEUE_TYPE_GRAPHICS:
264 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
265 break;
266 case XGL_QUEUE_TYPE_COMPUTE:
267 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
268 break;
269 case XGL_QUEUE_TYPE_DMA:
270 pipeline_select = -1;
271 break;
272 default:
273 return XGL_ERROR_INVALID_VALUE;
274 break;
275 }
276
Chia-I Wu545c2e12015-02-22 13:19:54 +0800277 cmd = (struct intel_cmd *) intel_base_create(&dev->base.handle,
278 sizeof(*cmd), dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
Chia-I Wu730e5362014-08-19 12:15:09 +0800279 if (!cmd)
280 return XGL_ERROR_OUT_OF_MEMORY;
281
282 cmd->obj.destroy = cmd_destroy;
283
284 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800285 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800286 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800287
Chia-I Wue0cdd832014-08-25 12:38:56 +0800288 /*
289 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
290 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
291 * and end offsets, for each referenced memories.
292 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800293 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800294 cmd->relocs = intel_alloc(cmd, sizeof(cmd->relocs[0]) * cmd->reloc_count,
Chia-I Wu343b1372014-08-20 16:39:20 +0800295 4096, XGL_SYSTEM_ALLOC_INTERNAL);
296 if (!cmd->relocs) {
297 intel_cmd_destroy(cmd);
298 return XGL_ERROR_OUT_OF_MEMORY;
299 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800300
301 *cmd_ret = cmd;
302
303 return XGL_SUCCESS;
304}
305
306void intel_cmd_destroy(struct intel_cmd *cmd)
307{
308 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800309
Chia-I Wuf9c81ef2015-02-22 13:49:15 +0800310 intel_free(cmd, cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800311 intel_base_destroy(&cmd->obj.base);
312}
313
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700314XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu730e5362014-08-19 12:15:09 +0800315{
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700316 const XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *ginfo;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800317 XGL_RESULT ret;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600318 uint32_t i;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700319 XGL_FLAGS flags = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800320
321 cmd_reset(cmd);
322
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700323 while (info != NULL) {
324 switch (info->sType) {
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700325 case XGL_STRUCTURE_TYPE_CMD_BUFFER_BEGIN_INFO:
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700326 flags = info->flags;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700327 break;
328 case XGL_STRUCTURE_TYPE_CMD_BUFFER_GRAPHICS_BEGIN_INFO:
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700329 ginfo = (const XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *) info;
330 cmd_begin_render_pass(cmd, intel_render_pass(ginfo->renderPass));
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700331 break;
332 default:
333 return XGL_ERROR_INVALID_VALUE;
334 break;
335 }
Chia-I Wuc6025ac2015-02-18 14:59:11 -0700336
337 info = (const XGL_CMD_BUFFER_BEGIN_INFO*) info->pNext;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700338 }
339
Chia-I Wu24565ee2014-08-21 20:24:31 +0800340 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800341 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800342 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800343 }
344
Chia-I Wu68f319d2014-09-09 09:43:21 +0800345 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600346 const uint32_t size = cmd->dev->gpu->max_batch_buffer_size / 2;
347 uint32_t divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800348
349 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
350 divider *= 4;
351
Chia-I Wu68f319d2014-09-09 09:43:21 +0800352 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800353 cmd->writers[INTEL_CMD_WRITER_SURFACE].size = size / divider / 2;
354 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider / 2;
Chia-I Wu72292b72014-09-09 10:48:33 +0800355 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800356 }
357
Chia-I Wu68f319d2014-09-09 09:43:21 +0800358 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800359 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800360 if (ret != XGL_SUCCESS) {
361 cmd_reset(cmd);
362 return ret;
363 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800364 }
365
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800366 cmd_batch_begin(cmd);
367
Chia-I Wu24565ee2014-08-21 20:24:31 +0800368 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800369}
370
371XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
372{
373 struct intel_winsys *winsys = cmd->dev->winsys;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600374 uint32_t i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800375
Chia-I Wub8762122014-12-01 22:51:03 +0800376 /* no matching intel_cmd_begin() */
377 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].ptr)
378 return XGL_ERROR_INCOMPLETE_COMMAND_BUFFER;
379
Chia-I Wue24c3292014-08-21 14:05:23 +0800380 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800381
Chia-I Wu343b1372014-08-20 16:39:20 +0800382 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800383 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800384 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800385 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800386 uint64_t presumed_offset;
387 int err;
388
Chia-I Wud7d1e482014-10-18 13:25:10 +0800389 /*
390 * Once a bo is used as a reloc target, libdrm_intel disallows more
391 * relocs to be added to it. That may happen when
392 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
393 * in another pass.
394 */
395 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
396 continue;
397
Chia-I Wu72292b72014-09-09 10:48:33 +0800398 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800399 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800400 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800401 if (err) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700402 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wu343b1372014-08-20 16:39:20 +0800403 break;
404 }
405
406 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800407 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800408 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800409 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800410 for (i = 0; i < cmd->reloc_used; i++) {
411 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
412 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
413 uint64_t presumed_offset;
414 int err;
415
416 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
417 continue;
418
419 err = intel_bo_add_reloc(writer->bo, reloc->offset,
420 cmd->writers[reloc->target].bo, reloc->target_offset,
421 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
422 &presumed_offset);
423 if (err) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700424 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wud7d1e482014-10-18 13:25:10 +0800425 break;
426 }
427
428 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
429 cmd_writer_patch(cmd, reloc->which, reloc->offset,
430 (uint32_t) presumed_offset);
431 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800432
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800433 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
434 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800435
Chia-I Wu04966702014-08-20 15:05:03 +0800436 if (cmd->result != XGL_SUCCESS)
437 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800438
Chia-I Wu68f319d2014-09-09 09:43:21 +0800439 if (intel_winsys_can_submit_bo(winsys,
440 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800441 return XGL_SUCCESS;
442 else
443 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
444}
445
Chia-I Wu96177272015-01-03 15:27:41 +0800446ICD_EXPORT XGL_RESULT XGLAPI xglCreateCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800447 XGL_DEVICE device,
448 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
449 XGL_CMD_BUFFER* pCmdBuffer)
450{
Chia-I Wu730e5362014-08-19 12:15:09 +0800451 struct intel_dev *dev = intel_dev(device);
452
453 return intel_cmd_create(dev, pCreateInfo,
454 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800455}
456
Chia-I Wu96177272015-01-03 15:27:41 +0800457ICD_EXPORT XGL_RESULT XGLAPI xglBeginCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800458 XGL_CMD_BUFFER cmdBuffer,
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700459 const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu09142132014-08-11 15:42:55 +0800460{
Chia-I Wu730e5362014-08-19 12:15:09 +0800461 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
462
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700463 return intel_cmd_begin(cmd, info);
Chia-I Wu09142132014-08-11 15:42:55 +0800464}
465
Chia-I Wu96177272015-01-03 15:27:41 +0800466ICD_EXPORT XGL_RESULT XGLAPI xglEndCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800467 XGL_CMD_BUFFER cmdBuffer)
468{
Chia-I Wu730e5362014-08-19 12:15:09 +0800469 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
470
471 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800472}
473
Chia-I Wu96177272015-01-03 15:27:41 +0800474ICD_EXPORT XGL_RESULT XGLAPI xglResetCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800475 XGL_CMD_BUFFER cmdBuffer)
476{
Chia-I Wu730e5362014-08-19 12:15:09 +0800477 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
478
479 cmd_reset(cmd);
480
481 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800482}
483
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600484ICD_EXPORT void XGLAPI xglCmdInitAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800485 XGL_CMD_BUFFER cmdBuffer,
486 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600487 uint32_t startCounter,
488 uint32_t counterCount,
489 const uint32_t* pData)
Chia-I Wu09142132014-08-11 15:42:55 +0800490{
491}
492
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600493ICD_EXPORT void XGLAPI xglCmdLoadAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800494 XGL_CMD_BUFFER cmdBuffer,
495 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600496 uint32_t startCounter,
497 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800498 XGL_BUFFER srcBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800499 XGL_GPU_SIZE srcOffset)
500{
501}
502
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600503ICD_EXPORT void XGLAPI xglCmdSaveAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800504 XGL_CMD_BUFFER cmdBuffer,
505 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600506 uint32_t startCounter,
507 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800508 XGL_BUFFER destBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800509 XGL_GPU_SIZE destOffset)
510{
511}
512
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600513ICD_EXPORT void XGLAPI xglCmdDbgMarkerBegin(
Chia-I Wu09142132014-08-11 15:42:55 +0800514 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600515 const char* pMarker)
Chia-I Wu09142132014-08-11 15:42:55 +0800516{
517}
518
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600519ICD_EXPORT void XGLAPI xglCmdDbgMarkerEnd(
Chia-I Wu09142132014-08-11 15:42:55 +0800520 XGL_CMD_BUFFER cmdBuffer)
521{
522}