blob: b4ca65db140cf59f47603f208b91fc01a35c13ee [file] [log] [blame]
Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "img.h"
29#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080030#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080031#include "cmd_priv.h"
32
33static void cmd_meta_init_mem_view(struct intel_cmd *cmd,
34 XGL_GPU_MEMORY mem,
35 XGL_GPU_SIZE range,
36 XGL_FORMAT format,
37 XGL_MEMORY_STATE state,
38 struct intel_mem_view *view)
39{
40 XGL_MEMORY_VIEW_ATTACH_INFO info;
41
42 memset(&info, 0, sizeof(info));
43 info.sType = XGL_STRUCTURE_TYPE_MEMORY_VIEW_ATTACH_INFO;
44 info.mem = mem;
45 info.range = range;
46 info.stride = icd_format_get_size(format);
47 info.format = format;
48 info.state = state;
49
50 intel_mem_view_init(view, cmd->dev, &info);
51}
52
53static void cmd_meta_set_src_for_mem(struct intel_cmd *cmd,
54 const struct intel_mem *mem,
55 XGL_FORMAT format,
56 struct intel_cmd_meta *meta)
57{
58 struct intel_mem_view view;
59
60 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
61 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
62
63 meta->src.valid = true;
64
65 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
66 meta->src.surface_len = view.cmd_len;
67
68 meta->src.reloc_target = (intptr_t) mem->bo;
69 meta->src.reloc_offset = 0;
70 meta->src.reloc_flags = 0;
71}
72
73static void cmd_meta_set_dst_for_mem(struct intel_cmd *cmd,
74 const struct intel_mem *mem,
75 XGL_FORMAT format,
76 struct intel_cmd_meta *meta)
77{
78 struct intel_mem_view view;
79
80 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
81 XGL_MEMORY_STATE_GRAPHICS_SHADER_WRITE_ONLY, &view);
82
83 meta->dst.valid = true;
84
85 memcpy(meta->dst.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
86 meta->dst.surface_len = view.cmd_len;
87
88 meta->dst.reloc_target = (intptr_t) mem->bo;
89 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +080090 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +080091}
92
93static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
94 const struct intel_img *img,
95 XGL_FORMAT format,
96 XGL_IMAGE_ASPECT aspect,
97 struct intel_cmd_meta *meta)
98{
99 XGL_IMAGE_VIEW_CREATE_INFO info;
100 struct intel_img_view *view;
101 XGL_RESULT ret;
102
103 memset(&info, 0, sizeof(info));
104 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
105 info.image = (XGL_IMAGE) img;
106
107 switch (img->type) {
108 case XGL_IMAGE_1D:
109 info.viewType = XGL_IMAGE_VIEW_1D;
110 break;
111 case XGL_IMAGE_2D:
112 info.viewType = XGL_IMAGE_VIEW_2D;
113 break;
114 case XGL_IMAGE_3D:
115 info.viewType = XGL_IMAGE_VIEW_3D;
116 break;
117 default:
118 break;
119 }
120
121 info.format = format;
122 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
123 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
124 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
125 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
126 info.subresourceRange.aspect = aspect;
127 info.subresourceRange.baseMipLevel = 0;
128 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
129 info.subresourceRange.baseArraySlice = 0;
130 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
131
132 ret = intel_img_view_create(cmd->dev, &info, &view);
133 if (ret != XGL_SUCCESS) {
134 cmd->result = ret;
135 return;
136 }
137
138 meta->src.valid = true;
139
140 memcpy(meta->src.surface, view->cmd,
141 sizeof(view->cmd[0]) * view->cmd_len);
142 meta->src.surface_len = view->cmd_len;
143
144 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
145 meta->src.reloc_offset = 0;
146 meta->src.reloc_flags = 0;
147
148 intel_img_view_destroy(view);
149}
150
151static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
152 const struct intel_img *img,
153 XGL_FORMAT format,
154 XGL_UINT lod, XGL_UINT layer,
155 struct intel_cmd_meta *meta)
156{
157 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
158 struct intel_rt_view *rt;
159 XGL_RESULT ret;
160
161 memset(&info, 0, sizeof(info));
162 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
163 info.image = (XGL_IMAGE) img;
164 info.format = format;
165 info.mipLevel = lod;
166 info.baseArraySlice = layer;
167 info.arraySize = 1;
168
169 ret = intel_rt_view_create(cmd->dev, &info, &rt);
170 if (ret != XGL_SUCCESS) {
171 cmd->result = ret;
172 return;
173 }
174
175 meta->dst.valid = true;
176
177 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
178 meta->dst.surface_len = rt->cmd_len;
179
180 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
181 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800182 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800183
184 intel_rt_view_destroy(rt);
185}
186
187static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
188 enum intel_cmd_writer_type writer,
189 XGL_GPU_SIZE size,
190 XGL_FORMAT format,
191 struct intel_cmd_meta *meta)
192{
193 struct intel_mem_view view;
194
195 cmd_meta_init_mem_view(cmd, XGL_NULL_HANDLE, size, format,
196 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
197
198 meta->src.valid = true;
199
200 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
201 meta->src.surface_len = view.cmd_len;
202
203 meta->src.reloc_target = (intptr_t) writer;
204 meta->src.reloc_offset = 0;
205 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
206}
207
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800208static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
209 const struct intel_img *img,
210 XGL_UINT lod, XGL_UINT layer,
211 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800212{
213 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
214 struct intel_ds_view *ds;
215 XGL_RESULT ret;
216
217 memset(&info, 0, sizeof(info));
218 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
219 info.image = (XGL_IMAGE) img;
220 info.mipLevel = lod;
221 info.baseArraySlice = layer;
222 info.arraySize = 1;
223
224 ret = intel_ds_view_create(cmd->dev, &info, &ds);
225 if (ret != XGL_SUCCESS) {
226 cmd->result = ret;
227 return;
228 }
229
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800230 meta->ds.view = ds;
231}
232
233static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
234 XGL_IMAGE_ASPECT aspect,
235 XGL_UINT32 stencil_ref,
236 struct intel_cmd_meta *meta)
237{
238 XGL_DEPTH_STENCIL_STATE_CREATE_INFO info;
239 struct intel_ds_state *state;
240 XGL_RESULT ret;
241
242 memset(&info, 0, sizeof(info));
243 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO;
244
245 if (aspect == XGL_IMAGE_ASPECT_DEPTH) {
246 info.depthWriteEnable = XGL_TRUE;
247 }
248 else if (aspect == XGL_IMAGE_ASPECT_STENCIL) {
249 info.stencilTestEnable = XGL_TRUE;
250 info.stencilReadMask = 0xff;
251 info.stencilWriteMask = 0xff;
252 info.front.stencilFailOp = XGL_STENCIL_OP_KEEP;
253 info.front.stencilPassOp = XGL_STENCIL_OP_REPLACE;
254 info.front.stencilDepthFailOp = XGL_STENCIL_OP_KEEP;
255 info.front.stencilFunc = XGL_COMPARE_ALWAYS;
256 info.front.stencilRef = stencil_ref;
257 info.back = info.front;
258 }
259
260 ret = intel_ds_state_create(cmd->dev, &info, &state);
261 if (ret != XGL_SUCCESS) {
262 cmd->result = ret;
263 return;
264 }
265
266 meta->ds.state = state;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800267}
268
269static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
270 const struct intel_img *img,
271 bool copy_array)
272{
273 enum intel_dev_meta_shader shader_id;
274
275 switch (img->type) {
276 case XGL_IMAGE_1D:
277 shader_id = (copy_array) ?
278 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
279 break;
280 case XGL_IMAGE_2D:
281 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
282 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
283 INTEL_DEV_META_FS_COPY_2D;
284 break;
285 case XGL_IMAGE_3D:
286 default:
287 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
288 break;
289 }
290
291 return shader_id;
292}
293
294/**
295 * Return the suitable format for copying between memories. The
296 * format is sampleable, renderable, and the offsets and copy size are
297 * multiples of the format size.
298 */
299static XGL_CHANNEL_FORMAT cmd_meta_mem_channel_format(const struct intel_cmd *cmd,
300 XGL_GPU_SIZE src_offset,
301 XGL_GPU_SIZE dst_offset,
302 XGL_GPU_SIZE size,
303 XGL_SIZE *format_size)
304{
305 const XGL_GPU_SIZE align = (src_offset | dst_offset | size) & 0xf;
306
307 if (align & 0x1) {
308 *format_size = 1;
309 return XGL_CH_FMT_R8;
310 } else if (align & 0x2) {
311 *format_size = 2;
312 return XGL_CH_FMT_R16;
313 } else if (align & 0x4) {
314 *format_size = 4;
315 return XGL_CH_FMT_R32;
316 } else if (align & 0x8) {
317 *format_size = 8;
318 return XGL_CH_FMT_R32G32;
319 } else {
320 *format_size = 16;
321 return XGL_CH_FMT_R32G32B32A32;
322 }
323}
324
325static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
326 XGL_FORMAT format)
327{
328 format.numericFormat = XGL_NUM_FMT_UINT;
329
330 if (icd_format_is_compressed(format)) {
331 switch (icd_format_get_size(format)) {
332 case 1:
333 format.channelFormat = XGL_CH_FMT_R8;
334 break;
335 case 2:
336 format.channelFormat = XGL_CH_FMT_R16;
337 break;
338 case 4:
339 format.channelFormat = XGL_CH_FMT_R32;
340 break;
341 case 8:
342 format.channelFormat = XGL_CH_FMT_R32G32;
343 break;
344 case 16:
345 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
346 break;
347 default:
348 assert(!"unsupported compressed block size");
349 format.channelFormat = XGL_CH_FMT_R8;
350 break;
351 }
352 }
353
354 return format;
355}
356
357XGL_VOID XGLAPI intelCmdCopyMemory(
358 XGL_CMD_BUFFER cmdBuffer,
359 XGL_GPU_MEMORY srcMem,
360 XGL_GPU_MEMORY destMem,
361 XGL_UINT regionCount,
362 const XGL_MEMORY_COPY* pRegions)
363{
364 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
365 struct intel_mem *src = intel_mem(srcMem);
366 struct intel_mem *dst = intel_mem(destMem);
367 struct intel_cmd_meta meta;
368 XGL_FORMAT format;
369 XGL_UINT i;
370
371 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800372 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800373
374 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM;
375 meta.height = 1;
376 meta.samples = 1;
377
378 format.channelFormat = XGL_CH_FMT_UNDEFINED;
379 format.numericFormat = XGL_NUM_FMT_UINT;
380
381 for (i = 0; i < regionCount; i++) {
382 const XGL_MEMORY_COPY *region = &pRegions[i];
383 XGL_CHANNEL_FORMAT ch;
384 XGL_SIZE format_size;
385
386 ch = cmd_meta_mem_channel_format(cmd, region->srcOffset,
387 region->destOffset, region->copySize, &format_size);
388
389 if (format.channelFormat != ch) {
390 format.channelFormat = ch;
391
392 cmd_meta_set_src_for_mem(cmd, src, format, &meta);
393 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
394 }
395
396 meta.src.x = region->srcOffset / format_size;
397 meta.dst.x = region->destOffset / format_size;
398 meta.width = region->copySize / format_size;
399
400 cmd_draw_meta(cmd, &meta);
401 }
402}
403
404XGL_VOID XGLAPI intelCmdCopyImage(
405 XGL_CMD_BUFFER cmdBuffer,
406 XGL_IMAGE srcImage,
407 XGL_IMAGE destImage,
408 XGL_UINT regionCount,
409 const XGL_IMAGE_COPY* pRegions)
410{
411 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
412 struct intel_img *src = intel_img(srcImage);
413 struct intel_img *dst = intel_img(destImage);
414 struct intel_cmd_meta meta;
415 XGL_FORMAT raw_format;
416 bool raw_copy;
417 XGL_UINT i;
418
419 if (src->type != dst->type) {
420 cmd->result = XGL_ERROR_UNKNOWN;
421 return;
422 }
423
424 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
425 raw_copy = true;
426 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
427 } else if (icd_format_is_compressed(src->layout.format) ||
428 icd_format_is_compressed(dst->layout.format)) {
429 cmd->result = XGL_ERROR_UNKNOWN;
430 return;
431 }
432
433 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800434 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800435
436 cmd_meta_set_src_for_img(cmd, src,
437 (raw_copy) ? raw_format : src->layout.format,
438 XGL_IMAGE_ASPECT_COLOR, &meta);
439
440 meta.samples = dst->samples;
441
442 for (i = 0; i < regionCount; i++) {
443 const XGL_IMAGE_COPY *region = &pRegions[i];
444 XGL_UINT j;
445
446 meta.shader_id = get_shader_id(cmd->dev, src,
447 (region->extent.depth > 1));
448
449 meta.src.lod = region->srcSubresource.mipLevel;
450 meta.src.layer = region->srcSubresource.arraySlice +
451 region->srcOffset.z;
452 meta.src.x = region->srcOffset.x;
453 meta.src.y = region->srcOffset.y;
454
455 meta.dst.lod = region->destSubresource.mipLevel;
456 meta.dst.layer = region->destSubresource.arraySlice +
457 region->destOffset.z;
458 meta.dst.x = region->destOffset.x;
459 meta.dst.y = region->destOffset.y;
460
461 meta.width = region->extent.width;
462 meta.height = region->extent.height;
463
464 for (j = 0; j < region->extent.depth; j++) {
465 cmd_meta_set_dst_for_img(cmd, dst,
466 (raw_copy) ? raw_format : dst->layout.format,
467 meta.dst.lod, meta.dst.layer, &meta);
468
469 cmd_draw_meta(cmd, &meta);
470
471 meta.src.layer++;
472 meta.dst.layer++;
473 }
474 }
475}
476
477XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
478 XGL_CMD_BUFFER cmdBuffer,
479 XGL_GPU_MEMORY srcMem,
480 XGL_IMAGE destImage,
481 XGL_UINT regionCount,
482 const XGL_MEMORY_IMAGE_COPY* pRegions)
483{
484 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
485 struct intel_mem *mem = intel_mem(srcMem);
486 struct intel_img *img = intel_img(destImage);
487 struct intel_cmd_meta meta;
488 XGL_FORMAT format;
489 XGL_UINT i;
490
491 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800492 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800493
494 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
495 meta.samples = img->samples;
496
497 format = cmd_meta_img_raw_format(cmd, img->layout.format);
498 cmd_meta_set_src_for_mem(cmd, mem, format, &meta);
499
500 for (i = 0; i < regionCount; i++) {
501 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
502 XGL_UINT j;
503
504 meta.src.x = region->memOffset / icd_format_get_size(format);
505
506 meta.dst.lod = region->imageSubresource.mipLevel;
507 meta.dst.layer = region->imageSubresource.arraySlice +
508 region->imageOffset.z;
509 meta.dst.x = region->imageOffset.x;
510 meta.dst.y = region->imageOffset.y;
511
512 meta.width = region->imageExtent.width;
513 meta.height = region->imageExtent.height;
514
515 for (j = 0; j < region->imageExtent.depth; j++) {
516 cmd_meta_set_dst_for_img(cmd, img, format,
517 meta.dst.lod, meta.dst.layer, &meta);
518
519 cmd_draw_meta(cmd, &meta);
520
521 meta.src.x += meta.width * meta.height;
522 meta.dst.layer++;
523 }
524 }
525}
526
527XGL_VOID XGLAPI intelCmdCopyImageToMemory(
528 XGL_CMD_BUFFER cmdBuffer,
529 XGL_IMAGE srcImage,
530 XGL_GPU_MEMORY destMem,
531 XGL_UINT regionCount,
532 const XGL_MEMORY_IMAGE_COPY* pRegions)
533{
534 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
535 struct intel_img *img = intel_img(srcImage);
536 struct intel_mem *mem = intel_mem(destMem);
537 struct intel_cmd_meta meta;
538 XGL_FORMAT format;
539 XGL_UINT i;
540
541 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800542 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800543
544 format = cmd_meta_img_raw_format(cmd, img->layout.format);
545 cmd_meta_set_src_for_img(cmd, img, format, XGL_IMAGE_ASPECT_COLOR, &meta);
546 cmd_meta_set_dst_for_mem(cmd, mem, format, &meta);
547
548 meta.height = 1;
549 meta.samples = 1;
550
551 for (i = 0; i < regionCount; i++) {
552 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
553 XGL_UINT j;
554
555 meta.shader_id = get_shader_id(cmd->dev, img,
556 (region->imageExtent.depth > 1));
557
558 meta.src.lod = region->imageSubresource.mipLevel;
559 meta.src.layer = region->imageSubresource.arraySlice +
560 region->imageOffset.z;
561 meta.src.x = region->imageOffset.x;
562 meta.src.y = region->imageOffset.y;
563
564 meta.dst.x = region->memOffset / icd_format_get_size(format);
565
566 meta.width = region->imageExtent.width * region->imageExtent.height;
567
568 for (j = 0; j < region->imageExtent.depth; j++) {
569 cmd_draw_meta(cmd, &meta);
570
571 meta.src.layer++;
572 meta.dst.x += meta.width;
573 }
574 }
575}
576
577XGL_VOID XGLAPI intelCmdCloneImageData(
578 XGL_CMD_BUFFER cmdBuffer,
579 XGL_IMAGE srcImage,
580 XGL_IMAGE_STATE srcImageState,
581 XGL_IMAGE destImage,
582 XGL_IMAGE_STATE destImageState)
583{
584 const struct intel_img *src = intel_img(srcImage);
585 XGL_IMAGE_COPY region;
586 XGL_UINT lv;
587
588 memset(&region, 0, sizeof(region));
589 region.srcSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
590 region.destSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
591
592 for (lv = 0; lv < src->mip_levels; lv++) {
593 region.srcSubresource.mipLevel = lv;
594 region.destSubresource.mipLevel = lv;
595
596 region.extent.width = u_minify(src->layout.width0, lv);
597 region.extent.height = u_minify(src->layout.height0, lv);
598 region.extent.depth = src->array_size;
599
600 intelCmdCopyImage(cmdBuffer, srcImage, destImage, 1, &region);
601 }
602}
603
604XGL_VOID XGLAPI intelCmdUpdateMemory(
605 XGL_CMD_BUFFER cmdBuffer,
606 XGL_GPU_MEMORY destMem,
607 XGL_GPU_SIZE destOffset,
608 XGL_GPU_SIZE dataSize,
609 const XGL_UINT32* pData)
610{
611 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
612 struct intel_mem *dst = intel_mem(destMem);
613 struct intel_cmd_meta meta;
614 XGL_FORMAT format;
615 XGL_SIZE format_size;
616 uint32_t *ptr;
617 uint32_t offset;
618
619 /* write to dynamic state writer first */
620 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
621 (dataSize + 3) / 4, &ptr);
622 memcpy(ptr, pData, dataSize);
623
624 format.channelFormat = cmd_meta_mem_channel_format(cmd,
625 offset, destOffset, dataSize, &format_size);
626 format.numericFormat = XGL_NUM_FMT_UINT;
627
628 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800629 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800630
631 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM;
632
633 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
634 offset + dataSize, format, &meta);
635 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
636
637 meta.src.x = offset / format_size;
638 meta.dst.x = destOffset / format_size;
639 meta.width = dataSize / format_size;
640 meta.height = 1;
641 meta.samples = 1;
642
643 cmd_draw_meta(cmd, &meta);
644}
645
646XGL_VOID XGLAPI intelCmdFillMemory(
647 XGL_CMD_BUFFER cmdBuffer,
648 XGL_GPU_MEMORY destMem,
649 XGL_GPU_SIZE destOffset,
650 XGL_GPU_SIZE fillSize,
651 XGL_UINT32 data)
652{
653 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
654 struct intel_mem *dst = intel_mem(destMem);
655 struct intel_cmd_meta meta;
656 XGL_FORMAT format;
657 XGL_SIZE format_size;
658
659 /* must be 4-byte aligned */
660 if ((destOffset | fillSize) & 3) {
661 cmd->result = XGL_ERROR_UNKNOWN;
662 return;
663 }
664
665 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800666 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800667
668 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
669
670 meta.clear_val[0] = data;
671 meta.clear_val[1] = data;
672 meta.clear_val[2] = data;
673 meta.clear_val[3] = data;
674
675 format.channelFormat = cmd_meta_mem_channel_format(cmd,
676 0, destOffset, fillSize, &format_size);;
677 format.numericFormat = XGL_NUM_FMT_UINT;
678 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
679
680 meta.dst.x = destOffset / format_size;
681 meta.width = fillSize / format_size;
682 meta.height = 1;
683 meta.samples = 1;
684
685 cmd_draw_meta(cmd, &meta);
686}
687
688static void cmd_meta_clear_image(struct intel_cmd *cmd,
689 struct intel_img *img,
690 XGL_FORMAT format,
691 struct intel_cmd_meta *meta,
692 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
693{
694 XGL_UINT mip_levels, array_size;
695 XGL_UINT i, j;
696
697 if (range->baseMipLevel >= img->mip_levels ||
698 range->baseArraySlice >= img->array_size)
699 return;
700
701 mip_levels = img->mip_levels - range->baseMipLevel;
702 if (mip_levels > range->mipLevels)
703 mip_levels = range->mipLevels;
704
705 array_size = img->array_size - range->baseArraySlice;
706 if (array_size > range->arraySize)
707 array_size = range->arraySize;
708
Chia-I Wuc14d1562014-10-17 09:49:22 +0800709 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800710 meta->dst.lod = range->baseMipLevel + i;
711 meta->dst.layer = range->baseArraySlice;
712
Chia-I Wuc14d1562014-10-17 09:49:22 +0800713 meta->width = u_minify(img->layout.width0, meta->dst.lod);
714 meta->height = u_minify(img->layout.height0, meta->dst.lod);
715
716 for (j = 0; j < array_size; j++) {
717 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
718 cmd_meta_set_dst_for_img(cmd, img, format,
719 meta->dst.lod, meta->dst.layer, meta);
720
721 cmd_draw_meta(cmd, meta);
722 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800723 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800724 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800725 cmd_meta_set_ds_state(cmd, range->aspect,
726 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800727
728 cmd_draw_meta(cmd, meta);
729
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800730 intel_ds_view_destroy(meta->ds.view);
731 intel_ds_state_destroy(meta->ds.state);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800732 }
733
734 meta->dst.layer++;
735 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800736 }
737}
738
739XGL_VOID XGLAPI intelCmdClearColorImage(
740 XGL_CMD_BUFFER cmdBuffer,
741 XGL_IMAGE image,
742 const XGL_FLOAT color[4],
743 XGL_UINT rangeCount,
744 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
745{
746 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
747 struct intel_img *img = intel_img(image);
748 struct intel_cmd_meta meta;
749 XGL_UINT i;
750
751 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800752 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800753
754 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
755 meta.samples = img->samples;
756
757 meta.clear_val[0] = u_fui(color[0]);
758 meta.clear_val[1] = u_fui(color[1]);
759 meta.clear_val[2] = u_fui(color[2]);
760 meta.clear_val[3] = u_fui(color[3]);
761
762 for (i = 0; i < rangeCount; i++) {
763 cmd_meta_clear_image(cmd, img, img->layout.format,
764 &meta, &pRanges[i]);
765 }
766}
767
768XGL_VOID XGLAPI intelCmdClearColorImageRaw(
769 XGL_CMD_BUFFER cmdBuffer,
770 XGL_IMAGE image,
771 const XGL_UINT32 color[4],
772 XGL_UINT rangeCount,
773 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
774{
775 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
776 struct intel_img *img = intel_img(image);
777 struct intel_cmd_meta meta;
778 XGL_FORMAT format;
779 XGL_UINT i;
780
781 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800782 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800783
784 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
785 meta.samples = img->samples;
786
787 meta.clear_val[0] = color[0];
788 meta.clear_val[1] = color[1];
789 meta.clear_val[2] = color[2];
790 meta.clear_val[3] = color[3];
791
792 format = cmd_meta_img_raw_format(cmd, img->layout.format);
793
794 for (i = 0; i < rangeCount; i++)
795 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
796}
797
798XGL_VOID XGLAPI intelCmdClearDepthStencil(
799 XGL_CMD_BUFFER cmdBuffer,
800 XGL_IMAGE image,
801 XGL_FLOAT depth,
802 XGL_UINT32 stencil,
803 XGL_UINT rangeCount,
804 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
805{
806 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
807 struct intel_img *img = intel_img(image);
808 struct intel_cmd_meta meta;
809 XGL_UINT i;
810
811 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800812 meta.mode = INTEL_CMD_META_DEPTH_STENCIL_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800813
814 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
815 meta.samples = img->samples;
816
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800817 meta.clear_val[0] = u_fui(depth);
818 meta.clear_val[1] = stencil;
819
Chia-I Wuc14d1562014-10-17 09:49:22 +0800820 for (i = 0; i < rangeCount; i++) {
821 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
822
Chia-I Wuc14d1562014-10-17 09:49:22 +0800823 cmd_meta_clear_image(cmd, img, img->layout.format,
824 &meta, range);
825 }
826}
827
828XGL_VOID XGLAPI intelCmdResolveImage(
829 XGL_CMD_BUFFER cmdBuffer,
830 XGL_IMAGE srcImage,
831 XGL_IMAGE destImage,
832 XGL_UINT rectCount,
833 const XGL_IMAGE_RESOLVE* pRects)
834{
835 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
836 struct intel_img *src = intel_img(srcImage);
837 struct intel_img *dst = intel_img(destImage);
838 struct intel_cmd_meta meta;
839 XGL_FORMAT format;
840 XGL_UINT i;
841
842 if (src->samples <= 1 || dst->samples > 1 ||
843 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
844 cmd->result = XGL_ERROR_UNKNOWN;
845 return;
846 }
847
848 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800849 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800850
851 switch (src->samples) {
852 case 2:
853 default:
854 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
855 break;
856 case 4:
857 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
858 break;
859 case 8:
860 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
861 break;
862 case 16:
863 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
864 break;
865 }
866
867 meta.samples = 1;
868
869 format = cmd_meta_img_raw_format(cmd, src->layout.format);
870 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
871
872 for (i = 0; i < rectCount; i++) {
873 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
874
875 meta.src.lod = rect->srcSubresource.mipLevel;
876 meta.src.layer = rect->srcSubresource.arraySlice;
877 meta.src.x = rect->srcOffset.x;
878 meta.src.y = rect->srcOffset.y;
879
880 meta.dst.lod = rect->destSubresource.mipLevel;
881 meta.dst.layer = rect->destSubresource.arraySlice;
882 meta.dst.x = rect->destOffset.x;
883 meta.dst.y = rect->destOffset.y;
884
885 meta.width = rect->extent.width;
886 meta.height = rect->extent.height;
887
888 cmd_meta_set_dst_for_img(cmd, dst, format,
889 meta.dst.lod, meta.dst.layer, &meta);
890
891 cmd_draw_meta(cmd, &meta);
892 }
893}