blob: 53f8ba4d2cdf465a635e0d374ecdc12e565596e0 [file] [log] [blame]
Colin Cross07a58322022-02-08 19:45:27 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __NDCTL_H__
20#define __NDCTL_H__
21#include <linux/types.h>
22struct nd_cmd_dimm_flags {
23 __u32 status;
24 __u32 flags;
25} __packed;
26struct nd_cmd_get_config_size {
27 __u32 status;
28 __u32 config_size;
29 __u32 max_xfer;
30} __packed;
31struct nd_cmd_get_config_data_hdr {
32 __u32 in_offset;
33 __u32 in_length;
34 __u32 status;
35 __u8 out_buf[0];
36} __packed;
37struct nd_cmd_set_config_hdr {
38 __u32 in_offset;
39 __u32 in_length;
40 __u8 in_buf[0];
41} __packed;
42struct nd_cmd_vendor_hdr {
43 __u32 opcode;
44 __u32 in_length;
45 __u8 in_buf[0];
46} __packed;
47struct nd_cmd_vendor_tail {
48 __u32 status;
49 __u32 out_length;
50 __u8 out_buf[0];
51} __packed;
52struct nd_cmd_ars_cap {
53 __u64 address;
54 __u64 length;
55 __u32 status;
56 __u32 max_ars_out;
57 __u32 clear_err_unit;
58 __u16 flags;
59 __u16 reserved;
60} __packed;
61struct nd_cmd_ars_start {
62 __u64 address;
63 __u64 length;
64 __u16 type;
65 __u8 flags;
66 __u8 reserved[5];
67 __u32 status;
68 __u32 scrub_time;
69} __packed;
70struct nd_cmd_ars_status {
71 __u32 status;
72 __u32 out_length;
73 __u64 address;
74 __u64 length;
75 __u64 restart_address;
76 __u64 restart_length;
77 __u16 type;
78 __u16 flags;
79 __u32 num_records;
80 struct nd_ars_record {
81 __u32 handle;
82 __u32 reserved;
83 __u64 err_address;
84 __u64 length;
85 } __packed records[0];
86} __packed;
87struct nd_cmd_clear_error {
88 __u64 address;
89 __u64 length;
90 __u32 status;
91 __u8 reserved[4];
92 __u64 cleared;
93} __packed;
94enum {
95 ND_CMD_IMPLEMENTED = 0,
96 ND_CMD_ARS_CAP = 1,
97 ND_CMD_ARS_START = 2,
98 ND_CMD_ARS_STATUS = 3,
99 ND_CMD_CLEAR_ERROR = 4,
100 ND_CMD_SMART = 1,
101 ND_CMD_SMART_THRESHOLD = 2,
102 ND_CMD_DIMM_FLAGS = 3,
103 ND_CMD_GET_CONFIG_SIZE = 4,
104 ND_CMD_GET_CONFIG_DATA = 5,
105 ND_CMD_SET_CONFIG_DATA = 6,
106 ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
107 ND_CMD_VENDOR_EFFECT_LOG = 8,
108 ND_CMD_VENDOR = 9,
109 ND_CMD_CALL = 10,
110};
111enum {
112 ND_ARS_VOLATILE = 1,
113 ND_ARS_PERSISTENT = 2,
114 ND_ARS_RETURN_PREV_DATA = 1 << 1,
115 ND_CONFIG_LOCKED = 1,
116};
117#define ND_IOCTL 'N'
118#define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS, struct nd_cmd_dimm_flags)
119#define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE, struct nd_cmd_get_config_size)
120#define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA, struct nd_cmd_get_config_data_hdr)
121#define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA, struct nd_cmd_set_config_hdr)
122#define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR, struct nd_cmd_vendor_hdr)
123#define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP, struct nd_cmd_ars_cap)
124#define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START, struct nd_cmd_ars_start)
125#define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS, struct nd_cmd_ars_status)
126#define ND_IOCTL_CLEAR_ERROR _IOWR(ND_IOCTL, ND_CMD_CLEAR_ERROR, struct nd_cmd_clear_error)
127#define ND_DEVICE_DIMM 1
128#define ND_DEVICE_REGION_PMEM 2
129#define ND_DEVICE_REGION_BLK 3
130#define ND_DEVICE_NAMESPACE_IO 4
131#define ND_DEVICE_NAMESPACE_PMEM 5
132#define ND_DEVICE_NAMESPACE_BLK 6
133#define ND_DEVICE_DAX_PMEM 7
134enum nd_driver_flags {
135 ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM,
136 ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM,
137 ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK,
138 ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO,
139 ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM,
140 ND_DRIVER_NAMESPACE_BLK = 1 << ND_DEVICE_NAMESPACE_BLK,
141 ND_DRIVER_DAX_PMEM = 1 << ND_DEVICE_DAX_PMEM,
142};
143enum ars_masks {
144 ARS_STATUS_MASK = 0x0000FFFF,
145 ARS_EXT_STATUS_SHIFT = 16,
146};
147struct nd_cmd_pkg {
148 __u64 nd_family;
149 __u64 nd_command;
150 __u32 nd_size_in;
151 __u32 nd_size_out;
152 __u32 nd_reserved2[9];
153 __u32 nd_fw_size;
154 unsigned char nd_payload[];
155};
156#define NVDIMM_FAMILY_INTEL 0
157#define NVDIMM_FAMILY_HPE1 1
158#define NVDIMM_FAMILY_HPE2 2
159#define NVDIMM_FAMILY_MSFT 3
160#define NVDIMM_FAMILY_HYPERV 4
161#define NVDIMM_FAMILY_PAPR 5
162#define NVDIMM_FAMILY_MAX NVDIMM_FAMILY_PAPR
163#define NVDIMM_BUS_FAMILY_NFIT 0
164#define NVDIMM_BUS_FAMILY_INTEL 1
165#define NVDIMM_BUS_FAMILY_MAX NVDIMM_BUS_FAMILY_INTEL
166#define ND_IOCTL_CALL _IOWR(ND_IOCTL, ND_CMD_CALL, struct nd_cmd_pkg)
167#endif