Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 1 | //===----------------------------------------------------------------------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | |
| 9 | #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ |
| 10 | #define _HEXAGON_CIRC_BREV_INTRINSICS_H_ 1 |
| 11 | |
| 12 | #include <hexagon_protos.h> |
| 13 | #include <stdint.h> |
| 14 | |
| 15 | /* Circular Load */ |
| 16 | /* ========================================================================== |
| 17 | Assembly Syntax: Return=instruction() |
| 18 | C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 19 | Instruction Type: InstructionType |
| 20 | Execution Slots: SLOT0123 |
| 21 | ========================================================================== */ |
| 22 | #define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K) \ |
| 23 | { ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } |
| 24 | |
| 25 | /* ========================================================================== |
| 26 | Assembly Syntax: Return=instruction() |
| 27 | C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 28 | Instruction Type: InstructionType |
| 29 | Execution Slots: SLOT0123 |
| 30 | ========================================================================== */ |
| 31 | #define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K) \ |
| 32 | { ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } |
| 33 | |
| 34 | /* ========================================================================== |
| 35 | Assembly Syntax: Return=instruction() |
| 36 | C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 37 | Instruction Type: InstructionType |
| 38 | Execution Slots: SLOT0123 |
| 39 | ========================================================================== */ |
| 40 | #define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K) \ |
| 41 | { ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
| 42 | |
| 43 | /* ========================================================================== |
| 44 | Assembly Syntax: Return=instruction() |
| 45 | C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst, UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 46 | Instruction Type: InstructionType |
| 47 | Execution Slots: SLOT0123 |
| 48 | ========================================================================== */ |
| 49 | #define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \ |
| 50 | { ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
| 51 | |
| 52 | /* ========================================================================== |
| 53 | Assembly Syntax: Return=instruction() |
| 54 | C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 55 | Instruction Type: InstructionType |
| 56 | Execution Slots: SLOT0123 |
| 57 | ========================================================================== */ |
| 58 | #define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K) \ |
| 59 | { ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } |
| 60 | |
| 61 | /* ========================================================================== |
| 62 | Assembly Syntax: Return=instruction() |
| 63 | C Intrinsic Prototype: void Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 64 | Instruction Type: InstructionType |
| 65 | Execution Slots: SLOT0123 |
| 66 | ========================================================================== */ |
| 67 | #define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \ |
| 68 | { ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } |
| 69 | |
| 70 | /* Circular Store */ |
| 71 | /* ========================================================================== |
| 72 | Assembly Syntax: Return=instruction() |
| 73 | C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 74 | Instruction Type: InstructionType |
| 75 | Execution Slots: SLOT0123 |
| 76 | ========================================================================== */ |
| 77 | #define Q6_circ_store_update_D(src,ptr,incr,bufsize,K) \ |
| 78 | { ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } |
| 79 | |
| 80 | /* ========================================================================== |
| 81 | Assembly Syntax: Return=instruction() |
| 82 | C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 83 | Instruction Type: InstructionType |
| 84 | Execution Slots: SLOT0123 |
| 85 | ========================================================================== */ |
| 86 | #define Q6_circ_store_update_W(src,ptr,incr,bufsize,K) \ |
| 87 | { ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } |
| 88 | |
| 89 | /* ========================================================================== |
| 90 | Assembly Syntax: Return=instruction() |
| 91 | C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 92 | Instruction Type: InstructionType |
| 93 | Execution Slots: SLOT0123 |
| 94 | ========================================================================== */ |
| 95 | #define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \ |
| 96 | { ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
| 97 | |
| 98 | /* ========================================================================== |
| 99 | Assembly Syntax: Return=instruction() |
| 100 | C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) |
| 101 | Instruction Type: InstructionType |
| 102 | Execution Slots: SLOT0123 |
| 103 | ========================================================================== */ |
| 104 | #define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \ |
| 105 | { ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } |
| 106 | |
| 107 | /* ========================================================================== |
| 108 | Assembly Syntax: Return=instruction() |
| 109 | C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize, UWord64 K) |
| 110 | Instruction Type: InstructionType |
| 111 | Execution Slots: SLOT0123 |
| 112 | ========================================================================== */ |
| 113 | #define Q6_circ_store_update_B(src,ptr,incr,bufsize,K) \ |
| 114 | { ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); } |
| 115 | |
| 116 | |
| 117 | /* Bit Reverse Load */ |
| 118 | /* ========================================================================== |
| 119 | Assembly Syntax: Return=instruction() |
| 120 | C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4) |
| 121 | Instruction Type: InstructionType |
| 122 | Execution Slots: SLOT0123 |
| 123 | ========================================================================== */ |
| 124 | #define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \ |
| 125 | { ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); } |
| 126 | |
| 127 | /* ========================================================================== |
| 128 | Assembly Syntax: Return=instruction() |
| 129 | C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4) |
| 130 | Instruction Type: InstructionType |
| 131 | Execution Slots: SLOT0123 |
| 132 | ========================================================================== */ |
| 133 | #define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \ |
| 134 | { ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); } |
| 135 | |
| 136 | /* ========================================================================== |
| 137 | Assembly Syntax: Return=instruction() |
| 138 | C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4) |
| 139 | Instruction Type: InstructionType |
| 140 | Execution Slots: SLOT0123 |
| 141 | ========================================================================== */ |
| 142 | #define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \ |
| 143 | { ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } |
| 144 | |
| 145 | /* ========================================================================== |
| 146 | Assembly Syntax: Return=instruction() |
| 147 | C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst, UWord16 *ptr, UWord32 Iu4) |
| 148 | Instruction Type: InstructionType |
| 149 | Execution Slots: SLOT0123 |
| 150 | ========================================================================== */ |
| 151 | #define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \ |
| 152 | { ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } |
| 153 | |
| 154 | /* ========================================================================== |
| 155 | Assembly Syntax: Return=instruction() |
| 156 | C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4) |
| 157 | Instruction Type: InstructionType |
| 158 | Execution Slots: SLOT0123 |
| 159 | ========================================================================== */ |
| 160 | #define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \ |
| 161 | { ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); } |
| 162 | |
| 163 | /* ========================================================================== |
| 164 | Assembly Syntax: Return=instruction() |
| 165 | C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4) |
| 166 | Instruction Type: InstructionType |
| 167 | Execution Slots: SLOT0123 |
| 168 | ========================================================================== */ |
| 169 | #define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \ |
| 170 | { ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); } |
| 171 | |
| 172 | /* Bit Reverse Store */ |
| 173 | |
| 174 | /* ========================================================================== |
| 175 | Assembly Syntax: Return=instruction() |
| 176 | C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4) |
| 177 | Instruction Type: InstructionType |
| 178 | Execution Slots: SLOT0123 |
| 179 | ========================================================================== */ |
| 180 | #define Q6_bitrev_store_update_D(src,ptr,log2bufsize) \ |
| 181 | { ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); } |
| 182 | |
| 183 | /* ========================================================================== |
| 184 | Assembly Syntax: Return=instruction() |
| 185 | C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4) |
| 186 | Instruction Type: InstructionType |
| 187 | Execution Slots: SLOT0123 |
| 188 | ========================================================================== */ |
| 189 | #define Q6_bitrev_store_update_W(src,ptr,log2bufsize) \ |
| 190 | { ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); } |
| 191 | |
| 192 | /* ========================================================================== |
| 193 | Assembly Syntax: Return=instruction() |
| 194 | C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4) |
| 195 | Instruction Type: InstructionType |
| 196 | Execution Slots: SLOT0123 |
| 197 | ========================================================================== */ |
| 198 | #define Q6_bitrev_store_update_HL(src,ptr,log2bufsize) \ |
| 199 | { ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); } |
| 200 | |
| 201 | /* ========================================================================== |
| 202 | Assembly Syntax: Return=instruction() |
| 203 | C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4) |
| 204 | Instruction Type: InstructionType |
| 205 | Execution Slots: SLOT0123 |
| 206 | ========================================================================== */ |
| 207 | #define Q6_bitrev_store_update_HH(src,ptr,log2bufsize) \ |
| 208 | { ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); } |
| 209 | |
| 210 | /* ========================================================================== |
| 211 | Assembly Syntax: Return=instruction() |
| 212 | C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4) |
| 213 | Instruction Type: InstructionType |
| 214 | Execution Slots: SLOT0123 |
| 215 | ========================================================================== */ |
| 216 | #define Q6_bitrev_store_update_B(src,ptr,log2bufsize) \ |
| 217 | { ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); } |
| 218 | |
| 219 | |
| 220 | #define HEXAGON_circ_ldd __builtin_circ_ldd |
| 221 | #define HEXAGON_circ_ldw __builtin_circ_ldw |
| 222 | #define HEXAGON_circ_ldh __builtin_circ_ldh |
| 223 | #define HEXAGON_circ_lduh __builtin_circ_lduh |
| 224 | #define HEXAGON_circ_ldb __builtin_circ_ldb |
| 225 | #define HEXAGON_circ_ldub __builtin_circ_ldub |
| 226 | |
| 227 | |
| 228 | #define HEXAGON_circ_std __builtin_circ_std |
| 229 | #define HEXAGON_circ_stw __builtin_circ_stw |
| 230 | #define HEXAGON_circ_sth __builtin_circ_sth |
| 231 | #define HEXAGON_circ_sthhi __builtin_circ_sthhi |
| 232 | #define HEXAGON_circ_stb __builtin_circ_stb |
| 233 | |
| 234 | |
| 235 | #define HEXAGON_brev_ldd __builtin_brev_ldd |
| 236 | #define HEXAGON_brev_ldw __builtin_brev_ldw |
| 237 | #define HEXAGON_brev_ldh __builtin_brev_ldh |
| 238 | #define HEXAGON_brev_lduh __builtin_brev_lduh |
| 239 | #define HEXAGON_brev_ldb __builtin_brev_ldb |
| 240 | #define HEXAGON_brev_ldub __builtin_brev_ldub |
| 241 | |
| 242 | #define HEXAGON_brev_std __builtin_brev_std |
| 243 | #define HEXAGON_brev_stw __builtin_brev_stw |
| 244 | #define HEXAGON_brev_sth __builtin_brev_sth |
| 245 | #define HEXAGON_brev_sthhi __builtin_brev_sthhi |
| 246 | #define HEXAGON_brev_stb __builtin_brev_stb |
| 247 | |
| 248 | #ifdef __HVX__ |
| 249 | /* ========================================================================== |
| 250 | Assembly Syntax: if (Qt) vmem(Rt+#0) = Vs |
| 251 | C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
| 252 | Instruction Type: COPROC_VMEM |
| 253 | Execution Slots: SLOT0 |
| 254 | ========================================================================== */ |
| 255 | |
| 256 | #define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq) |
| 257 | |
| 258 | /* ========================================================================== |
| 259 | Assembly Syntax: if (!Qt) vmem(Rt+#0) = Vs |
| 260 | C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
| 261 | Instruction Type: COPROC_VMEM |
| 262 | Execution Slots: SLOT0 |
| 263 | ========================================================================== */ |
| 264 | |
| 265 | #define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq) |
| 266 | |
| 267 | /* ========================================================================== |
| 268 | Assembly Syntax: if (Qt) vmem(Rt+#0):nt = Vs |
| 269 | C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
| 270 | Instruction Type: COPROC_VMEM |
| 271 | Execution Slots: SLOT0 |
| 272 | ========================================================================== */ |
| 273 | |
| 274 | #define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq) |
| 275 | |
| 276 | /* ========================================================================== |
| 277 | Assembly Syntax: if (!Qt) vmem(Rt+#0):nt = Vs |
| 278 | C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) |
| 279 | Instruction Type: COPROC_VMEM |
| 280 | Execution Slots: SLOT0 |
| 281 | ========================================================================== */ |
| 282 | |
| 283 | #define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq) |
| 284 | |
| 285 | #endif |
| 286 | |
| 287 | |
| 288 | #endif /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */ |
| 289 | |
| 290 | #ifdef __NOT_DEFINED__ |
| 291 | /*** comment block template ***/ |
| 292 | /* ========================================================================== |
| 293 | Assembly Syntax: Return=instruction() |
| 294 | C Intrinsic Prototype: ReturnType Intrinsic(ParamType Rs, ParamType Rt) |
| 295 | Instruction Type: InstructionType |
| 296 | Execution Slots: SLOT0123 |
| 297 | ========================================================================== */ |
| 298 | #endif /*** __NOT_DEFINED__ ***/ |