commit 096041174b1d8cc09b06c51053b2b7e8545bd93f
author Duane Sand <duanes@mips.com> Thu May 24 17:40:21 2012 -0700
committer Duane Sand <duanes@mips.com> Tue May 29 16:18:42 2012 -0700
tree 2b977eddbaf2a93d5a35f851efaa965fe57d2a57
parent d98c87c95342ed6eade9f1239122dc9e90dcad67

Add Mips architecture to system/core/include

Change-Id: Ief7bdbd8d09cabe3f11f3ed47a932a7faa81cad9

include/private/pixelflinger/ggl_context.h

diff --git a/include/private/pixelflinger/ggl_context.h b/include/private/pixelflinger/ggl_context.h
index 2d7fdcf..4864d5a 100644
--- a/include/private/pixelflinger/ggl_context.h
+++ b/include/private/pixelflinger/ggl_context.h
@@ -42,10 +42,30 @@
 #else
 
 inline uint32_t GGL_RGBA_TO_HOST(uint32_t v) {
+#if defined(__mips__) && __mips==32 && __mips_isa_rev>=2
+    uint32_t r;
+    __asm__("wsbh %0, %1;"
+        "rotr %0, %0, 16"
+        : "=r" (r)
+        : "r" (v)
+        );
+    return r;
+#else
     return (v<<24) | (v>>24) | ((v<<8)&0xff0000) | ((v>>8)&0xff00);
+#endif
 }
 inline uint32_t GGL_HOST_TO_RGBA(uint32_t v) {
+#if defined(__mips__) && __mips==32 && __mips_isa_rev>=2
+    uint32_t r;
+    __asm__("wsbh %0, %1;"
+        "rotr %0, %0, 16"
+        : "=r" (r)
+        : "r" (v)
+        );
+    return r;
+#else
     return (v<<24) | (v>>24) | ((v<<8)&0xff0000) | ((v>>8)&0xff00);
+#endif
 }
 
 #endif