| commit | 51546ee32c22426aa85f2ee7cc2e8df7d774e385 | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Thu May 24 16:54:49 2012 -0700 |
| committer | Andrew Boie <andrew.p.boie@intel.com> | Tue Sep 24 12:53:18 2013 -0700 |
| tree | f2ad68e05da0730958508cd19ebdf90620d48384 | |
| parent | 3c8bdef029cbaa8d8fa18e4e55e51b60e938dd6e [diff] |
Use SSE2 enhanced memset for capable x86 processors Originally, if TARGET_ARCH_VARIANT is x86-atom, the SSE2 enhanced memset is used. This patch extends this to all x86 processors which support SSE2 (i.e. ARCH_X86_HAVE_SSE2 is true). Indentation added to the ifeq cases to make this easier to read. Change-Id: I05f49e237a95359d3f2e3216b037e3fc1a0fbcb0 Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>