asoc: bolero: enable swr DMIC clk_div after tx mclk is enabled
If swr DMIC clk_div is enabled before enabling tx mclk and LPASS
power collapse happens, volatile swr DMIC clk_div registers would
be cleared and swr DMIC would not work. Make this change to enable
swr DMIC clk_div after tx mclk is enabled
Change-Id: Ie9e7e8c74dc0e013898f3fd8b62344a670ad6664
Signed-off-by: Meng Wang <mengw@codeaurora.org>
diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c
index a27c3e1..a9efa30 100644
--- a/asoc/codecs/bolero/tx-macro.c
+++ b/asoc/codecs/bolero/tx-macro.c
@@ -835,6 +835,8 @@
int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
struct device *tx_dev = NULL;
struct tx_macro_priv *tx_priv = NULL;
+ u16 adc_mux_reg = 0, adc_reg = 0, adc_n = 0;
+ u16 dmic_clk_reg = 0;
if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__))
return -EINVAL;
@@ -855,6 +857,22 @@
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ adc_mux_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
+ TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
+ if (snd_soc_component_read32(component, adc_mux_reg) & SWR_MIC) {
+ adc_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
+ TX_MACRO_ADC_MUX_CFG_OFFSET * decimator;
+ adc_n = snd_soc_component_read32(component, adc_reg) &
+ TX_MACRO_SWR_MIC_MUX_SEL_MASK;
+ if (adc_n >= BOLERO_ADC_MAX) {
+ dmic_clk_reg =
+ BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL +
+ ((adc_n - 5) / 2) * 4;
+ snd_soc_component_update_bits(component,
+ dmic_clk_reg,
+ 0x0E, tx_priv->dmic_clk_div << 0x1);
+ }
+ }
snd_soc_component_update_bits(component,
dec_cfg_reg, 0x06, tx_priv->dec_mode[decimator] <<
TX_MACRO_ADC_MODE_CFG0_SHIFT);