Merge "asoc: codecs: Do not update VA clk muxsel register"
diff --git a/asoc/codecs/bolero/bolero-clk-rsc.c b/asoc/codecs/bolero/bolero-clk-rsc.c
index 2921624..7e28c5b 100644
--- a/asoc/codecs/bolero/bolero-clk-rsc.c
+++ b/asoc/codecs/bolero/bolero-clk-rsc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/of_platform.h>
@@ -250,10 +250,13 @@
if (enable) {
if (priv->clk_cnt[clk_id] == 0) {
- ret = bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
+ if (clk_id != VA_CORE_CLK) {
+ ret = bolero_clk_rsc_mux0_clk_request(priv,
+ default_clk_id,
true);
- if (ret < 0)
- goto done;
+ if (ret < 0)
+ goto done;
+ }
ret = clk_prepare_enable(priv->clk[clk_id]);
if (ret < 0) {
@@ -271,12 +274,22 @@
goto err_npl_clk;
}
}
- iowrite32(0x1, clk_muxsel);
- muxsel = ioread32(clk_muxsel);
- trace_printk("%s: muxsel value after enable: %d\n",
- __func__, muxsel);
- bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
+
+ /*
+ * Temp SW workaround to address a glitch issue of
+ * VA GFMux instance responsible for switching from
+ * TX MCLK to VA MCLK. This configuration would be taken
+ * care in DSP itself
+ */
+ if (clk_id != VA_CORE_CLK) {
+ iowrite32(0x1, clk_muxsel);
+ muxsel = ioread32(clk_muxsel);
+ trace_printk("%s: muxsel value after enable: %d\n",
+ __func__, muxsel);
+ bolero_clk_rsc_mux0_clk_request(priv,
+ default_clk_id,
false);
+ }
}
priv->clk_cnt[clk_id]++;
} else {
@@ -288,23 +301,34 @@
}
priv->clk_cnt[clk_id]--;
if (priv->clk_cnt[clk_id] == 0) {
- ret = bolero_clk_rsc_mux0_clk_request(priv,
+ if (clk_id != VA_CORE_CLK) {
+ ret = bolero_clk_rsc_mux0_clk_request(priv,
default_clk_id, true);
- if (!ret)
- iowrite32(0x0, clk_muxsel);
-
- muxsel = ioread32(clk_muxsel);
- trace_printk("%s: muxsel value after disable: %d\n",
- __func__, muxsel);
+ if (!ret) {
+ /*
+ * Temp SW workaround to address a glitch issue
+ * of VA GFMux instance responsible for
+ * switching from TX MCLK to VA MCLK.
+ * This configuration would be taken
+ * care in DSP itself.
+ */
+ iowrite32(0x0, clk_muxsel);
+ muxsel = ioread32(clk_muxsel);
+ trace_printk("%s: muxsel value after disable: %d\n",
+ __func__, muxsel);
+ }
+ }
if (priv->clk[clk_id + NPL_CLK_OFFSET])
clk_disable_unprepare(
priv->clk[clk_id + NPL_CLK_OFFSET]);
clk_disable_unprepare(priv->clk[clk_id]);
- if (!ret)
- bolero_clk_rsc_mux0_clk_request(priv,
+ if (clk_id != VA_CORE_CLK) {
+ if (!ret)
+ bolero_clk_rsc_mux0_clk_request(priv,
default_clk_id, false);
+ }
}
}
return ret;
@@ -313,7 +337,8 @@
clk_disable_unprepare(priv->clk[clk_id]);
err_clk:
- bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
+ if (clk_id != VA_CORE_CLK)
+ bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
done:
return ret;
}