| commit | 5e8453b03efadb73392730872c4a79b244fe6ffd | [log] [tgz] |
|---|---|---|
| author | Xiaojun Sang <xsang@codeaurora.org> | Fri Jun 15 17:03:42 2018 +0800 |
| committer | Xiaojun Sang <xsang@codeaurora.org> | Fri Jun 22 16:26:12 2018 +0800 |
| tree | 0fcb187b8f72bf403f03edd4cded25c9e066b4fb | |
| parent | b40af4675ef287f49c61152506cbfe56c0ef3b62 [diff] |
ipc: Implement FIFO queue to fix sequence inconsistency The SVA history buffer is out of order if there are more than 2 continuous RX buffer done from GLINK. Implement FIFO to ensure sequence consistency. Change-Id: If70e2d0160e8f3140d621298b0db03bd89ba88ba Signed-off-by: Xiaojun Sang <xsang@codeaurora.org>