Merge "ASoC: wcd938x: Add support for ADC modes"
diff --git a/asoc/codecs/wcd938x/internal.h b/asoc/codecs/wcd938x/internal.h
index 46d61a0..c59d5b8 100644
--- a/asoc/codecs/wcd938x/internal.h
+++ b/asoc/codecs/wcd938x/internal.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD938X_INTERNAL_H
@@ -70,6 +70,7 @@
bool comp1_enable;
bool comp2_enable;
bool ldoh;
+ bool bcs_dis;
struct irq_domain *virq;
struct wcd_irq_info irq_info;
u32 rx_clk_cnt;
diff --git a/asoc/codecs/wcd938x/wcd938x.c b/asoc/codecs/wcd938x/wcd938x.c
index 60ef2bf..191db8d 100644
--- a/asoc/codecs/wcd938x/wcd938x.c
+++ b/asoc/codecs/wcd938x/wcd938x.c
@@ -69,6 +69,16 @@
ADC_MODE_ULP2,
};
+static u8 tx_mode_bit[] = {
+ [ADC_MODE_INVALID] = 0x00,
+ [ADC_MODE_HIFI] = 0x01,
+ [ADC_MODE_LO_HIF] = 0x02,
+ [ADC_MODE_NORMAL] = 0x04,
+ [ADC_MODE_LP] = 0x08,
+ [ADC_MODE_ULP1] = 0x10,
+ [ADC_MODE_ULP2] = 0x20,
+};
+
static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
@@ -141,26 +151,56 @@
return ((bank & 0x40) ? 1: 0);
}
-static int wcd938x_swr_slv_set_host_clk_div2(struct swr_device *dev,
- u8 devnum, int bank)
+static int wcd938x_get_clk_rate(int mode)
{
- u8 val = (bank ? 1 : 0);
+ int rate;
- return (swr_write(dev, devnum,
- (SWR_SCP_HOST_CLK_DIV2_CTL_BANK + (0x10 * bank)), &val));
+ switch (mode) {
+ case ADC_MODE_ULP2:
+ rate = SWR_CLK_RATE_0P6MHZ;
+ break;
+ case ADC_MODE_ULP1:
+ rate = SWR_CLK_RATE_1P2MHZ;
+ break;
+ case ADC_MODE_LP:
+ rate = SWR_CLK_RATE_4P8MHZ;
+ break;
+ case ADC_MODE_NORMAL:
+ case ADC_MODE_LO_HIF:
+ case ADC_MODE_HIFI:
+ case ADC_MODE_INVALID:
+ default:
+ rate = SWR_CLK_RATE_9P6MHZ;
+ break;
+ }
+
+ return rate;
}
static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
- int mode, int bank)
+ int rate, int bank)
{
u8 mask = (bank ? 0xF0 : 0x0F);
u8 val = 0;
- if ((mode == ADC_MODE_ULP1) || (mode == ADC_MODE_ULP2))
+ switch (rate) {
+ case SWR_CLK_RATE_0P6MHZ:
val = (bank ? 0x60 : 0x06);
- else
+ break;
+ case SWR_CLK_RATE_1P2MHZ:
+ val = (bank ? 0x50 : 0x05);
+ break;
+ case SWR_CLK_RATE_2P4MHZ:
+ val = (bank ? 0x30 : 0x03);
+ break;
+ case SWR_CLK_RATE_4P8MHZ:
+ val = (bank ? 0x10 : 0x01);
+ break;
+ case SWR_CLK_RATE_9P6MHZ:
+ default:
val = 0x00;
-
+ break;
+ }
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_SWR_TX_CLK_RATE,
mask, val);
@@ -354,7 +394,8 @@
}
static int wcd938x_tx_connect_port(struct snd_soc_component *component,
- u8 slv_port_type, u8 enable)
+ u8 slv_port_type, int clk_rate,
+ u8 enable)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
u8 port_id, num_ch, ch_mask, port_type;
@@ -365,6 +406,8 @@
ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
&num_ch, &ch_mask, &ch_rate,
&port_type, CODEC_TX);
+ if (clk_rate)
+ ch_rate = clk_rate;
if (ret)
return ret;
@@ -1325,10 +1368,12 @@
/* enable clock scaling */
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
- wcd938x_tx_connect_port(component, DMIC0 + (w->shift), true);
+ wcd938x_tx_connect_port(component, DMIC0 + (w->shift),
+ SWR_CLK_RATE_2P4MHZ, true);
break;
case SND_SOC_DAPM_POST_PMD:
- wcd938x_tx_connect_port(component, DMIC0 + (w->shift), false);
+ wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
+ false);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_CDC_AMIC_CTL,
(0x01 << dmic_ctl_shift),
@@ -1449,32 +1494,54 @@
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int ret = 0;
int bank = 0;
- int mode = 0;
+ u8 mode = 0;
+ int i = 0;
+ int rate = 0;
- bank = wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
- wcd938x->tx_swr_dev->dev_num);
- wcd938x_swr_slv_set_host_clk_div2(wcd938x->tx_swr_dev,
- wcd938x->tx_swr_dev->dev_num, bank);
+ bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
+ wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
+
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+ if (test_bit(WCD_ADC1, &wcd938x->status_mask))
+ mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
+ if (test_bit(WCD_ADC2, &wcd938x->status_mask))
+ mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
+ if (test_bit(WCD_ADC3, &wcd938x->status_mask))
+ mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
+ if (test_bit(WCD_ADC4, &wcd938x->status_mask))
+ mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
+
+ if (mode != 0) {
+ for (i = 0; i < ADC_MODE_ULP2; i++) {
+ if (mode & (1 << i)) {
+ i++;
+ break;
+ }
+ }
+ }
+ rate = wcd938x_get_clk_rate(i);
+ wcd938x_set_swr_clk_rate(component, rate, bank);
+ }
ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
wcd938x->tx_swr_dev->dev_num,
true);
- if (test_bit(WCD_ADC1, &wcd938x->status_mask))
- mode |= wcd938x->tx_mode[WCD_ADC1];
- if (test_bit(WCD_ADC2, &wcd938x->status_mask))
- mode |= wcd938x->tx_mode[WCD_ADC2];
- if (test_bit(WCD_ADC3, &wcd938x->status_mask))
- mode |= wcd938x->tx_mode[WCD_ADC3];
- if (test_bit(WCD_ADC4, &wcd938x->status_mask))
- mode |= wcd938x->tx_mode[WCD_ADC4];
- wcd938x_set_swr_clk_rate(component, mode, bank);
+ if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+ /* Copy clk settings to active bank */
+ wcd938x_set_swr_clk_rate(component, rate, !bank);
+ }
break;
case SND_SOC_DAPM_POST_PMD:
+ if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+ rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
+ wcd938x_set_swr_clk_rate(component, rate, !bank);
+ }
ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
wcd938x->tx_swr_dev->dev_num,
false);
- wcd938x_set_swr_clk_rate(component, ADC_MODE_INVALID, bank);
+ if (strnstr(w->name, "ADC", sizeof("ADC")))
+ wcd938x_set_swr_clk_rate(component, rate, bank);
break;
};
@@ -1521,6 +1588,7 @@
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
+ int clk_rate = 0;
dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
w->name, event);
@@ -1532,19 +1600,25 @@
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
set_bit(w->shift, &wcd938x->status_mask);
+ clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
/* Enable BCS for Headset mic */
if (w->shift == 1 && !(snd_soc_component_read32(component,
WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
- wcd938x_tx_connect_port(component, MBHC, true);
+ if (!wcd938x->bcs_dis)
+ wcd938x_tx_connect_port(component, MBHC,
+ SWR_CLK_RATE_4P8MHZ, true);
set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
}
- wcd938x_tx_connect_port(component, ADC1 + (w->shift), true);
+ wcd938x_tx_connect_port(component, ADC1 + (w->shift), clk_rate,
+ true);
break;
case SND_SOC_DAPM_POST_PMD:
- wcd938x_tx_connect_port(component, ADC1 + (w->shift), false);
+ wcd938x_tx_connect_port(component, ADC1 + (w->shift), 0, false);
if (w->shift == 1 &&
test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
- wcd938x_tx_connect_port(component, MBHC, false);
+ if (!wcd938x->bcs_dis)
+ wcd938x_tx_connect_port(component, MBHC, 0,
+ false);
clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
}
snd_soc_component_update_bits(component,
@@ -2305,6 +2379,30 @@
return 0;
}
+static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component =
+ snd_soc_kcontrol_component(kcontrol);
+ struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
+
+ ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
+
+ return 0;
+}
+
+static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component =
+ snd_soc_kcontrol_component(kcontrol);
+ struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
+
+ wcd938x->bcs_dis = ucontrol->value.integer.value[0];
+
+ return 0;
+}
+
static const char * const tx_mode_mux_text_wcd9380[] = {
"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
};
@@ -2391,6 +2489,9 @@
SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
wcd938x_ldoh_get, wcd938x_ldoh_put),
+ SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
+ wcd938x_bcs_get, wcd938x_bcs_put),
+
SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,