asoc: codecs: Update muxsel registers only when clock counts are not stale
During SSR/PDR use cases, core clock count in different
macros becomes stale and muxsel registers are accessed
leading to NOC errors. Update muxsel registers only after
clock counts are reset after SSR/PDR recovery.
Change-Id: I656f8e7ddc8a92a325c2ba644f1a945cbafb08a0
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
diff --git a/asoc/codecs/bolero/bolero-clk-rsc.c b/asoc/codecs/bolero/bolero-clk-rsc.c
index daed7e6..9cc9b1c 100644
--- a/asoc/codecs/bolero/bolero-clk-rsc.c
+++ b/asoc/codecs/bolero/bolero-clk-rsc.c
@@ -38,6 +38,7 @@
int reg_seq_en_cnt;
int va_tx_clk_cnt;
bool dev_up;
+ bool dev_up_gfmux;
u32 num_fs_reg;
u32 *fs_gen_seq;
int default_clk_id[MAX_CLK];
@@ -65,10 +66,14 @@
}
mutex_lock(&priv->rsc_clk_lock);
- if (event == BOLERO_MACRO_EVT_SSR_UP)
+ if (event == BOLERO_MACRO_EVT_SSR_UP) {
priv->dev_up = true;
- else if (event == BOLERO_MACRO_EVT_SSR_DOWN)
+ } else if (event == BOLERO_MACRO_EVT_SSR_DOWN) {
priv->dev_up = false;
+ priv->dev_up_gfmux = false;
+ } else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) {
+ priv->dev_up_gfmux = true;
+ }
mutex_unlock(&priv->rsc_clk_lock);
return 0;
@@ -282,10 +287,12 @@
* care in DSP itself
*/
if (clk_id != VA_CORE_CLK) {
- iowrite32(0x1, clk_muxsel);
- muxsel = ioread32(clk_muxsel);
- trace_printk("%s: muxsel value after enable: %d\n",
- __func__, muxsel);
+ if (priv->dev_up_gfmux) {
+ iowrite32(0x1, clk_muxsel);
+ muxsel = ioread32(clk_muxsel);
+ trace_printk("%s: muxsel value after enable: %d\n",
+ __func__, muxsel);
+ }
bolero_clk_rsc_mux0_clk_request(priv,
default_clk_id,
false);
@@ -313,10 +320,12 @@
* This configuration would be taken
* care in DSP itself.
*/
- iowrite32(0x0, clk_muxsel);
- muxsel = ioread32(clk_muxsel);
- trace_printk("%s: muxsel value after disable: %d\n",
- __func__, muxsel);
+ if (priv->dev_up_gfmux) {
+ iowrite32(0x0, clk_muxsel);
+ muxsel = ioread32(clk_muxsel);
+ trace_printk("%s: muxsel value after disable: %d\n",
+ __func__, muxsel);
+ }
}
}
if (priv->clk[clk_id + NPL_CLK_OFFSET])
@@ -706,6 +715,7 @@
}
priv->dev = &pdev->dev;
priv->dev_up = true;
+ priv->dev_up_gfmux = true;
mutex_init(&priv->rsc_clk_lock);
mutex_init(&priv->fs_gen_lock);
dev_set_drvdata(&pdev->dev, priv);