Laxminath Kasam | 9e78ef8 | 2019-07-01 12:31:45 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (c) 2015, 2018-2019, The Linux Foundation. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #include <linux/regmap.h> |
| 7 | #include <linux/device.h> |
| 8 | #include "wsa881x-registers-analog.h" |
| 9 | #include "wsa881x-analog.h" |
| 10 | |
| 11 | struct reg_default wsa881x_ana_reg_defaults[] = { |
| 12 | {WSA881X_CHIP_ID0, 0x00}, |
| 13 | {WSA881X_CHIP_ID1, 0x00}, |
| 14 | {WSA881X_CHIP_ID2, 0x00}, |
| 15 | {WSA881X_CHIP_ID3, 0x02}, |
| 16 | {WSA881X_BUS_ID, 0x00}, |
| 17 | {WSA881X_CDC_RST_CTL, 0x00}, |
| 18 | {WSA881X_CDC_TOP_CLK_CTL, 0x03}, |
| 19 | {WSA881X_CDC_ANA_CLK_CTL, 0x00}, |
| 20 | {WSA881X_CDC_DIG_CLK_CTL, 0x00}, |
| 21 | {WSA881X_CLOCK_CONFIG, 0x00}, |
| 22 | {WSA881X_ANA_CTL, 0x08}, |
| 23 | {WSA881X_SWR_RESET_EN, 0x00}, |
| 24 | {WSA881X_TEMP_DETECT_CTL, 0x01}, |
| 25 | {WSA881X_TEMP_MSB, 0x00}, |
| 26 | {WSA881X_TEMP_LSB, 0x00}, |
| 27 | {WSA881X_TEMP_CONFIG0, 0x00}, |
| 28 | {WSA881X_TEMP_CONFIG1, 0x00}, |
| 29 | {WSA881X_CDC_CLIP_CTL, 0x03}, |
| 30 | {WSA881X_SDM_PDM9_LSB, 0x00}, |
| 31 | {WSA881X_SDM_PDM9_MSB, 0x00}, |
| 32 | {WSA881X_CDC_RX_CTL, 0x7E}, |
| 33 | {WSA881X_DEM_BYPASS_DATA0, 0x00}, |
| 34 | {WSA881X_DEM_BYPASS_DATA1, 0x00}, |
| 35 | {WSA881X_DEM_BYPASS_DATA2, 0x00}, |
| 36 | {WSA881X_DEM_BYPASS_DATA3, 0x00}, |
| 37 | {WSA881X_OTP_CTRL0, 0x00}, |
| 38 | {WSA881X_OTP_CTRL1, 0x00}, |
| 39 | {WSA881X_HDRIVE_CTL_GROUP1, 0x00}, |
| 40 | {WSA881X_INTR_MODE, 0x00}, |
| 41 | {WSA881X_INTR_MASK, 0x1F}, |
| 42 | {WSA881X_INTR_STATUS, 0x00}, |
| 43 | {WSA881X_INTR_CLEAR, 0x00}, |
| 44 | {WSA881X_INTR_LEVEL, 0x00}, |
| 45 | {WSA881X_INTR_SET, 0x00}, |
| 46 | {WSA881X_INTR_TEST, 0x00}, |
| 47 | {WSA881X_PDM_TEST_MODE, 0x00}, |
| 48 | {WSA881X_ATE_TEST_MODE, 0x00}, |
| 49 | {WSA881X_PIN_CTL_MODE, 0x00}, |
| 50 | {WSA881X_PIN_CTL_OE, 0x00}, |
| 51 | {WSA881X_PIN_WDATA_IOPAD, 0x00}, |
| 52 | {WSA881X_PIN_STATUS, 0x00}, |
| 53 | {WSA881X_DIG_DEBUG_MODE, 0x00}, |
| 54 | {WSA881X_DIG_DEBUG_SEL, 0x00}, |
| 55 | {WSA881X_DIG_DEBUG_EN, 0x00}, |
| 56 | {WSA881X_SWR_HM_TEST1, 0x08}, |
| 57 | {WSA881X_SWR_HM_TEST2, 0x00}, |
| 58 | {WSA881X_TEMP_DETECT_DBG_CTL, 0x00}, |
| 59 | {WSA881X_TEMP_DEBUG_MSB, 0x00}, |
| 60 | {WSA881X_TEMP_DEBUG_LSB, 0x00}, |
| 61 | {WSA881X_SAMPLE_EDGE_SEL, 0x0C}, |
| 62 | {WSA881X_SPARE_0, 0x00}, |
| 63 | {WSA881X_SPARE_1, 0x00}, |
| 64 | {WSA881X_SPARE_2, 0x00}, |
| 65 | {WSA881X_OTP_REG_0, 0x01}, |
| 66 | {WSA881X_OTP_REG_1, 0xFF}, |
| 67 | {WSA881X_OTP_REG_2, 0xC0}, |
| 68 | {WSA881X_OTP_REG_3, 0xFF}, |
| 69 | {WSA881X_OTP_REG_4, 0xC0}, |
| 70 | {WSA881X_OTP_REG_5, 0xFF}, |
| 71 | {WSA881X_OTP_REG_6, 0xFF}, |
| 72 | {WSA881X_OTP_REG_7, 0xFF}, |
| 73 | {WSA881X_OTP_REG_8, 0xFF}, |
| 74 | {WSA881X_OTP_REG_9, 0xFF}, |
| 75 | {WSA881X_OTP_REG_10, 0xFF}, |
| 76 | {WSA881X_OTP_REG_11, 0xFF}, |
| 77 | {WSA881X_OTP_REG_12, 0xFF}, |
| 78 | {WSA881X_OTP_REG_13, 0xFF}, |
| 79 | {WSA881X_OTP_REG_14, 0xFF}, |
| 80 | {WSA881X_OTP_REG_15, 0xFF}, |
| 81 | {WSA881X_OTP_REG_16, 0xFF}, |
| 82 | {WSA881X_OTP_REG_17, 0xFF}, |
| 83 | {WSA881X_OTP_REG_18, 0xFF}, |
| 84 | {WSA881X_OTP_REG_19, 0xFF}, |
| 85 | {WSA881X_OTP_REG_20, 0xFF}, |
| 86 | {WSA881X_OTP_REG_21, 0xFF}, |
| 87 | {WSA881X_OTP_REG_22, 0xFF}, |
| 88 | {WSA881X_OTP_REG_23, 0xFF}, |
| 89 | {WSA881X_OTP_REG_24, 0x03}, |
| 90 | {WSA881X_OTP_REG_25, 0x01}, |
| 91 | {WSA881X_OTP_REG_26, 0x03}, |
| 92 | {WSA881X_OTP_REG_27, 0x11}, |
| 93 | {WSA881X_OTP_REG_28, 0xFF}, |
| 94 | {WSA881X_OTP_REG_29, 0xFF}, |
| 95 | {WSA881X_OTP_REG_30, 0xFF}, |
| 96 | {WSA881X_OTP_REG_31, 0xFF}, |
| 97 | {WSA881X_OTP_REG_63, 0x40}, |
| 98 | /* WSA881x Analog registers */ |
| 99 | {WSA881X_BIAS_REF_CTRL, 0x6C}, |
| 100 | {WSA881X_BIAS_TEST, 0x16}, |
| 101 | {WSA881X_BIAS_BIAS, 0xF0}, |
| 102 | {WSA881X_TEMP_OP, 0x00}, |
| 103 | {WSA881X_TEMP_IREF_CTRL, 0x56}, |
| 104 | {WSA881X_TEMP_ISENS_CTRL, 0x47}, |
| 105 | {WSA881X_TEMP_CLK_CTRL, 0x87}, |
| 106 | {WSA881X_TEMP_TEST, 0x00}, |
| 107 | {WSA881X_TEMP_BIAS, 0x51}, |
| 108 | {WSA881X_TEMP_ADC_CTRL, 0x00}, |
| 109 | {WSA881X_TEMP_DOUT_MSB, 0x00}, |
| 110 | {WSA881X_TEMP_DOUT_LSB, 0x00}, |
| 111 | {WSA881X_ADC_EN_MODU_V, 0x00}, |
| 112 | {WSA881X_ADC_EN_MODU_I, 0x00}, |
| 113 | {WSA881X_ADC_EN_DET_TEST_V, 0x00}, |
| 114 | {WSA881X_ADC_EN_DET_TEST_I, 0x00}, |
| 115 | {WSA881X_ADC_SEL_IBIAS, 0x25}, |
| 116 | {WSA881X_ADC_EN_SEL_IBIAS, 0x10}, |
| 117 | {WSA881X_SPKR_DRV_EN, 0x74}, |
| 118 | {WSA881X_SPKR_DRV_GAIN, 0x01}, |
| 119 | {WSA881X_SPKR_DAC_CTL, 0x40}, |
| 120 | {WSA881X_SPKR_DRV_DBG, 0x15}, |
| 121 | {WSA881X_SPKR_PWRSTG_DBG, 0x00}, |
| 122 | {WSA881X_SPKR_OCP_CTL, 0xD4}, |
| 123 | {WSA881X_SPKR_CLIP_CTL, 0x90}, |
| 124 | {WSA881X_SPKR_BBM_CTL, 0x00}, |
| 125 | {WSA881X_SPKR_MISC_CTL1, 0x80}, |
| 126 | {WSA881X_SPKR_MISC_CTL2, 0x00}, |
| 127 | {WSA881X_SPKR_BIAS_INT, 0x56}, |
| 128 | {WSA881X_SPKR_PA_INT, 0x54}, |
| 129 | {WSA881X_SPKR_BIAS_CAL, 0xAC}, |
| 130 | {WSA881X_SPKR_BIAS_PSRR, 0x54}, |
| 131 | {WSA881X_SPKR_STATUS1, 0x00}, |
| 132 | {WSA881X_SPKR_STATUS2, 0x00}, |
| 133 | {WSA881X_BOOST_EN_CTL, 0x18}, |
| 134 | {WSA881X_BOOST_CURRENT_LIMIT, 0x7A}, |
| 135 | {WSA881X_BOOST_PS_CTL, 0xC0}, |
| 136 | {WSA881X_BOOST_PRESET_OUT1, 0x77}, |
| 137 | {WSA881X_BOOST_PRESET_OUT2, 0x70}, |
| 138 | {WSA881X_BOOST_FORCE_OUT, 0x0E}, |
| 139 | {WSA881X_BOOST_LDO_PROG, 0x16}, |
| 140 | {WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71}, |
| 141 | {WSA881X_BOOST_RON_CTL, 0x0F}, |
| 142 | {WSA881X_BOOST_LOOP_STABILITY, 0xAD}, |
| 143 | {WSA881X_BOOST_ZX_CTL, 0x34}, |
| 144 | {WSA881X_BOOST_START_CTL, 0x23}, |
| 145 | {WSA881X_BOOST_MISC1_CTL, 0x80}, |
| 146 | {WSA881X_BOOST_MISC2_CTL, 0x00}, |
| 147 | {WSA881X_BOOST_MISC3_CTL, 0x00}, |
| 148 | {WSA881X_BOOST_ATEST_CTL, 0x00}, |
| 149 | {WSA881X_SPKR_PROT_FE_GAIN, 0x46}, |
| 150 | {WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B}, |
| 151 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D}, |
| 152 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D}, |
| 153 | {WSA881X_SPKR_PROT_ATEST1, 0x01}, |
| 154 | {WSA881X_SPKR_PROT_ATEST2, 0x00}, |
| 155 | {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D}, |
| 156 | {WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D}, |
| 157 | {WSA881X_BONGO_RESRV_REG1, 0x00}, |
| 158 | {WSA881X_BONGO_RESRV_REG2, 0x00}, |
| 159 | {WSA881X_SPKR_PROT_SAR, 0x00}, |
| 160 | {WSA881X_SPKR_STATUS3, 0x00}, |
| 161 | }; |
| 162 | |
| 163 | struct reg_default wsa881x_ana_reg_defaults_0[] = { |
| 164 | {WSA881X_CHIP_ID0, 0x00}, |
| 165 | {WSA881X_CHIP_ID1, 0x00}, |
| 166 | {WSA881X_CHIP_ID2, 0x00}, |
| 167 | {WSA881X_CHIP_ID3, 0x02}, |
| 168 | {WSA881X_BUS_ID, 0x00}, |
| 169 | {WSA881X_CDC_RST_CTL, 0x00}, |
| 170 | {WSA881X_CDC_TOP_CLK_CTL, 0x03}, |
| 171 | {WSA881X_CDC_ANA_CLK_CTL, 0x00}, |
| 172 | {WSA881X_CDC_DIG_CLK_CTL, 0x00}, |
| 173 | {WSA881X_CLOCK_CONFIG, 0x00}, |
| 174 | {WSA881X_ANA_CTL, 0x08}, |
| 175 | {WSA881X_SWR_RESET_EN, 0x00}, |
| 176 | {WSA881X_TEMP_DETECT_CTL, 0x01}, |
| 177 | {WSA881X_TEMP_MSB, 0x00}, |
| 178 | {WSA881X_TEMP_LSB, 0x00}, |
| 179 | {WSA881X_TEMP_CONFIG0, 0x00}, |
| 180 | {WSA881X_TEMP_CONFIG1, 0x00}, |
| 181 | {WSA881X_CDC_CLIP_CTL, 0x03}, |
| 182 | {WSA881X_SDM_PDM9_LSB, 0x00}, |
| 183 | {WSA881X_SDM_PDM9_MSB, 0x00}, |
| 184 | {WSA881X_CDC_RX_CTL, 0x7E}, |
| 185 | {WSA881X_DEM_BYPASS_DATA0, 0x00}, |
| 186 | {WSA881X_DEM_BYPASS_DATA1, 0x00}, |
| 187 | {WSA881X_DEM_BYPASS_DATA2, 0x00}, |
| 188 | {WSA881X_DEM_BYPASS_DATA3, 0x00}, |
| 189 | {WSA881X_OTP_CTRL0, 0x00}, |
| 190 | {WSA881X_OTP_CTRL1, 0x00}, |
| 191 | {WSA881X_HDRIVE_CTL_GROUP1, 0x00}, |
| 192 | {WSA881X_INTR_MODE, 0x00}, |
| 193 | {WSA881X_INTR_MASK, 0x1F}, |
| 194 | {WSA881X_INTR_STATUS, 0x00}, |
| 195 | {WSA881X_INTR_CLEAR, 0x00}, |
| 196 | {WSA881X_INTR_LEVEL, 0x00}, |
| 197 | {WSA881X_INTR_SET, 0x00}, |
| 198 | {WSA881X_INTR_TEST, 0x00}, |
| 199 | {WSA881X_PDM_TEST_MODE, 0x00}, |
| 200 | {WSA881X_ATE_TEST_MODE, 0x00}, |
| 201 | {WSA881X_PIN_CTL_MODE, 0x00}, |
| 202 | {WSA881X_PIN_CTL_OE, 0x00}, |
| 203 | {WSA881X_PIN_WDATA_IOPAD, 0x00}, |
| 204 | {WSA881X_PIN_STATUS, 0x00}, |
| 205 | {WSA881X_DIG_DEBUG_MODE, 0x00}, |
| 206 | {WSA881X_DIG_DEBUG_SEL, 0x00}, |
| 207 | {WSA881X_DIG_DEBUG_EN, 0x00}, |
| 208 | {WSA881X_SWR_HM_TEST1, 0x08}, |
| 209 | {WSA881X_SWR_HM_TEST2, 0x00}, |
| 210 | {WSA881X_TEMP_DETECT_DBG_CTL, 0x00}, |
| 211 | {WSA881X_TEMP_DEBUG_MSB, 0x00}, |
| 212 | {WSA881X_TEMP_DEBUG_LSB, 0x00}, |
| 213 | {WSA881X_SAMPLE_EDGE_SEL, 0x0C}, |
| 214 | {WSA881X_SPARE_0, 0x00}, |
| 215 | {WSA881X_SPARE_1, 0x00}, |
| 216 | {WSA881X_SPARE_2, 0x00}, |
| 217 | {WSA881X_OTP_REG_0, 0x01}, |
| 218 | {WSA881X_OTP_REG_1, 0xFF}, |
| 219 | {WSA881X_OTP_REG_2, 0xC0}, |
| 220 | {WSA881X_OTP_REG_3, 0xFF}, |
| 221 | {WSA881X_OTP_REG_4, 0xC0}, |
| 222 | {WSA881X_OTP_REG_5, 0xFF}, |
| 223 | {WSA881X_OTP_REG_6, 0xFF}, |
| 224 | {WSA881X_OTP_REG_7, 0xFF}, |
| 225 | {WSA881X_OTP_REG_8, 0xFF}, |
| 226 | {WSA881X_OTP_REG_9, 0xFF}, |
| 227 | {WSA881X_OTP_REG_10, 0xFF}, |
| 228 | {WSA881X_OTP_REG_11, 0xFF}, |
| 229 | {WSA881X_OTP_REG_12, 0xFF}, |
| 230 | {WSA881X_OTP_REG_13, 0xFF}, |
| 231 | {WSA881X_OTP_REG_14, 0xFF}, |
| 232 | {WSA881X_OTP_REG_15, 0xFF}, |
| 233 | {WSA881X_OTP_REG_16, 0xFF}, |
| 234 | {WSA881X_OTP_REG_17, 0xFF}, |
| 235 | {WSA881X_OTP_REG_18, 0xFF}, |
| 236 | {WSA881X_OTP_REG_19, 0xFF}, |
| 237 | {WSA881X_OTP_REG_20, 0xFF}, |
| 238 | {WSA881X_OTP_REG_21, 0xFF}, |
| 239 | {WSA881X_OTP_REG_22, 0xFF}, |
| 240 | {WSA881X_OTP_REG_23, 0xFF}, |
| 241 | {WSA881X_OTP_REG_24, 0x03}, |
| 242 | {WSA881X_OTP_REG_25, 0x01}, |
| 243 | {WSA881X_OTP_REG_26, 0x03}, |
| 244 | {WSA881X_OTP_REG_27, 0x11}, |
| 245 | {WSA881X_OTP_REG_28, 0xFF}, |
| 246 | {WSA881X_OTP_REG_29, 0xFF}, |
| 247 | {WSA881X_OTP_REG_30, 0xFF}, |
| 248 | {WSA881X_OTP_REG_31, 0xFF}, |
| 249 | {WSA881X_OTP_REG_63, 0x40}, |
| 250 | }; |
| 251 | |
| 252 | struct reg_default wsa881x_ana_reg_defaults_1[] = { |
| 253 | {WSA881X_BIAS_REF_CTRL - WSA881X_ANALOG_BASE, 0x6C}, |
| 254 | {WSA881X_BIAS_TEST - WSA881X_ANALOG_BASE, 0x16}, |
| 255 | {WSA881X_BIAS_BIAS - WSA881X_ANALOG_BASE, 0xF0}, |
| 256 | {WSA881X_TEMP_OP - WSA881X_ANALOG_BASE, 0x00}, |
| 257 | {WSA881X_TEMP_IREF_CTRL - WSA881X_ANALOG_BASE, 0x56}, |
| 258 | {WSA881X_TEMP_ISENS_CTRL - WSA881X_ANALOG_BASE, 0x47}, |
| 259 | {WSA881X_TEMP_CLK_CTRL - WSA881X_ANALOG_BASE, 0x87}, |
| 260 | {WSA881X_TEMP_TEST - WSA881X_ANALOG_BASE, 0x00}, |
| 261 | {WSA881X_TEMP_BIAS - WSA881X_ANALOG_BASE, 0x51}, |
| 262 | {WSA881X_TEMP_ADC_CTRL - WSA881X_ANALOG_BASE, 0x00}, |
| 263 | {WSA881X_TEMP_DOUT_MSB - WSA881X_ANALOG_BASE, 0x00}, |
| 264 | {WSA881X_TEMP_DOUT_LSB - WSA881X_ANALOG_BASE, 0x00}, |
| 265 | {WSA881X_ADC_EN_MODU_V - WSA881X_ANALOG_BASE, 0x00}, |
| 266 | {WSA881X_ADC_EN_MODU_I - WSA881X_ANALOG_BASE, 0x00}, |
| 267 | {WSA881X_ADC_EN_DET_TEST_V - WSA881X_ANALOG_BASE, 0x00}, |
| 268 | {WSA881X_ADC_EN_DET_TEST_I - WSA881X_ANALOG_BASE, 0x00}, |
| 269 | {WSA881X_ADC_SEL_IBIAS - WSA881X_ANALOG_BASE, 0x25}, |
| 270 | {WSA881X_ADC_EN_SEL_IBIAS - WSA881X_ANALOG_BASE, 0x10}, |
| 271 | {WSA881X_SPKR_DRV_EN - WSA881X_ANALOG_BASE, 0x74}, |
| 272 | {WSA881X_SPKR_DRV_GAIN - WSA881X_ANALOG_BASE, 0x01}, |
| 273 | {WSA881X_SPKR_DAC_CTL - WSA881X_ANALOG_BASE, 0x40}, |
| 274 | {WSA881X_SPKR_DRV_DBG - WSA881X_ANALOG_BASE, 0x15}, |
| 275 | {WSA881X_SPKR_PWRSTG_DBG - WSA881X_ANALOG_BASE, 0x00}, |
| 276 | {WSA881X_SPKR_OCP_CTL - WSA881X_ANALOG_BASE, 0xD4}, |
| 277 | {WSA881X_SPKR_CLIP_CTL - WSA881X_ANALOG_BASE, 0x90}, |
| 278 | {WSA881X_SPKR_BBM_CTL - WSA881X_ANALOG_BASE, 0x00}, |
| 279 | {WSA881X_SPKR_MISC_CTL1 - WSA881X_ANALOG_BASE, 0x80}, |
| 280 | {WSA881X_SPKR_MISC_CTL2 - WSA881X_ANALOG_BASE, 0x00}, |
| 281 | {WSA881X_SPKR_BIAS_INT - WSA881X_ANALOG_BASE, 0x56}, |
| 282 | {WSA881X_SPKR_PA_INT - WSA881X_ANALOG_BASE, 0x54}, |
| 283 | {WSA881X_SPKR_BIAS_CAL - WSA881X_ANALOG_BASE, 0xAC}, |
| 284 | {WSA881X_SPKR_BIAS_PSRR - WSA881X_ANALOG_BASE, 0x54}, |
| 285 | {WSA881X_SPKR_STATUS1 - WSA881X_ANALOG_BASE, 0x00}, |
| 286 | {WSA881X_SPKR_STATUS2 - WSA881X_ANALOG_BASE, 0x00}, |
| 287 | {WSA881X_BOOST_EN_CTL - WSA881X_ANALOG_BASE, 0x18}, |
| 288 | {WSA881X_BOOST_CURRENT_LIMIT - WSA881X_ANALOG_BASE, 0x7A}, |
| 289 | {WSA881X_BOOST_PS_CTL - WSA881X_ANALOG_BASE, 0xC0}, |
| 290 | {WSA881X_BOOST_PRESET_OUT1 - WSA881X_ANALOG_BASE, 0x77}, |
| 291 | {WSA881X_BOOST_PRESET_OUT2 - WSA881X_ANALOG_BASE, 0x70}, |
| 292 | {WSA881X_BOOST_FORCE_OUT - WSA881X_ANALOG_BASE, 0x0E}, |
| 293 | {WSA881X_BOOST_LDO_PROG - WSA881X_ANALOG_BASE, 0x16}, |
| 294 | {WSA881X_BOOST_SLOPE_COMP_ISENSE_FB - WSA881X_ANALOG_BASE, 0x71}, |
| 295 | {WSA881X_BOOST_RON_CTL - WSA881X_ANALOG_BASE, 0x0F}, |
| 296 | {WSA881X_BOOST_LOOP_STABILITY - WSA881X_ANALOG_BASE, 0xAD}, |
| 297 | {WSA881X_BOOST_ZX_CTL - WSA881X_ANALOG_BASE, 0x34}, |
| 298 | {WSA881X_BOOST_START_CTL - WSA881X_ANALOG_BASE, 0x23}, |
| 299 | {WSA881X_BOOST_MISC1_CTL - WSA881X_ANALOG_BASE, 0x80}, |
| 300 | {WSA881X_BOOST_MISC2_CTL - WSA881X_ANALOG_BASE, 0x00}, |
| 301 | {WSA881X_BOOST_MISC3_CTL - WSA881X_ANALOG_BASE, 0x00}, |
| 302 | {WSA881X_BOOST_ATEST_CTL - WSA881X_ANALOG_BASE, 0x00}, |
| 303 | {WSA881X_SPKR_PROT_FE_GAIN - WSA881X_ANALOG_BASE, 0x46}, |
| 304 | {WSA881X_SPKR_PROT_FE_CM_LDO_SET - WSA881X_ANALOG_BASE, 0x3B}, |
| 305 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 - WSA881X_ANALOG_BASE, 0x8D}, |
| 306 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 - WSA881X_ANALOG_BASE, 0x8D}, |
| 307 | {WSA881X_SPKR_PROT_ATEST1 - WSA881X_ANALOG_BASE, 0x01}, |
| 308 | {WSA881X_SPKR_PROT_ATEST2 - WSA881X_ANALOG_BASE, 0x00}, |
| 309 | {WSA881X_SPKR_PROT_FE_VSENSE_VCM - WSA881X_ANALOG_BASE, 0x8D}, |
| 310 | {WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 - WSA881X_ANALOG_BASE, 0x4D}, |
| 311 | {WSA881X_BONGO_RESRV_REG1 - WSA881X_ANALOG_BASE, 0x00}, |
| 312 | {WSA881X_BONGO_RESRV_REG2 - WSA881X_ANALOG_BASE, 0x00}, |
| 313 | {WSA881X_SPKR_PROT_SAR - WSA881X_ANALOG_BASE, 0x00}, |
| 314 | {WSA881X_SPKR_STATUS3 - WSA881X_ANALOG_BASE, 0x00}, |
| 315 | }; |
| 316 | |
| 317 | static const struct reg_sequence wsa881x_rev_2_0_dig[] = { |
| 318 | {WSA881X_RESET_CTL, 0x00}, |
| 319 | {WSA881X_TADC_VALUE_CTL, 0x01}, |
| 320 | {WSA881X_INTR_MASK, 0x1B}, |
| 321 | {WSA881X_IOPAD_CTL, 0x00}, |
| 322 | {WSA881X_OTP_REG_28, 0x3F}, |
| 323 | {WSA881X_OTP_REG_29, 0x3F}, |
| 324 | {WSA881X_OTP_REG_30, 0x01}, |
| 325 | {WSA881X_OTP_REG_31, 0x01}, |
| 326 | }; |
| 327 | |
| 328 | static const struct reg_sequence wsa881x_rev_2_0_ana[] = { |
| 329 | {WSA881X_TEMP_ADC_CTRL, 0x03}, |
| 330 | {WSA881X_ADC_SEL_IBIAS, 0x45}, |
| 331 | {WSA881X_SPKR_DRV_GAIN, 0xC1}, |
| 332 | {WSA881X_SPKR_DAC_CTL, 0x42}, |
| 333 | {WSA881X_SPKR_BBM_CTL, 0x02}, |
| 334 | {WSA881X_SPKR_MISC_CTL1, 0x40}, |
| 335 | {WSA881X_SPKR_MISC_CTL2, 0x07}, |
| 336 | {WSA881X_SPKR_BIAS_INT, 0x5F}, |
| 337 | {WSA881X_SPKR_BIAS_PSRR, 0x44}, |
| 338 | {WSA881X_BOOST_PS_CTL, 0xA0}, |
| 339 | {WSA881X_BOOST_PRESET_OUT1, 0xB7}, |
| 340 | {WSA881X_BOOST_LOOP_STABILITY, 0x8D}, |
| 341 | {WSA881X_SPKR_PROT_ATEST2, 0x02}, |
| 342 | {WSA881X_BONGO_RESRV_REG1, 0x5E}, |
| 343 | {WSA881X_BONGO_RESRV_REG2, 0x07}, |
| 344 | }; |
| 345 | |
| 346 | struct reg_default wsa881x_rev_2_0_regmap_ana[] = { |
| 347 | {WSA881X_TEMP_ADC_CTRL - WSA881X_ANALOG_BASE, 0x03}, |
| 348 | {WSA881X_ADC_SEL_IBIAS - WSA881X_ANALOG_BASE, 0x45}, |
| 349 | {WSA881X_SPKR_DRV_GAIN - WSA881X_ANALOG_BASE, 0xC1}, |
| 350 | {WSA881X_SPKR_DAC_CTL - WSA881X_ANALOG_BASE, 0x42}, |
| 351 | {WSA881X_SPKR_BBM_CTL - WSA881X_ANALOG_BASE, 0x02}, |
| 352 | {WSA881X_SPKR_MISC_CTL1 - WSA881X_ANALOG_BASE, 0x40}, |
| 353 | {WSA881X_SPKR_MISC_CTL2 - WSA881X_ANALOG_BASE, 0x07}, |
| 354 | {WSA881X_SPKR_BIAS_INT - WSA881X_ANALOG_BASE, 0x5F}, |
| 355 | {WSA881X_SPKR_BIAS_PSRR - WSA881X_ANALOG_BASE, 0x44}, |
| 356 | {WSA881X_BOOST_PS_CTL - WSA881X_ANALOG_BASE, 0xA0}, |
| 357 | {WSA881X_BOOST_PRESET_OUT1 - WSA881X_ANALOG_BASE, 0xB7}, |
| 358 | {WSA881X_BOOST_LOOP_STABILITY - WSA881X_ANALOG_BASE, 0x8D}, |
| 359 | {WSA881X_SPKR_PROT_ATEST2 - WSA881X_ANALOG_BASE, 0x02}, |
| 360 | {WSA881X_BONGO_RESRV_REG1 - WSA881X_ANALOG_BASE, 0x5E}, |
| 361 | {WSA881X_BONGO_RESRV_REG2 - WSA881X_ANALOG_BASE, 0x07}, |
| 362 | }; |
| 363 | |
| 364 | /** |
| 365 | * wsa881x_update_reg_defaults_2_0 - update default values of regs for v2.0 |
| 366 | * |
| 367 | * wsa881x v2.0 has different default values for certain analog and digital |
| 368 | * registers compared to v1.x. Therefore, update the values of these registers |
| 369 | * with the values from tables defined above for v2.0. |
| 370 | */ |
| 371 | void wsa881x_update_reg_defaults_2_0(void) |
| 372 | { |
| 373 | int i, j; |
| 374 | |
| 375 | for (i = 0; i < ARRAY_SIZE(wsa881x_rev_2_0_dig); i++) { |
| 376 | for (j = 0; j < ARRAY_SIZE(wsa881x_ana_reg_defaults); j++) |
| 377 | if (wsa881x_ana_reg_defaults[j].reg == |
| 378 | wsa881x_rev_2_0_dig[i].reg) |
| 379 | wsa881x_ana_reg_defaults[j].def = |
| 380 | wsa881x_rev_2_0_dig[i].def; |
| 381 | } |
| 382 | for (i = 0; i < ARRAY_SIZE(wsa881x_rev_2_0_ana); i++) { |
| 383 | for (j = 0; j < ARRAY_SIZE(wsa881x_ana_reg_defaults); j++) |
| 384 | if (wsa881x_ana_reg_defaults[j].reg == |
| 385 | wsa881x_rev_2_0_ana[i].reg) |
| 386 | wsa881x_ana_reg_defaults[j].def = |
| 387 | wsa881x_rev_2_0_ana[i].def; |
| 388 | } |
| 389 | } |
| 390 | EXPORT_SYMBOL(wsa881x_update_reg_defaults_2_0); |
| 391 | |
| 392 | /** |
| 393 | * wsa881x_update_regmap_2_0 - update regmap framework with new tables |
| 394 | * @regmap: pointer to wsa881x regmap structure |
| 395 | * @flag: indicates digital or analog wsa881x slave |
| 396 | * |
| 397 | * wsa881x v2.0 has some new registers for both analog and digital slaves. |
| 398 | * Update the regmap framework with all the new registers. |
| 399 | */ |
| 400 | void wsa881x_update_regmap_2_0(struct regmap *regmap, int flag) |
| 401 | { |
| 402 | u16 ret = 0; |
| 403 | |
| 404 | switch (flag) { |
| 405 | case WSA881X_DIGITAL_SLAVE: |
| 406 | ret = regmap_register_patch(regmap, wsa881x_rev_2_0_dig, |
| 407 | ARRAY_SIZE(wsa881x_rev_2_0_dig)); |
| 408 | break; |
| 409 | case WSA881X_ANALOG_SLAVE: |
| 410 | ret = regmap_register_patch(regmap, wsa881x_rev_2_0_ana, |
| 411 | ARRAY_SIZE(wsa881x_rev_2_0_ana)); |
| 412 | break; |
| 413 | default: |
| 414 | pr_debug("%s: unknown version", __func__); |
| 415 | ret = -EINVAL; |
| 416 | break; |
| 417 | } |
| 418 | if (ret) |
| 419 | pr_err("%s: Failed to update regmap defaults ret= %d\n", |
| 420 | __func__, ret); |
| 421 | } |
| 422 | EXPORT_SYMBOL(wsa881x_update_regmap_2_0); |
| 423 | |
| 424 | static bool wsa881x_readable_register(struct device *dev, unsigned int reg) |
| 425 | { |
| 426 | return wsa881x_ana_reg_readable[reg]; |
| 427 | } |
| 428 | |
| 429 | static bool wsa881x_volatile_register(struct device *dev, unsigned int reg) |
| 430 | { |
| 431 | switch (reg) { |
| 432 | case WSA881X_CHIP_ID0: |
| 433 | case WSA881X_CHIP_ID1: |
| 434 | case WSA881X_CHIP_ID2: |
| 435 | case WSA881X_CHIP_ID3: |
| 436 | case WSA881X_BUS_ID: |
| 437 | case WSA881X_TEMP_MSB: |
| 438 | case WSA881X_TEMP_LSB: |
| 439 | case WSA881X_SDM_PDM9_LSB: |
| 440 | case WSA881X_SDM_PDM9_MSB: |
| 441 | case WSA881X_OTP_REG_0: |
| 442 | case WSA881X_OTP_REG_1: |
| 443 | case WSA881X_OTP_REG_2: |
| 444 | case WSA881X_OTP_REG_3: |
| 445 | case WSA881X_OTP_REG_4: |
| 446 | case WSA881X_OTP_REG_5: |
| 447 | case WSA881X_OTP_REG_31: |
| 448 | case WSA881X_TEMP_DOUT_MSB: |
| 449 | case WSA881X_TEMP_DOUT_LSB: |
| 450 | case WSA881X_TEMP_OP: |
| 451 | case WSA881X_OTP_CTRL1: |
| 452 | case WSA881X_INTR_STATUS: |
| 453 | case WSA881X_ATE_TEST_MODE: |
| 454 | case WSA881X_PIN_STATUS: |
| 455 | case WSA881X_SWR_HM_TEST2: |
| 456 | case WSA881X_SPKR_STATUS1: |
| 457 | case WSA881X_SPKR_STATUS2: |
| 458 | case WSA881X_SPKR_STATUS3: |
| 459 | case WSA881X_SPKR_PROT_SAR: |
| 460 | return true; |
| 461 | default: |
| 462 | return false; |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | struct regmap_config wsa881x_ana_regmap_config[] = { |
| 467 | { |
| 468 | .reg_bits = 8, |
| 469 | .val_bits = 8, |
| 470 | .cache_type = REGCACHE_NONE, |
| 471 | .reg_defaults = wsa881x_ana_reg_defaults_0, |
| 472 | .num_reg_defaults = ARRAY_SIZE(wsa881x_ana_reg_defaults_0), |
| 473 | .max_register = WSA881X_MAX_REGISTER, |
| 474 | .volatile_reg = wsa881x_volatile_register, |
| 475 | .readable_reg = wsa881x_readable_register, |
| 476 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
| 477 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
| 478 | }, |
| 479 | { |
| 480 | .reg_bits = 8, |
| 481 | .val_bits = 8, |
| 482 | .cache_type = REGCACHE_NONE, |
| 483 | .reg_defaults = wsa881x_ana_reg_defaults_1, |
| 484 | .num_reg_defaults = ARRAY_SIZE(wsa881x_ana_reg_defaults_1), |
| 485 | .max_register = WSA881X_MAX_REGISTER, |
| 486 | .volatile_reg = wsa881x_volatile_register, |
| 487 | .readable_reg = wsa881x_readable_register, |
| 488 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
| 489 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
| 490 | } |
| 491 | }; |