Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Mangesh Kunchamwar | 7f6fc83 | 2019-01-30 16:24:49 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #ifndef __MFD_WCD9XXX_PDATA_H__ |
| 6 | |
| 7 | #define __MFD_WCD9XXX_PDATA_H__ |
| 8 | |
Meng Wang | b0e0479 | 2018-09-27 18:46:44 +0800 | [diff] [blame] | 9 | #if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE) |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 10 | #include <linux/slimbus/slimbus.h> |
Meng Wang | b0e0479 | 2018-09-27 18:46:44 +0800 | [diff] [blame] | 11 | #endif |
| 12 | |
Laxminath Kasam | 605b42f | 2017-08-01 22:02:15 +0530 | [diff] [blame] | 13 | #include "msm-cdc-supply.h" |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 14 | |
| 15 | #define MICBIAS_EXT_BYP_CAP 0x00 |
| 16 | #define MICBIAS_NO_EXT_BYP_CAP 0x01 |
| 17 | |
| 18 | #define SITAR_LDOH_1P95_V 0x0 |
| 19 | #define SITAR_LDOH_2P35_V 0x1 |
| 20 | #define SITAR_LDOH_2P75_V 0x2 |
| 21 | #define SITAR_LDOH_2P85_V 0x3 |
| 22 | |
| 23 | #define SITAR_CFILT1_SEL 0x0 |
| 24 | #define SITAR_CFILT2_SEL 0x1 |
| 25 | #define SITAR_CFILT3_SEL 0x2 |
| 26 | |
| 27 | #define WCD9XXX_LDOH_1P95_V 0x0 |
| 28 | #define WCD9XXX_LDOH_2P35_V 0x1 |
| 29 | #define WCD9XXX_LDOH_2P75_V 0x2 |
| 30 | #define WCD9XXX_LDOH_2P85_V 0x3 |
| 31 | #define WCD9XXX_LDOH_3P0_V 0x3 |
| 32 | |
| 33 | #define TABLA_LDOH_1P95_V 0x0 |
| 34 | #define TABLA_LDOH_2P35_V 0x1 |
| 35 | #define TABLA_LDOH_2P75_V 0x2 |
| 36 | #define TABLA_LDOH_2P85_V 0x3 |
| 37 | |
| 38 | #define TABLA_CFILT1_SEL 0x0 |
| 39 | #define TABLA_CFILT2_SEL 0x1 |
| 40 | #define TABLA_CFILT3_SEL 0x2 |
| 41 | |
| 42 | #define MAX_AMIC_CHANNEL 7 |
| 43 | |
| 44 | #define TABLA_OCP_300_MA 0x0 |
| 45 | #define TABLA_OCP_350_MA 0x2 |
| 46 | #define TABLA_OCP_365_MA 0x3 |
| 47 | #define TABLA_OCP_150_MA 0x4 |
| 48 | #define TABLA_OCP_190_MA 0x6 |
| 49 | #define TABLA_OCP_220_MA 0x7 |
| 50 | |
| 51 | #define TABLA_DCYCLE_255 0x0 |
| 52 | #define TABLA_DCYCLE_511 0x1 |
| 53 | #define TABLA_DCYCLE_767 0x2 |
| 54 | #define TABLA_DCYCLE_1023 0x3 |
| 55 | #define TABLA_DCYCLE_1279 0x4 |
| 56 | #define TABLA_DCYCLE_1535 0x5 |
| 57 | #define TABLA_DCYCLE_1791 0x6 |
| 58 | #define TABLA_DCYCLE_2047 0x7 |
| 59 | #define TABLA_DCYCLE_2303 0x8 |
| 60 | #define TABLA_DCYCLE_2559 0x9 |
| 61 | #define TABLA_DCYCLE_2815 0xA |
| 62 | #define TABLA_DCYCLE_3071 0xB |
| 63 | #define TABLA_DCYCLE_3327 0xC |
| 64 | #define TABLA_DCYCLE_3583 0xD |
| 65 | #define TABLA_DCYCLE_3839 0xE |
| 66 | #define TABLA_DCYCLE_4095 0xF |
| 67 | |
| 68 | #define WCD9XXX_MCLK_CLK_12P288MHZ 12288000 |
| 69 | #define WCD9XXX_MCLK_CLK_9P6HZ 9600000 |
| 70 | |
| 71 | /* Only valid for 9.6 MHz mclk */ |
| 72 | #define WCD9XXX_DMIC_SAMPLE_RATE_600KHZ 600000 |
| 73 | #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 |
| 74 | #define WCD9XXX_DMIC_SAMPLE_RATE_3P2MHZ 3200000 |
| 75 | #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 |
| 76 | |
| 77 | /* Only valid for 12.288 MHz mclk */ |
| 78 | #define WCD9XXX_DMIC_SAMPLE_RATE_768KHZ 768000 |
| 79 | #define WCD9XXX_DMIC_SAMPLE_RATE_2P048MHZ 2048000 |
| 80 | #define WCD9XXX_DMIC_SAMPLE_RATE_3P072MHZ 3072000 |
| 81 | #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 |
| 82 | #define WCD9XXX_DMIC_SAMPLE_RATE_6P144MHZ 6144000 |
| 83 | |
| 84 | #define WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED 0 |
| 85 | |
| 86 | #define WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED 0 |
| 87 | |
| 88 | struct wcd9xxx_amic { |
| 89 | /*legacy mode, txfe_enable and txfe_buff take 7 input |
| 90 | * each bit represent the channel / TXFE number |
| 91 | * and numbered as below |
| 92 | * bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF |
| 93 | * bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF |
| 94 | * ... |
| 95 | * bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF |
| 96 | */ |
| 97 | u8 legacy_mode:MAX_AMIC_CHANNEL; |
| 98 | u8 txfe_enable:MAX_AMIC_CHANNEL; |
| 99 | u8 txfe_buff:MAX_AMIC_CHANNEL; |
| 100 | u8 use_pdata:MAX_AMIC_CHANNEL; |
| 101 | }; |
| 102 | |
| 103 | /* Each micbias can be assigned to one of three cfilters |
| 104 | * Vbatt_min >= .15V + ldoh_v |
| 105 | * ldoh_v >= .15v + cfiltx_mv |
| 106 | * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv |
| 107 | * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv |
| 108 | * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv |
| 109 | * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv |
| 110 | */ |
| 111 | |
| 112 | struct wcd9xxx_micbias_setting { |
| 113 | u8 ldoh_v; |
| 114 | u32 cfilt1_mv; /* in mv */ |
| 115 | u32 cfilt2_mv; /* in mv */ |
| 116 | u32 cfilt3_mv; /* in mv */ |
| 117 | u32 micb1_mv; |
| 118 | u32 micb2_mv; |
| 119 | u32 micb3_mv; |
| 120 | u32 micb4_mv; |
| 121 | /* Different WCD9xxx series codecs may not |
| 122 | * have 4 mic biases. If a codec has fewer |
| 123 | * mic biases, some of these properties will |
| 124 | * not be used. |
| 125 | */ |
| 126 | u8 bias1_cfilt_sel; |
| 127 | u8 bias2_cfilt_sel; |
| 128 | u8 bias3_cfilt_sel; |
| 129 | u8 bias4_cfilt_sel; |
| 130 | u8 bias1_cap_mode; |
| 131 | u8 bias2_cap_mode; |
| 132 | u8 bias3_cap_mode; |
| 133 | u8 bias4_cap_mode; |
| 134 | bool bias2_is_headset_only; |
| 135 | }; |
| 136 | |
| 137 | struct wcd9xxx_ocp_setting { |
| 138 | unsigned int use_pdata:1; /* 0 - use sys default as recommended */ |
| 139 | unsigned int num_attempts:4; /* up to 15 attempts */ |
| 140 | unsigned int run_time:4; /* in duty cycle */ |
| 141 | unsigned int wait_time:4; /* in duty cycle */ |
| 142 | unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */ |
| 143 | }; |
| 144 | |
| 145 | #define WCD9XXX_MAX_REGULATOR 9 |
| 146 | /* |
| 147 | * format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX |
| 148 | * |
| 149 | * <POWER_SUPPLY_PIN_NAME> from Tabla objective spec |
| 150 | */ |
| 151 | |
| 152 | #define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000 |
| 153 | #define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000 |
| 154 | #define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000 |
| 155 | #define WCD9XXX_VDDIO_CDC_CUR_MAX 5000 |
| 156 | |
| 157 | #define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000 |
| 158 | #define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000 |
| 159 | |
| 160 | #define WCD9XXX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv" |
| 161 | #define WCD9XXX_VDD_SPKDRV2_NAME "cdc-vdd-spkdrv-2" |
| 162 | |
| 163 | struct wcd9xxx_regulator { |
| 164 | const char *name; |
| 165 | int min_uV; |
| 166 | int max_uV; |
| 167 | int optimum_uA; |
| 168 | bool ondemand; |
| 169 | struct regulator *regulator; |
| 170 | }; |
| 171 | |
| 172 | struct wcd9xxx_pdata { |
| 173 | int irq; |
| 174 | int irq_base; |
| 175 | int num_irqs; |
| 176 | int reset_gpio; |
Laxminath Kasam | 38070be | 2017-08-17 18:21:59 +0530 | [diff] [blame] | 177 | bool has_buck_vsel_gpio; |
Vatsal Bucha | 8148b99 | 2018-09-27 16:20:30 +0530 | [diff] [blame] | 178 | bool has_micb_supply_en_gpio; |
Laxminath Kasam | 38070be | 2017-08-17 18:21:59 +0530 | [diff] [blame] | 179 | struct device_node *buck_vsel_ctl_np; |
Vatsal Bucha | 8148b99 | 2018-09-27 16:20:30 +0530 | [diff] [blame] | 180 | struct device_node *micb_en_ctl; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 181 | struct device_node *wcd_rst_np; |
| 182 | struct wcd9xxx_amic amic_settings; |
Meng Wang | b0e0479 | 2018-09-27 18:46:44 +0800 | [diff] [blame] | 183 | #if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE) |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 184 | struct slim_device slimbus_slave_device; |
Meng Wang | b0e0479 | 2018-09-27 18:46:44 +0800 | [diff] [blame] | 185 | #endif |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 186 | struct wcd9xxx_micbias_setting micbias; |
| 187 | struct wcd9xxx_ocp_setting ocp; |
| 188 | struct cdc_regulator *regulator; |
| 189 | int num_supplies; |
| 190 | u32 mclk_rate; |
| 191 | u32 dmic_sample_rate; |
| 192 | u32 mad_dmic_sample_rate; |
| 193 | u32 ecpp_dmic_sample_rate; |
| 194 | u32 dmic_clk_drv; |
| 195 | u16 use_pinctrl; |
Mangesh Kunchamwar | 7f6fc83 | 2019-01-30 16:24:49 +0530 | [diff] [blame] | 196 | u32 vote_regulator_on_demand; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 197 | }; |
| 198 | |
| 199 | #endif |