Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <sound/soc.h> |
| 19 | #include <sound/pcm.h> |
| 20 | #include <sound/pcm_params.h> |
| 21 | #include <sound/soc-dapm.h> |
| 22 | #include <sound/tlv.h> |
| 23 | #include <soc/swr-wcd.h> |
| 24 | |
| 25 | #include "bolero-cdc.h" |
| 26 | #include "bolero-cdc-registers.h" |
| 27 | #include "../msm-cdc-pinctrl.h" |
| 28 | |
| 29 | #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 30 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 31 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ |
| 32 | SNDRV_PCM_RATE_384000) |
| 33 | /* Fractional Rates */ |
| 34 | #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ |
| 35 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) |
| 36 | |
| 37 | #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 38 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 39 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 40 | |
| 41 | #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 42 | SNDRV_PCM_RATE_48000) |
| 43 | #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 44 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 45 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 46 | |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 47 | #define SAMPLING_RATE_44P1KHZ 44100 |
| 48 | #define SAMPLING_RATE_88P2KHZ 88200 |
| 49 | #define SAMPLING_RATE_176P4KHZ 176400 |
| 50 | #define SAMPLING_RATE_352P8KHZ 352800 |
| 51 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 52 | #define RX_MACRO_MAX_OFFSET 0x1000 |
| 53 | |
| 54 | #define RX_MACRO_MAX_DMA_CH_PER_PORT 2 |
| 55 | #define RX_SWR_STRING_LEN 80 |
| 56 | #define RX_MACRO_CHILD_DEVICES_MAX 3 |
| 57 | |
| 58 | #define RX_MACRO_INTERP_MUX_NUM_INPUTS 3 |
| 59 | #define RX_MACRO_SIDETONE_IIR_COEFF_MAX 5 |
| 60 | |
| 61 | #define STRING(name) #name |
| 62 | #define RX_MACRO_DAPM_ENUM(name, reg, offset, text) \ |
| 63 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 64 | static const struct snd_kcontrol_new name##_mux = \ |
| 65 | SOC_DAPM_ENUM(STRING(name), name##_enum) |
| 66 | |
| 67 | #define RX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \ |
| 68 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 69 | static const struct snd_kcontrol_new name##_mux = \ |
| 70 | SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname) |
| 71 | |
| 72 | #define RX_MACRO_DAPM_MUX(name, shift, kctl) \ |
| 73 | SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux) |
| 74 | |
| 75 | #define RX_MACRO_RX_PATH_OFFSET 0x80 |
| 76 | #define RX_MACRO_COMP_OFFSET 0x40 |
| 77 | |
| 78 | enum { |
| 79 | INTERP_HPHL, |
| 80 | INTERP_HPHR, |
| 81 | INTERP_AUX, |
| 82 | INTERP_MAX |
| 83 | }; |
| 84 | |
| 85 | enum { |
| 86 | RX_MACRO_RX0, |
| 87 | RX_MACRO_RX1, |
| 88 | RX_MACRO_RX2, |
| 89 | RX_MACRO_RX3, |
| 90 | RX_MACRO_RX4, |
| 91 | RX_MACRO_RX5, |
| 92 | RX_MACRO_PORTS_MAX |
| 93 | }; |
| 94 | |
| 95 | enum { |
| 96 | RX_MACRO_COMP1, /* HPH_L */ |
| 97 | RX_MACRO_COMP2, /* HPH_R */ |
| 98 | RX_MACRO_COMP_MAX |
| 99 | }; |
| 100 | |
| 101 | enum { |
| 102 | INTn_1_INP_SEL_ZERO = 0, |
| 103 | INTn_1_INP_SEL_DEC0, |
| 104 | INTn_1_INP_SEL_DEC1, |
| 105 | INTn_1_INP_SEL_IIR0, |
| 106 | INTn_1_INP_SEL_IIR1, |
| 107 | INTn_1_INP_SEL_RX0, |
| 108 | INTn_1_INP_SEL_RX1, |
| 109 | INTn_1_INP_SEL_RX2, |
| 110 | INTn_1_INP_SEL_RX3, |
| 111 | INTn_1_INP_SEL_RX4, |
| 112 | INTn_1_INP_SEL_RX5, |
| 113 | }; |
| 114 | |
| 115 | enum { |
| 116 | INTn_2_INP_SEL_ZERO = 0, |
| 117 | INTn_2_INP_SEL_RX0, |
| 118 | INTn_2_INP_SEL_RX1, |
| 119 | INTn_2_INP_SEL_RX2, |
| 120 | INTn_2_INP_SEL_RX3, |
| 121 | INTn_2_INP_SEL_RX4, |
| 122 | INTn_2_INP_SEL_RX5, |
| 123 | }; |
| 124 | |
| 125 | enum { |
| 126 | INTERP_MAIN_PATH, |
| 127 | INTERP_MIX_PATH, |
| 128 | }; |
| 129 | |
| 130 | /* Codec supports 2 IIR filters */ |
| 131 | enum { |
| 132 | IIR0 = 0, |
| 133 | IIR1, |
| 134 | IIR_MAX, |
| 135 | }; |
| 136 | |
| 137 | /* Each IIR has 5 Filter Stages */ |
| 138 | enum { |
| 139 | BAND1 = 0, |
| 140 | BAND2, |
| 141 | BAND3, |
| 142 | BAND4, |
| 143 | BAND5, |
| 144 | BAND_MAX, |
| 145 | }; |
| 146 | |
| 147 | struct rx_macro_idle_detect_config { |
| 148 | u8 hph_idle_thr; |
| 149 | u8 hph_idle_detect_en; |
| 150 | }; |
| 151 | |
| 152 | struct interp_sample_rate { |
| 153 | int sample_rate; |
| 154 | int rate_val; |
| 155 | }; |
| 156 | |
| 157 | static struct interp_sample_rate sr_val_tbl[] = { |
| 158 | {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, |
| 159 | {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA}, |
| 160 | {176400, 0xB}, {352800, 0xC}, |
| 161 | }; |
| 162 | |
| 163 | static int rx_macro_hw_params(struct snd_pcm_substream *substream, |
| 164 | struct snd_pcm_hw_params *params, |
| 165 | struct snd_soc_dai *dai); |
| 166 | static int rx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 167 | unsigned int *tx_num, unsigned int *tx_slot, |
| 168 | unsigned int *rx_num, unsigned int *rx_slot); |
| 169 | static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, |
| 170 | struct snd_ctl_elem_value *ucontrol); |
| 171 | static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, |
| 172 | struct snd_ctl_elem_value *ucontrol); |
| 173 | static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, |
| 174 | struct snd_ctl_elem_value *ucontrol); |
| 175 | static int rx_macro_enable_interp_clk(struct snd_soc_codec *codec, |
| 176 | int event, int interp_idx); |
| 177 | |
| 178 | /* Hold instance to soundwire platform device */ |
| 179 | struct rx_swr_ctrl_data { |
| 180 | struct platform_device *rx_swr_pdev; |
| 181 | }; |
| 182 | |
| 183 | struct rx_swr_ctrl_platform_data { |
| 184 | void *handle; /* holds codec private data */ |
| 185 | int (*read)(void *handle, int reg); |
| 186 | int (*write)(void *handle, int reg, int val); |
| 187 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 188 | int (*clk)(void *handle, bool enable); |
| 189 | int (*handle_irq)(void *handle, |
| 190 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 191 | void *data), |
| 192 | void *swrm_handle, |
| 193 | int action); |
| 194 | }; |
| 195 | |
| 196 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 197 | RX_MACRO_AIF_INVALID = 0, |
| 198 | RX_MACRO_AIF1_PB, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 199 | RX_MACRO_AIF2_PB, |
| 200 | RX_MACRO_AIF3_PB, |
| 201 | RX_MACRO_AIF4_PB, |
| 202 | RX_MACRO_MAX_DAIS, |
| 203 | }; |
| 204 | |
| 205 | enum { |
| 206 | RX_MACRO_AIF1_CAP = 0, |
| 207 | RX_MACRO_AIF2_CAP, |
| 208 | RX_MACRO_AIF3_CAP, |
| 209 | RX_MACRO_MAX_AIF_CAP_DAIS |
| 210 | }; |
| 211 | /* |
| 212 | * @dev: rx macro device pointer |
| 213 | * @comp_enabled: compander enable mixer value set |
| 214 | * @prim_int_users: Users of interpolator |
| 215 | * @rx_mclk_users: RX MCLK users count |
| 216 | * @vi_feed_value: VI sense mask |
| 217 | * @swr_clk_lock: to lock swr master clock operations |
| 218 | * @swr_ctrl_data: SoundWire data structure |
| 219 | * @swr_plat_data: Soundwire platform data |
| 220 | * @rx_macro_add_child_devices_work: work for adding child devices |
| 221 | * @rx_swr_gpio_p: used by pinctrl API |
| 222 | * @rx_core_clk: MCLK for rx macro |
| 223 | * @rx_npl_clk: NPL clock for RX soundwire |
| 224 | * @codec: codec handle |
| 225 | */ |
| 226 | struct rx_macro_priv { |
| 227 | struct device *dev; |
| 228 | int comp_enabled[RX_MACRO_COMP_MAX]; |
| 229 | /* Main path clock users count */ |
| 230 | int main_clk_users[INTERP_MAX]; |
| 231 | int rx_port_value[RX_MACRO_PORTS_MAX]; |
| 232 | u16 prim_int_users[INTERP_MAX]; |
| 233 | int rx_mclk_users; |
| 234 | int swr_clk_users; |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 235 | int clsh_users; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 236 | int rx_mclk_cnt; |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 237 | bool is_native_on; |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 238 | bool is_ear_mode_on; |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 239 | u16 mclk_mux; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 240 | struct mutex mclk_lock; |
| 241 | struct mutex swr_clk_lock; |
| 242 | struct rx_swr_ctrl_data *swr_ctrl_data; |
| 243 | struct rx_swr_ctrl_platform_data swr_plat_data; |
| 244 | struct work_struct rx_macro_add_child_devices_work; |
| 245 | struct device_node *rx_swr_gpio_p; |
| 246 | struct clk *rx_core_clk; |
| 247 | struct clk *rx_npl_clk; |
| 248 | struct snd_soc_codec *codec; |
| 249 | unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; |
| 250 | unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; |
| 251 | u16 bit_width[RX_MACRO_MAX_DAIS]; |
| 252 | char __iomem *rx_io_base; |
| 253 | char __iomem *rx_mclk_mode_muxsel; |
| 254 | struct rx_macro_idle_detect_config idle_det_cfg; |
| 255 | u8 sidetone_coeff_array[IIR_MAX][BAND_MAX] |
| 256 | [RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4]; |
| 257 | |
| 258 | struct platform_device *pdev_child_devices |
| 259 | [RX_MACRO_CHILD_DEVICES_MAX]; |
| 260 | int child_count; |
| 261 | }; |
| 262 | |
| 263 | static struct snd_soc_dai_driver rx_macro_dai[]; |
| 264 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 265 | |
| 266 | static const char * const rx_int_mix_mux_text[] = { |
| 267 | "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" |
| 268 | }; |
| 269 | |
| 270 | static const char * const rx_prim_mix_text[] = { |
| 271 | "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", |
| 272 | "RX3", "RX4", "RX5" |
| 273 | }; |
| 274 | |
| 275 | static const char * const rx_sidetone_mix_text[] = { |
| 276 | "ZERO", "SRC0", "SRC1", "SRC_SUM" |
| 277 | }; |
| 278 | |
| 279 | static const char * const rx_echo_mux_text[] = { |
| 280 | "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2" |
| 281 | }; |
| 282 | |
| 283 | static const char * const iir_inp_mux_text[] = { |
| 284 | "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", |
| 285 | "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" |
| 286 | }; |
| 287 | |
| 288 | static const char * const rx_int_dem_inp_mux_text[] = { |
| 289 | "NORMAL_DSM_OUT", "CLSH_DSM_OUT", |
| 290 | }; |
| 291 | |
| 292 | static const char * const rx_int0_1_interp_mux_text[] = { |
| 293 | "ZERO", "RX INT0_1 MIX1", |
| 294 | }; |
| 295 | |
| 296 | static const char * const rx_int1_1_interp_mux_text[] = { |
| 297 | "ZERO", "RX INT1_1 MIX1", |
| 298 | }; |
| 299 | |
| 300 | static const char * const rx_int2_1_interp_mux_text[] = { |
| 301 | "ZERO", "RX INT2_1 MIX1", |
| 302 | }; |
| 303 | |
| 304 | static const char * const rx_int0_2_interp_mux_text[] = { |
| 305 | "ZERO", "RX INT0_2 MUX", |
| 306 | }; |
| 307 | |
| 308 | static const char * const rx_int1_2_interp_mux_text[] = { |
| 309 | "ZERO", "RX INT1_2 MUX", |
| 310 | }; |
| 311 | |
| 312 | static const char * const rx_int2_2_interp_mux_text[] = { |
| 313 | "ZERO", "RX INT2_2 MUX", |
| 314 | }; |
| 315 | |
| 316 | static const char *const rx_macro_mux_text[] = { |
| 317 | "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB" |
| 318 | }; |
| 319 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 320 | static const char *const rx_macro_ear_mode_text[] = {"OFF", "ON"}; |
| 321 | static const struct soc_enum rx_macro_ear_mode_enum = |
| 322 | SOC_ENUM_SINGLE_EXT(2, rx_macro_ear_mode_text); |
| 323 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 324 | RX_MACRO_DAPM_ENUM(rx_int0_2, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, |
| 325 | rx_int_mix_mux_text); |
| 326 | RX_MACRO_DAPM_ENUM(rx_int1_2, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, |
| 327 | rx_int_mix_mux_text); |
| 328 | RX_MACRO_DAPM_ENUM(rx_int2_2, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, |
| 329 | rx_int_mix_mux_text); |
| 330 | |
| 331 | |
| 332 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, |
| 333 | rx_prim_mix_text); |
| 334 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, |
| 335 | rx_prim_mix_text); |
| 336 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, |
| 337 | rx_prim_mix_text); |
| 338 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, |
| 339 | rx_prim_mix_text); |
| 340 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, |
| 341 | rx_prim_mix_text); |
| 342 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, |
| 343 | rx_prim_mix_text); |
| 344 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, |
| 345 | rx_prim_mix_text); |
| 346 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, |
| 347 | rx_prim_mix_text); |
| 348 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, |
| 349 | rx_prim_mix_text); |
| 350 | |
| 351 | RX_MACRO_DAPM_ENUM(rx_int0_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, |
| 352 | rx_sidetone_mix_text); |
| 353 | RX_MACRO_DAPM_ENUM(rx_int1_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, |
| 354 | rx_sidetone_mix_text); |
| 355 | RX_MACRO_DAPM_ENUM(rx_int2_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, |
| 356 | rx_sidetone_mix_text); |
| 357 | |
| 358 | RX_MACRO_DAPM_ENUM(rx_mix_tx0, BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 4, |
| 359 | rx_echo_mux_text); |
| 360 | RX_MACRO_DAPM_ENUM(rx_mix_tx1, BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 0, |
| 361 | rx_echo_mux_text); |
| 362 | RX_MACRO_DAPM_ENUM(rx_mix_tx2, BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 0, |
| 363 | rx_echo_mux_text); |
| 364 | |
| 365 | RX_MACRO_DAPM_ENUM(iir0_inp0, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, |
| 366 | iir_inp_mux_text); |
| 367 | RX_MACRO_DAPM_ENUM(iir0_inp1, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, |
| 368 | iir_inp_mux_text); |
| 369 | RX_MACRO_DAPM_ENUM(iir0_inp2, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, |
| 370 | iir_inp_mux_text); |
| 371 | RX_MACRO_DAPM_ENUM(iir0_inp3, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, |
| 372 | iir_inp_mux_text); |
| 373 | RX_MACRO_DAPM_ENUM(iir1_inp0, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, |
| 374 | iir_inp_mux_text); |
| 375 | RX_MACRO_DAPM_ENUM(iir1_inp1, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, |
| 376 | iir_inp_mux_text); |
| 377 | RX_MACRO_DAPM_ENUM(iir1_inp2, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, |
| 378 | iir_inp_mux_text); |
| 379 | RX_MACRO_DAPM_ENUM(iir1_inp3, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, |
| 380 | iir_inp_mux_text); |
| 381 | |
| 382 | RX_MACRO_DAPM_ENUM(rx_int0_1_interp, SND_SOC_NOPM, 0, |
| 383 | rx_int0_1_interp_mux_text); |
| 384 | RX_MACRO_DAPM_ENUM(rx_int1_1_interp, SND_SOC_NOPM, 0, |
| 385 | rx_int1_1_interp_mux_text); |
| 386 | RX_MACRO_DAPM_ENUM(rx_int2_1_interp, SND_SOC_NOPM, 0, |
| 387 | rx_int2_1_interp_mux_text); |
| 388 | |
| 389 | RX_MACRO_DAPM_ENUM(rx_int0_2_interp, SND_SOC_NOPM, 0, |
| 390 | rx_int0_2_interp_mux_text); |
| 391 | RX_MACRO_DAPM_ENUM(rx_int1_2_interp, SND_SOC_NOPM, 0, |
| 392 | rx_int1_2_interp_mux_text); |
| 393 | RX_MACRO_DAPM_ENUM(rx_int2_2_interp, SND_SOC_NOPM, 0, |
| 394 | rx_int2_2_interp_mux_text); |
| 395 | |
| 396 | RX_MACRO_DAPM_ENUM_EXT(rx_int0_dem_inp, BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0, |
| 397 | rx_int_dem_inp_mux_text, snd_soc_dapm_get_enum_double, |
| 398 | rx_macro_int_dem_inp_mux_put); |
| 399 | RX_MACRO_DAPM_ENUM_EXT(rx_int1_dem_inp, BOLERO_CDC_RX_RX1_RX_PATH_CFG1, 0, |
| 400 | rx_int_dem_inp_mux_text, snd_soc_dapm_get_enum_double, |
| 401 | rx_macro_int_dem_inp_mux_put); |
| 402 | |
| 403 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx0, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 404 | rx_macro_mux_get, rx_macro_mux_put); |
| 405 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx1, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 406 | rx_macro_mux_get, rx_macro_mux_put); |
| 407 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx2, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 408 | rx_macro_mux_get, rx_macro_mux_put); |
| 409 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx3, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 410 | rx_macro_mux_get, rx_macro_mux_put); |
| 411 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx4, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 412 | rx_macro_mux_get, rx_macro_mux_put); |
| 413 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx5, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 414 | rx_macro_mux_get, rx_macro_mux_put); |
| 415 | |
| 416 | static struct snd_soc_dai_ops rx_macro_dai_ops = { |
| 417 | .hw_params = rx_macro_hw_params, |
| 418 | .get_channel_map = rx_macro_get_channel_map, |
| 419 | }; |
| 420 | |
| 421 | static struct snd_soc_dai_driver rx_macro_dai[] = { |
| 422 | { |
| 423 | .name = "rx_macro_rx1", |
| 424 | .id = RX_MACRO_AIF1_PB, |
| 425 | .playback = { |
| 426 | .stream_name = "RX_MACRO_AIF1 Playback", |
| 427 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 428 | .formats = RX_MACRO_FORMATS, |
| 429 | .rate_max = 384000, |
| 430 | .rate_min = 8000, |
| 431 | .channels_min = 1, |
| 432 | .channels_max = 2, |
| 433 | }, |
| 434 | .ops = &rx_macro_dai_ops, |
| 435 | }, |
| 436 | { |
| 437 | .name = "rx_macro_rx2", |
| 438 | .id = RX_MACRO_AIF2_PB, |
| 439 | .playback = { |
| 440 | .stream_name = "RX_MACRO_AIF2 Playback", |
| 441 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 442 | .formats = RX_MACRO_FORMATS, |
| 443 | .rate_max = 384000, |
| 444 | .rate_min = 8000, |
| 445 | .channels_min = 1, |
| 446 | .channels_max = 2, |
| 447 | }, |
| 448 | .ops = &rx_macro_dai_ops, |
| 449 | }, |
| 450 | { |
| 451 | .name = "rx_macro_rx3", |
| 452 | .id = RX_MACRO_AIF3_PB, |
| 453 | .playback = { |
| 454 | .stream_name = "RX_MACRO_AIF3 Playback", |
| 455 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 456 | .formats = RX_MACRO_FORMATS, |
| 457 | .rate_max = 384000, |
| 458 | .rate_min = 8000, |
| 459 | .channels_min = 1, |
| 460 | .channels_max = 2, |
| 461 | }, |
| 462 | .ops = &rx_macro_dai_ops, |
| 463 | }, |
| 464 | { |
| 465 | .name = "rx_macro_rx4", |
| 466 | .id = RX_MACRO_AIF4_PB, |
| 467 | .playback = { |
| 468 | .stream_name = "RX_MACRO_AIF4 Playback", |
| 469 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 470 | .formats = RX_MACRO_FORMATS, |
| 471 | .rate_max = 384000, |
| 472 | .rate_min = 8000, |
| 473 | .channels_min = 1, |
| 474 | .channels_max = 2, |
| 475 | }, |
| 476 | .ops = &rx_macro_dai_ops, |
| 477 | }, |
| 478 | }; |
| 479 | |
| 480 | static bool rx_macro_get_data(struct snd_soc_codec *codec, |
| 481 | struct device **rx_dev, |
| 482 | struct rx_macro_priv **rx_priv, |
| 483 | const char *func_name) |
| 484 | { |
| 485 | *rx_dev = bolero_get_device_ptr(codec->dev, RX_MACRO); |
| 486 | |
| 487 | if (!(*rx_dev)) { |
| 488 | dev_err(codec->dev, |
| 489 | "%s: null device for macro!\n", func_name); |
| 490 | return false; |
| 491 | } |
| 492 | |
| 493 | *rx_priv = dev_get_drvdata((*rx_dev)); |
| 494 | if (!(*rx_priv)) { |
| 495 | dev_err(codec->dev, |
| 496 | "%s: priv is null for macro!\n", func_name); |
| 497 | return false; |
| 498 | } |
| 499 | |
| 500 | if (!(*rx_priv)->codec) { |
| 501 | dev_err(codec->dev, |
| 502 | "%s: tx_priv codec is not initialized!\n", func_name); |
| 503 | return false; |
| 504 | } |
| 505 | |
| 506 | return true; |
| 507 | } |
| 508 | |
| 509 | static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, |
| 510 | struct snd_ctl_elem_value *ucontrol) |
| 511 | { |
| 512 | struct snd_soc_dapm_widget *widget = |
| 513 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 514 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 515 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 516 | unsigned int val = 0; |
| 517 | unsigned short look_ahead_dly_reg = |
| 518 | BOLERO_CDC_RX_RX0_RX_PATH_CFG0; |
| 519 | |
| 520 | val = ucontrol->value.enumerated.item[0]; |
| 521 | if (val >= e->items) |
| 522 | return -EINVAL; |
| 523 | |
| 524 | dev_dbg(codec->dev, "%s: wname: %s, val: 0x%x\n", __func__, |
| 525 | widget->name, val); |
| 526 | |
| 527 | if (e->reg == BOLERO_CDC_RX_RX0_RX_PATH_CFG1) |
| 528 | look_ahead_dly_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0; |
| 529 | else if (e->reg == BOLERO_CDC_RX_RX1_RX_PATH_CFG1) |
| 530 | look_ahead_dly_reg = BOLERO_CDC_RX_RX1_RX_PATH_CFG0; |
| 531 | |
| 532 | /* Set Look Ahead Delay */ |
| 533 | snd_soc_update_bits(codec, look_ahead_dly_reg, |
| 534 | 0x08, (val ? 0x08 : 0x00)); |
| 535 | /* Set DEM INP Select */ |
| 536 | return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 537 | } |
| 538 | |
| 539 | static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, |
| 540 | u8 rate_reg_val, |
| 541 | u32 sample_rate) |
| 542 | { |
| 543 | u8 int_1_mix1_inp = 0; |
| 544 | u32 j = 0, port = 0; |
| 545 | u16 int_mux_cfg0 = 0, int_mux_cfg1 = 0; |
| 546 | u16 int_fs_reg = 0; |
| 547 | u8 int_mux_cfg0_val = 0, int_mux_cfg1_val = 0; |
| 548 | u8 inp0_sel = 0, inp1_sel = 0, inp2_sel = 0; |
| 549 | struct snd_soc_codec *codec = dai->codec; |
| 550 | struct device *rx_dev = NULL; |
| 551 | struct rx_macro_priv *rx_priv = NULL; |
| 552 | |
| 553 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 554 | return -EINVAL; |
| 555 | |
| 556 | for_each_set_bit(port, &rx_priv->active_ch_mask[dai->id], |
| 557 | RX_MACRO_PORTS_MAX) { |
| 558 | int_1_mix1_inp = port; |
| 559 | if ((int_1_mix1_inp < RX_MACRO_RX0) || |
| 560 | (int_1_mix1_inp > RX_MACRO_PORTS_MAX)) { |
| 561 | pr_err("%s: Invalid RX port, Dai ID is %d\n", |
| 562 | __func__, dai->id); |
| 563 | return -EINVAL; |
| 564 | } |
| 565 | |
| 566 | int_mux_cfg0 = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0; |
| 567 | |
| 568 | /* |
| 569 | * Loop through all interpolator MUX inputs and find out |
| 570 | * to which interpolator input, the rx port |
| 571 | * is connected |
| 572 | */ |
| 573 | for (j = 0; j < INTERP_MAX; j++) { |
| 574 | int_mux_cfg1 = int_mux_cfg0 + 4; |
| 575 | |
| 576 | int_mux_cfg0_val = snd_soc_read(codec, int_mux_cfg0); |
| 577 | int_mux_cfg1_val = snd_soc_read(codec, int_mux_cfg1); |
| 578 | inp0_sel = int_mux_cfg0_val & 0x07; |
| 579 | inp1_sel = (int_mux_cfg0_val >> 4) & 0x038; |
| 580 | inp2_sel = (int_mux_cfg1_val >> 4) & 0x038; |
| 581 | if ((inp0_sel == int_1_mix1_inp) || |
| 582 | (inp1_sel == int_1_mix1_inp) || |
| 583 | (inp2_sel == int_1_mix1_inp)) { |
| 584 | int_fs_reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + |
| 585 | 0x80 * j; |
| 586 | pr_debug("%s: AIF_PB DAI(%d) connected to INT%u_1\n", |
| 587 | __func__, dai->id, j); |
| 588 | pr_debug("%s: set INT%u_1 sample rate to %u\n", |
| 589 | __func__, j, sample_rate); |
| 590 | /* sample_rate is in Hz */ |
| 591 | snd_soc_update_bits(codec, int_fs_reg, |
| 592 | 0x0F, rate_reg_val); |
| 593 | } |
| 594 | int_mux_cfg0 += 8; |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, |
| 602 | u8 rate_reg_val, |
| 603 | u32 sample_rate) |
| 604 | { |
| 605 | u8 int_2_inp = 0; |
| 606 | u32 j = 0, port = 0; |
| 607 | u16 int_mux_cfg1 = 0, int_fs_reg = 0; |
| 608 | u8 int_mux_cfg1_val = 0; |
| 609 | struct snd_soc_codec *codec = dai->codec; |
| 610 | struct device *rx_dev = NULL; |
| 611 | struct rx_macro_priv *rx_priv = NULL; |
| 612 | |
| 613 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 614 | return -EINVAL; |
| 615 | |
| 616 | for_each_set_bit(port, &rx_priv->active_ch_mask[dai->id], |
| 617 | RX_MACRO_PORTS_MAX) { |
| 618 | int_2_inp = port; |
| 619 | if ((int_2_inp < RX_MACRO_RX0) || |
| 620 | (int_2_inp > RX_MACRO_PORTS_MAX)) { |
| 621 | pr_err("%s: Invalid RX port, Dai ID is %d\n", |
| 622 | __func__, dai->id); |
| 623 | return -EINVAL; |
| 624 | } |
| 625 | |
| 626 | int_mux_cfg1 = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1; |
| 627 | for (j = 0; j < INTERP_MAX; j++) { |
| 628 | int_mux_cfg1_val = snd_soc_read(codec, int_mux_cfg1) & |
| 629 | 0x07; |
| 630 | if (int_mux_cfg1_val == int_2_inp) { |
| 631 | int_fs_reg = BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL + |
| 632 | 0x80 * j; |
| 633 | pr_debug("%s: AIF_PB DAI(%d) connected to INT%u_2\n", |
| 634 | __func__, dai->id, j); |
| 635 | pr_debug("%s: set INT%u_2 sample rate to %u\n", |
| 636 | __func__, j, sample_rate); |
| 637 | snd_soc_update_bits(codec, int_fs_reg, |
| 638 | 0x0F, rate_reg_val); |
| 639 | } |
| 640 | int_mux_cfg1 += 8; |
| 641 | } |
| 642 | } |
| 643 | return 0; |
| 644 | } |
| 645 | |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 646 | static bool rx_macro_is_fractional_sample_rate(u32 sample_rate) |
| 647 | { |
| 648 | switch (sample_rate) { |
| 649 | case SAMPLING_RATE_44P1KHZ: |
| 650 | case SAMPLING_RATE_88P2KHZ: |
| 651 | case SAMPLING_RATE_176P4KHZ: |
| 652 | case SAMPLING_RATE_352P8KHZ: |
| 653 | return true; |
| 654 | default: |
| 655 | return false; |
| 656 | } |
| 657 | return false; |
| 658 | } |
| 659 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 660 | static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, |
| 661 | u32 sample_rate) |
| 662 | { |
| 663 | struct snd_soc_codec *codec = dai->codec; |
| 664 | int rate_val = 0; |
| 665 | int i = 0, ret = 0; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 666 | struct device *rx_dev = NULL; |
| 667 | struct rx_macro_priv *rx_priv = NULL; |
| 668 | |
| 669 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 670 | return -EINVAL; |
| 671 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 672 | |
| 673 | for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { |
| 674 | if (sample_rate == sr_val_tbl[i].sample_rate) { |
| 675 | rate_val = sr_val_tbl[i].rate_val; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 676 | if (rx_macro_is_fractional_sample_rate(sample_rate)) |
| 677 | rx_priv->is_native_on = true; |
| 678 | else |
| 679 | rx_priv->is_native_on = false; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 680 | break; |
| 681 | } |
| 682 | } |
| 683 | if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { |
| 684 | dev_err(codec->dev, "%s: Unsupported sample rate: %d\n", |
| 685 | __func__, sample_rate); |
| 686 | return -EINVAL; |
| 687 | } |
| 688 | |
| 689 | ret = rx_macro_set_prim_interpolator_rate(dai, (u8)rate_val, sample_rate); |
| 690 | if (ret) |
| 691 | return ret; |
| 692 | ret = rx_macro_set_mix_interpolator_rate(dai, (u8)rate_val, sample_rate); |
| 693 | if (ret) |
| 694 | return ret; |
| 695 | |
| 696 | return ret; |
| 697 | } |
| 698 | |
| 699 | static int rx_macro_hw_params(struct snd_pcm_substream *substream, |
| 700 | struct snd_pcm_hw_params *params, |
| 701 | struct snd_soc_dai *dai) |
| 702 | { |
| 703 | struct snd_soc_codec *codec = dai->codec; |
| 704 | int ret = 0; |
| 705 | struct device *rx_dev = NULL; |
| 706 | struct rx_macro_priv *rx_priv = NULL; |
| 707 | |
| 708 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 709 | return -EINVAL; |
| 710 | |
| 711 | dev_dbg(codec->dev, |
| 712 | "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 713 | dai->name, dai->id, params_rate(params), |
| 714 | params_channels(params)); |
| 715 | |
| 716 | switch (substream->stream) { |
| 717 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 718 | ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); |
| 719 | if (ret) { |
| 720 | pr_err("%s: cannot set sample rate: %u\n", |
| 721 | __func__, params_rate(params)); |
| 722 | return ret; |
| 723 | } |
| 724 | rx_priv->bit_width[dai->id] = params_width(params); |
| 725 | break; |
| 726 | case SNDRV_PCM_STREAM_CAPTURE: |
| 727 | default: |
| 728 | break; |
| 729 | } |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | static int rx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 734 | unsigned int *tx_num, unsigned int *tx_slot, |
| 735 | unsigned int *rx_num, unsigned int *rx_slot) |
| 736 | { |
| 737 | struct snd_soc_codec *codec = dai->codec; |
| 738 | struct device *rx_dev = NULL; |
| 739 | struct rx_macro_priv *rx_priv = NULL; |
| 740 | unsigned int temp = 0, ch_mask = 0; |
| 741 | u16 i = 0; |
| 742 | |
| 743 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 744 | return -EINVAL; |
| 745 | |
| 746 | switch (dai->id) { |
| 747 | case RX_MACRO_AIF1_PB: |
| 748 | case RX_MACRO_AIF2_PB: |
| 749 | case RX_MACRO_AIF3_PB: |
| 750 | case RX_MACRO_AIF4_PB: |
| 751 | for_each_set_bit(temp, &rx_priv->active_ch_mask[dai->id], |
| 752 | RX_MACRO_PORTS_MAX) { |
| 753 | ch_mask |= (1 << i); |
| 754 | if (++i == RX_MACRO_MAX_DMA_CH_PER_PORT) |
| 755 | break; |
| 756 | } |
| 757 | *rx_slot = ch_mask; |
| 758 | *rx_num = rx_priv->active_ch_cnt[dai->id]; |
| 759 | break; |
| 760 | default: |
| 761 | dev_err(rx_dev, "%s: Invalid AIF\n", __func__); |
| 762 | break; |
| 763 | } |
| 764 | return 0; |
| 765 | } |
| 766 | |
| 767 | static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, |
| 768 | bool mclk_enable, bool dapm) |
| 769 | { |
| 770 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 771 | int ret = 0, mclk_mux = MCLK_MUX0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 772 | |
| 773 | dev_dbg(rx_priv->dev, "%s: mclk_enable = %u, dapm = %d clk_users= %d\n", |
| 774 | __func__, mclk_enable, dapm, rx_priv->rx_mclk_users); |
| 775 | |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 776 | if (rx_priv->is_native_on) |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 777 | mclk_mux = MCLK_MUX1; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 778 | mutex_lock(&rx_priv->mclk_lock); |
| 779 | if (mclk_enable) { |
| 780 | if (rx_priv->rx_mclk_users == 0) { |
| 781 | ret = bolero_request_clock(rx_priv->dev, |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 782 | RX_MACRO, mclk_mux, true); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 783 | if (ret < 0) { |
| 784 | dev_err(rx_priv->dev, |
| 785 | "%s: rx request clock enable failed\n", |
| 786 | __func__); |
| 787 | goto exit; |
| 788 | } |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 789 | rx_priv->mclk_mux = mclk_mux; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 790 | regcache_mark_dirty(regmap); |
| 791 | regcache_sync_region(regmap, |
| 792 | RX_START_OFFSET, |
| 793 | RX_MAX_OFFSET); |
| 794 | regmap_update_bits(regmap, |
| 795 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 796 | 0x01, 0x01); |
| 797 | regmap_update_bits(regmap, |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 798 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 799 | 0x02, 0x02); |
| 800 | regmap_update_bits(regmap, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 801 | BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 802 | 0x01, 0x01); |
| 803 | } |
| 804 | rx_priv->rx_mclk_users++; |
| 805 | } else { |
| 806 | if (rx_priv->rx_mclk_users <= 0) { |
| 807 | dev_err(rx_priv->dev, "%s: clock already disabled\n", |
| 808 | __func__); |
| 809 | rx_priv->rx_mclk_users = 0; |
| 810 | goto exit; |
| 811 | } |
| 812 | rx_priv->rx_mclk_users--; |
| 813 | if (rx_priv->rx_mclk_users == 0) { |
| 814 | regmap_update_bits(regmap, |
| 815 | BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 816 | 0x01, 0x00); |
| 817 | regmap_update_bits(regmap, |
| 818 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 819 | 0x01, 0x00); |
| 820 | bolero_request_clock(rx_priv->dev, |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 821 | RX_MACRO, mclk_mux, false); |
| 822 | rx_priv->mclk_mux = MCLK_MUX0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 823 | } |
| 824 | } |
| 825 | exit: |
| 826 | mutex_unlock(&rx_priv->mclk_lock); |
| 827 | return ret; |
| 828 | } |
| 829 | |
| 830 | static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 831 | struct snd_kcontrol *kcontrol, int event) |
| 832 | { |
| 833 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 834 | int ret = 0; |
| 835 | struct device *rx_dev = NULL; |
| 836 | struct rx_macro_priv *rx_priv = NULL; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 837 | int mclk_freq = MCLK_FREQ; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 838 | |
| 839 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 840 | return -EINVAL; |
| 841 | |
| 842 | dev_dbg(rx_dev, "%s: event = %d\n", __func__, event); |
| 843 | switch (event) { |
| 844 | case SND_SOC_DAPM_PRE_PMU: |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 845 | /* if swr_clk_users > 0, call device down */ |
| 846 | if (rx_priv->swr_clk_users > 0) { |
| 847 | if ((rx_priv->mclk_mux == MCLK_MUX0 && |
| 848 | rx_priv->is_native_on) || |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 849 | (rx_priv->mclk_mux == MCLK_MUX1 && |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 850 | !rx_priv->is_native_on)) { |
| 851 | swrm_wcd_notify( |
| 852 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 853 | SWR_DEVICE_DOWN, NULL); |
| 854 | } |
| 855 | } |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 856 | if (rx_priv->is_native_on) |
| 857 | mclk_freq = MCLK_FREQ_NATIVE; |
| 858 | swrm_wcd_notify( |
| 859 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 860 | SWR_CLK_FREQ, &mclk_freq); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 861 | ret = rx_macro_mclk_enable(rx_priv, 1, true); |
| 862 | break; |
| 863 | case SND_SOC_DAPM_POST_PMD: |
| 864 | ret = rx_macro_mclk_enable(rx_priv, 0, true); |
| 865 | break; |
| 866 | default: |
| 867 | dev_err(rx_priv->dev, |
| 868 | "%s: invalid DAPM event %d\n", __func__, event); |
| 869 | ret = -EINVAL; |
| 870 | } |
| 871 | return ret; |
| 872 | } |
| 873 | |
| 874 | static int rx_macro_mclk_ctrl(struct device *dev, bool enable) |
| 875 | { |
| 876 | struct rx_macro_priv *rx_priv = dev_get_drvdata(dev); |
| 877 | int ret = 0; |
| 878 | |
| 879 | if (enable) { |
| 880 | ret = clk_prepare_enable(rx_priv->rx_core_clk); |
| 881 | if (ret < 0) { |
| 882 | dev_err(dev, "%s:rx mclk enable failed\n", __func__); |
| 883 | return ret; |
| 884 | } |
| 885 | ret = clk_prepare_enable(rx_priv->rx_npl_clk); |
| 886 | if (ret < 0) { |
| 887 | clk_disable_unprepare(rx_priv->rx_core_clk); |
| 888 | dev_err(dev, "%s:rx npl_clk enable failed\n", |
| 889 | __func__); |
| 890 | return ret; |
| 891 | } |
| 892 | if (rx_priv->rx_mclk_cnt++ == 0) |
| 893 | iowrite32(0x1, rx_priv->rx_mclk_mode_muxsel); |
| 894 | } else { |
| 895 | if (rx_priv->rx_mclk_cnt <= 0) { |
| 896 | dev_dbg(dev, "%s:rx mclk already disabled\n", __func__); |
| 897 | rx_priv->rx_mclk_cnt = 0; |
| 898 | return 0; |
| 899 | } |
| 900 | if (--rx_priv->rx_mclk_cnt == 0) |
| 901 | iowrite32(0x0, rx_priv->rx_mclk_mode_muxsel); |
| 902 | clk_disable_unprepare(rx_priv->rx_npl_clk); |
| 903 | clk_disable_unprepare(rx_priv->rx_core_clk); |
| 904 | } |
| 905 | |
| 906 | return 0; |
| 907 | } |
| 908 | |
| 909 | static int rx_macro_find_playback_dai_id_for_port(int port_id, |
| 910 | struct rx_macro_priv *rx_priv) |
| 911 | { |
| 912 | int i = 0; |
| 913 | |
| 914 | for (i = RX_MACRO_AIF1_PB; i < RX_MACRO_MAX_DAIS; i++) { |
| 915 | if (test_bit(port_id, &rx_priv->active_ch_mask[i])) |
| 916 | return i; |
| 917 | } |
| 918 | |
| 919 | return -EINVAL; |
| 920 | } |
| 921 | |
| 922 | static int rx_macro_set_idle_detect_thr(struct snd_soc_codec *codec, |
| 923 | struct rx_macro_priv *rx_priv, |
| 924 | int interp, int path_type) |
| 925 | { |
| 926 | int port_id[4] = { 0, 0, 0, 0 }; |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 927 | int *port_ptr = NULL; |
| 928 | int num_ports = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 929 | int bit_width = 0, i = 0; |
| 930 | int mux_reg = 0, mux_reg_val = 0; |
| 931 | int dai_id = 0, idle_thr = 0; |
| 932 | |
| 933 | if ((interp != INTERP_HPHL) && (interp != INTERP_HPHR)) |
| 934 | return 0; |
| 935 | |
| 936 | if (!rx_priv->idle_det_cfg.hph_idle_detect_en) |
| 937 | return 0; |
| 938 | |
| 939 | port_ptr = &port_id[0]; |
| 940 | num_ports = 0; |
| 941 | |
| 942 | /* |
| 943 | * Read interpolator MUX input registers and find |
| 944 | * which cdc_dma port is connected and store the port |
| 945 | * numbers in port_id array. |
| 946 | */ |
| 947 | if (path_type == INTERP_MIX_PATH) { |
| 948 | mux_reg = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1 + |
| 949 | 2 * interp; |
| 950 | mux_reg_val = snd_soc_read(codec, mux_reg) & 0x0f; |
| 951 | |
| 952 | if ((mux_reg_val >= INTn_2_INP_SEL_RX0) && |
| 953 | (mux_reg_val <= INTn_2_INP_SEL_RX5)) { |
| 954 | *port_ptr++ = mux_reg_val - 1; |
| 955 | num_ports++; |
| 956 | } |
| 957 | } |
| 958 | |
| 959 | if (path_type == INTERP_MAIN_PATH) { |
| 960 | mux_reg = BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0 + |
| 961 | 2 * (interp - 1); |
| 962 | mux_reg_val = snd_soc_read(codec, mux_reg) & 0x0f; |
| 963 | i = RX_MACRO_INTERP_MUX_NUM_INPUTS; |
| 964 | |
| 965 | while (i) { |
| 966 | if ((mux_reg_val >= INTn_1_INP_SEL_RX0) && |
| 967 | (mux_reg_val <= INTn_1_INP_SEL_RX5)) { |
| 968 | *port_ptr++ = mux_reg_val - |
| 969 | INTn_1_INP_SEL_RX0; |
| 970 | num_ports++; |
| 971 | } |
| 972 | mux_reg_val = (snd_soc_read(codec, mux_reg) & |
| 973 | 0xf0) >> 4; |
| 974 | mux_reg += 1; |
| 975 | i--; |
| 976 | } |
| 977 | } |
| 978 | |
| 979 | dev_dbg(codec->dev, "%s: num_ports: %d, ports[%d %d %d %d]\n", |
| 980 | __func__, num_ports, port_id[0], port_id[1], |
| 981 | port_id[2], port_id[3]); |
| 982 | |
| 983 | i = 0; |
| 984 | while (num_ports) { |
| 985 | dai_id = rx_macro_find_playback_dai_id_for_port(port_id[i++], |
| 986 | rx_priv); |
| 987 | |
| 988 | if ((dai_id >= 0) && (dai_id < RX_MACRO_MAX_DAIS)) { |
| 989 | dev_dbg(codec->dev, "%s: dai_id: %d bit_width: %d\n", |
| 990 | __func__, dai_id, |
| 991 | rx_priv->bit_width[dai_id]); |
| 992 | |
| 993 | if (rx_priv->bit_width[dai_id] > bit_width) |
| 994 | bit_width = rx_priv->bit_width[dai_id]; |
| 995 | } |
| 996 | num_ports--; |
| 997 | } |
| 998 | |
| 999 | switch (bit_width) { |
| 1000 | case 16: |
| 1001 | idle_thr = 0xff; /* F16 */ |
| 1002 | break; |
| 1003 | case 24: |
| 1004 | case 32: |
| 1005 | idle_thr = 0x03; /* F22 */ |
| 1006 | break; |
| 1007 | default: |
| 1008 | idle_thr = 0x00; |
| 1009 | break; |
| 1010 | } |
| 1011 | |
| 1012 | dev_dbg(codec->dev, "%s: (new) idle_thr: %d, (cur) idle_thr: %d\n", |
| 1013 | __func__, idle_thr, rx_priv->idle_det_cfg.hph_idle_thr); |
| 1014 | |
| 1015 | if ((rx_priv->idle_det_cfg.hph_idle_thr == 0) || |
| 1016 | (idle_thr < rx_priv->idle_det_cfg.hph_idle_thr)) { |
| 1017 | snd_soc_write(codec, BOLERO_CDC_RX_IDLE_DETECT_CFG3, idle_thr); |
| 1018 | rx_priv->idle_det_cfg.hph_idle_thr = idle_thr; |
| 1019 | } |
| 1020 | |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
| 1024 | static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, |
| 1025 | struct snd_kcontrol *kcontrol, int event) |
| 1026 | { |
| 1027 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 1028 | u16 gain_reg = 0, mix_reg = 0; |
| 1029 | struct device *rx_dev = NULL; |
| 1030 | struct rx_macro_priv *rx_priv = NULL; |
| 1031 | |
| 1032 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1033 | return -EINVAL; |
| 1034 | |
| 1035 | if (w->shift >= INTERP_MAX) { |
| 1036 | dev_err(codec->dev, "%s: Invalid Interpolator value %d for name %s\n", |
| 1037 | __func__, w->shift, w->name); |
| 1038 | return -EINVAL; |
| 1039 | } |
| 1040 | |
| 1041 | gain_reg = BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL + |
| 1042 | (w->shift * RX_MACRO_RX_PATH_OFFSET); |
| 1043 | mix_reg = BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL + |
| 1044 | (w->shift * RX_MACRO_RX_PATH_OFFSET); |
| 1045 | |
| 1046 | dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); |
| 1047 | |
| 1048 | switch (event) { |
| 1049 | case SND_SOC_DAPM_PRE_PMU: |
| 1050 | rx_macro_set_idle_detect_thr(codec, rx_priv, w->shift, |
| 1051 | INTERP_MIX_PATH); |
| 1052 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1053 | /* Clk enable */ |
| 1054 | snd_soc_update_bits(codec, mix_reg, 0x20, 0x20); |
| 1055 | break; |
| 1056 | case SND_SOC_DAPM_POST_PMU: |
| 1057 | snd_soc_write(codec, gain_reg, |
| 1058 | snd_soc_read(codec, gain_reg)); |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 1059 | snd_soc_update_bits(codec, mix_reg, 0x10, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1060 | break; |
| 1061 | case SND_SOC_DAPM_POST_PMD: |
| 1062 | /* Clk Disable */ |
| 1063 | snd_soc_update_bits(codec, mix_reg, 0x20, 0x00); |
| 1064 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1065 | /* Reset enable and disable */ |
| 1066 | snd_soc_update_bits(codec, mix_reg, 0x40, 0x40); |
| 1067 | snd_soc_update_bits(codec, mix_reg, 0x40, 0x00); |
| 1068 | break; |
| 1069 | } |
| 1070 | |
| 1071 | return 0; |
| 1072 | } |
| 1073 | |
| 1074 | static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, |
| 1075 | struct snd_kcontrol *kcontrol, |
| 1076 | int event) |
| 1077 | { |
| 1078 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 1079 | u16 gain_reg = 0; |
| 1080 | u16 reg = 0; |
| 1081 | struct device *rx_dev = NULL; |
| 1082 | struct rx_macro_priv *rx_priv = NULL; |
| 1083 | |
| 1084 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1085 | return -EINVAL; |
| 1086 | |
| 1087 | dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); |
| 1088 | |
| 1089 | if (w->shift >= INTERP_MAX) { |
| 1090 | dev_err(codec->dev, "%s: Invalid Interpolator value %d for name %s\n", |
| 1091 | __func__, w->shift, w->name); |
| 1092 | return -EINVAL; |
| 1093 | } |
| 1094 | |
| 1095 | reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + (w->shift * |
| 1096 | RX_MACRO_RX_PATH_OFFSET); |
| 1097 | gain_reg = BOLERO_CDC_RX_RX0_RX_VOL_CTL + (w->shift * |
| 1098 | RX_MACRO_RX_PATH_OFFSET); |
| 1099 | |
| 1100 | switch (event) { |
| 1101 | case SND_SOC_DAPM_PRE_PMU: |
| 1102 | rx_macro_set_idle_detect_thr(codec, rx_priv, w->shift, |
| 1103 | INTERP_MAIN_PATH); |
| 1104 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1105 | break; |
| 1106 | case SND_SOC_DAPM_POST_PMU: |
| 1107 | snd_soc_write(codec, gain_reg, |
| 1108 | snd_soc_read(codec, gain_reg)); |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 1109 | snd_soc_update_bits(codec, reg, 0x10, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1110 | break; |
| 1111 | case SND_SOC_DAPM_POST_PMD: |
| 1112 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1113 | break; |
| 1114 | } |
| 1115 | |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
| 1119 | static int rx_macro_config_compander(struct snd_soc_codec *codec, |
| 1120 | struct rx_macro_priv *rx_priv, |
| 1121 | int interp_n, int event) |
| 1122 | { |
| 1123 | int comp = 0; |
| 1124 | u16 comp_ctl0_reg = 0, rx_path_cfg0_reg = 0; |
| 1125 | |
| 1126 | /* AUX does not have compander */ |
| 1127 | if (interp_n == INTERP_AUX) |
| 1128 | return 0; |
| 1129 | |
| 1130 | comp = interp_n; |
| 1131 | dev_dbg(codec->dev, "%s: event %d compander %d, enabled %d\n", |
| 1132 | __func__, event, comp + 1, rx_priv->comp_enabled[comp]); |
| 1133 | |
| 1134 | if (!rx_priv->comp_enabled[comp]) |
| 1135 | return 0; |
| 1136 | |
| 1137 | comp_ctl0_reg = BOLERO_CDC_RX_COMPANDER0_CTL0 + |
| 1138 | (comp * RX_MACRO_COMP_OFFSET); |
| 1139 | rx_path_cfg0_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0 + |
| 1140 | (comp * RX_MACRO_RX_PATH_OFFSET); |
| 1141 | |
| 1142 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1143 | /* Enable Compander Clock */ |
| 1144 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x01, 0x01); |
| 1145 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x02); |
| 1146 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x00); |
| 1147 | snd_soc_update_bits(codec, rx_path_cfg0_reg, 0x02, 0x02); |
| 1148 | } |
| 1149 | |
| 1150 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1151 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x04, 0x04); |
| 1152 | snd_soc_update_bits(codec, rx_path_cfg0_reg, 0x02, 0x00); |
| 1153 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x02); |
| 1154 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x02, 0x00); |
| 1155 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x01, 0x00); |
| 1156 | snd_soc_update_bits(codec, comp_ctl0_reg, 0x04, 0x00); |
| 1157 | } |
| 1158 | |
| 1159 | return 0; |
| 1160 | } |
| 1161 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1162 | static inline void |
| 1163 | rx_macro_enable_clsh_block(struct rx_macro_priv *rx_priv, bool enable) |
| 1164 | { |
| 1165 | if ((enable && ++rx_priv->clsh_users == 1) || |
| 1166 | (!enable && --rx_priv->clsh_users == 0)) |
| 1167 | snd_soc_update_bits(rx_priv->codec, |
| 1168 | BOLERO_CDC_RX_CLSH_CRC, 0x01, |
| 1169 | (u8) enable); |
| 1170 | if (rx_priv->clsh_users < 0) |
| 1171 | rx_priv->clsh_users = 0; |
| 1172 | dev_dbg(rx_priv->dev, "%s: clsh_users %d, enable %d", __func__, |
| 1173 | rx_priv->clsh_users, enable); |
| 1174 | } |
| 1175 | |
| 1176 | static int rx_macro_config_classh(struct snd_soc_codec *codec, |
| 1177 | struct rx_macro_priv *rx_priv, |
| 1178 | int interp_n, int event) |
| 1179 | { |
| 1180 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1181 | rx_macro_enable_clsh_block(rx_priv, false); |
| 1182 | return 0; |
| 1183 | } |
| 1184 | |
| 1185 | if (!SND_SOC_DAPM_EVENT_ON(event)) |
| 1186 | return 0; |
| 1187 | |
| 1188 | rx_macro_enable_clsh_block(rx_priv, true); |
| 1189 | if (interp_n == INTERP_HPHL || |
| 1190 | interp_n == INTERP_HPHR) { |
| 1191 | /* |
| 1192 | * These K1 values depend on the Headphone Impedance |
| 1193 | * For now it is assumed to be 16 ohm |
| 1194 | */ |
| 1195 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_K1_LSB, |
| 1196 | 0xFF, 0xC0); |
| 1197 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_K1_MSB, |
| 1198 | 0x0F, 0x00); |
| 1199 | } |
| 1200 | switch (interp_n) { |
| 1201 | case INTERP_HPHL: |
| 1202 | if (rx_priv->is_ear_mode_on) |
| 1203 | snd_soc_update_bits(codec, |
| 1204 | BOLERO_CDC_RX_CLSH_HPH_V_PA, |
| 1205 | 0x3F, 0x39); |
| 1206 | else |
| 1207 | snd_soc_update_bits(codec, |
| 1208 | BOLERO_CDC_RX_CLSH_HPH_V_PA, |
| 1209 | 0x3F, 0x1C); |
| 1210 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_DECAY_CTRL, |
| 1211 | 0x07, 0x00); |
| 1212 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX0_RX_PATH_CFG0, |
| 1213 | 0x40, 0x40); |
| 1214 | break; |
| 1215 | case INTERP_HPHR: |
| 1216 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_HPH_V_PA, |
| 1217 | 0x3F, 0x1C); |
| 1218 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_DECAY_CTRL, |
| 1219 | 0x07, 0x00); |
| 1220 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX1_RX_PATH_CFG0, |
| 1221 | 0x40, 0x40); |
| 1222 | break; |
| 1223 | case INTERP_AUX: |
| 1224 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX2_RX_PATH_CFG0, |
| 1225 | 0x10, 0x10); |
| 1226 | break; |
| 1227 | } |
| 1228 | |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1232 | static void rx_macro_hd2_control(struct snd_soc_codec *codec, |
| 1233 | u16 interp_idx, int event) |
| 1234 | { |
| 1235 | u16 hd2_scale_reg = 0; |
| 1236 | u16 hd2_enable_reg = 0; |
| 1237 | |
| 1238 | switch (interp_idx) { |
| 1239 | case INTERP_HPHL: |
| 1240 | hd2_scale_reg = BOLERO_CDC_RX_RX1_RX_PATH_SEC3; |
| 1241 | hd2_enable_reg = BOLERO_CDC_RX_RX1_RX_PATH_CFG0; |
| 1242 | break; |
| 1243 | case INTERP_HPHR: |
| 1244 | hd2_scale_reg = BOLERO_CDC_RX_RX2_RX_PATH_SEC3; |
| 1245 | hd2_enable_reg = BOLERO_CDC_RX_RX2_RX_PATH_CFG0; |
| 1246 | break; |
| 1247 | } |
| 1248 | |
| 1249 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { |
| 1250 | snd_soc_update_bits(codec, hd2_scale_reg, 0x3C, 0x14); |
| 1251 | snd_soc_update_bits(codec, hd2_enable_reg, 0x04, 0x04); |
| 1252 | } |
| 1253 | |
| 1254 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1255 | snd_soc_update_bits(codec, hd2_enable_reg, 0x04, 0x00); |
| 1256 | snd_soc_update_bits(codec, hd2_scale_reg, 0x3C, 0x00); |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, |
| 1261 | struct snd_ctl_elem_value *ucontrol) |
| 1262 | { |
| 1263 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1264 | int comp = ((struct soc_multi_mixer_control *) |
| 1265 | kcontrol->private_value)->shift; |
| 1266 | struct device *rx_dev = NULL; |
| 1267 | struct rx_macro_priv *rx_priv = NULL; |
| 1268 | |
| 1269 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1270 | return -EINVAL; |
| 1271 | |
| 1272 | ucontrol->value.integer.value[0] = rx_priv->comp_enabled[comp]; |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
| 1276 | static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, |
| 1277 | struct snd_ctl_elem_value *ucontrol) |
| 1278 | { |
| 1279 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1280 | int comp = ((struct soc_multi_mixer_control *) |
| 1281 | kcontrol->private_value)->shift; |
| 1282 | int value = ucontrol->value.integer.value[0]; |
| 1283 | struct device *rx_dev = NULL; |
| 1284 | struct rx_macro_priv *rx_priv = NULL; |
| 1285 | |
| 1286 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1287 | return -EINVAL; |
| 1288 | |
| 1289 | dev_dbg(codec->dev, "%s: Compander %d enable current %d, new %d\n", |
| 1290 | __func__, comp + 1, rx_priv->comp_enabled[comp], value); |
| 1291 | rx_priv->comp_enabled[comp] = value; |
| 1292 | |
| 1293 | return 0; |
| 1294 | } |
| 1295 | |
| 1296 | static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, |
| 1297 | struct snd_ctl_elem_value *ucontrol) |
| 1298 | { |
| 1299 | struct snd_soc_dapm_widget *widget = |
| 1300 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 1301 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 1302 | struct device *rx_dev = NULL; |
| 1303 | struct rx_macro_priv *rx_priv = NULL; |
| 1304 | |
| 1305 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1306 | return -EINVAL; |
| 1307 | |
| 1308 | ucontrol->value.integer.value[0] = |
| 1309 | rx_priv->rx_port_value[widget->shift]; |
| 1310 | return 0; |
| 1311 | } |
| 1312 | |
| 1313 | static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, |
| 1314 | struct snd_ctl_elem_value *ucontrol) |
| 1315 | { |
| 1316 | struct snd_soc_dapm_widget *widget = |
| 1317 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 1318 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 1319 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1320 | struct snd_soc_dapm_update *update = NULL; |
| 1321 | u32 rx_port_value = ucontrol->value.integer.value[0]; |
| 1322 | u32 aif_rst = 0; |
| 1323 | struct device *rx_dev = NULL; |
| 1324 | struct rx_macro_priv *rx_priv = NULL; |
| 1325 | |
| 1326 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1327 | return -EINVAL; |
| 1328 | |
| 1329 | aif_rst = rx_priv->rx_port_value[widget->shift]; |
| 1330 | if (!rx_port_value) { |
| 1331 | if (aif_rst == 0) { |
| 1332 | dev_err(rx_dev, "%s:AIF reset already\n", __func__); |
| 1333 | return 0; |
| 1334 | } |
| 1335 | } |
| 1336 | rx_priv->rx_port_value[widget->shift] = rx_port_value; |
| 1337 | |
| 1338 | switch (rx_port_value) { |
| 1339 | case 0: |
| 1340 | clear_bit(widget->shift, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1341 | &rx_priv->active_ch_mask[aif_rst]); |
| 1342 | rx_priv->active_ch_cnt[aif_rst]--; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1343 | break; |
| 1344 | case 1: |
| 1345 | case 2: |
| 1346 | case 3: |
| 1347 | case 4: |
| 1348 | set_bit(widget->shift, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1349 | &rx_priv->active_ch_mask[rx_port_value]); |
| 1350 | rx_priv->active_ch_cnt[rx_port_value]++; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1351 | break; |
| 1352 | default: |
| 1353 | dev_err(codec->dev, |
| 1354 | "%s:Invalid AIF_ID for RX_MACRO MUX\n", __func__); |
| 1355 | goto err; |
| 1356 | } |
| 1357 | |
| 1358 | snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, |
| 1359 | rx_port_value, e, update); |
| 1360 | return 0; |
| 1361 | err: |
| 1362 | return -EINVAL; |
| 1363 | } |
| 1364 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1365 | static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, |
| 1366 | struct snd_ctl_elem_value *ucontrol) |
| 1367 | { |
| 1368 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1369 | struct device *rx_dev = NULL; |
| 1370 | struct rx_macro_priv *rx_priv = NULL; |
| 1371 | |
| 1372 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1373 | return -EINVAL; |
| 1374 | |
| 1375 | ucontrol->value.integer.value[0] = rx_priv->is_ear_mode_on; |
| 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, |
| 1380 | struct snd_ctl_elem_value *ucontrol) |
| 1381 | { |
| 1382 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1383 | struct device *rx_dev = NULL; |
| 1384 | struct rx_macro_priv *rx_priv = NULL; |
| 1385 | |
| 1386 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1387 | return -EINVAL; |
| 1388 | |
| 1389 | rx_priv->is_ear_mode_on = |
| 1390 | (!ucontrol->value.integer.value[0] ? false : true); |
| 1391 | return 0; |
| 1392 | } |
| 1393 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1394 | static void rx_macro_idle_detect_control(struct snd_soc_codec *codec, |
| 1395 | struct rx_macro_priv *rx_priv, |
| 1396 | int interp, int event) |
| 1397 | { |
| 1398 | int reg = 0, mask = 0, val = 0; |
| 1399 | |
| 1400 | if (!rx_priv->idle_det_cfg.hph_idle_detect_en) |
| 1401 | return; |
| 1402 | |
| 1403 | if (interp == INTERP_HPHL) { |
| 1404 | reg = BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL; |
| 1405 | mask = 0x01; |
| 1406 | val = 0x01; |
| 1407 | } |
| 1408 | if (interp == INTERP_HPHR) { |
| 1409 | reg = BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL; |
| 1410 | mask = 0x02; |
| 1411 | val = 0x02; |
| 1412 | } |
| 1413 | |
| 1414 | if (reg && SND_SOC_DAPM_EVENT_ON(event)) |
| 1415 | snd_soc_update_bits(codec, reg, mask, val); |
| 1416 | |
| 1417 | if (reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1418 | snd_soc_update_bits(codec, reg, mask, 0x00); |
| 1419 | rx_priv->idle_det_cfg.hph_idle_thr = 0; |
| 1420 | snd_soc_write(codec, BOLERO_CDC_RX_IDLE_DETECT_CFG3, 0x0); |
| 1421 | } |
| 1422 | } |
| 1423 | |
| 1424 | static void rx_macro_hphdelay_lutbypass(struct snd_soc_codec *codec, |
| 1425 | struct rx_macro_priv *rx_priv, |
| 1426 | u16 interp_idx, int event) |
| 1427 | { |
| 1428 | u8 hph_dly_mask = 0; |
| 1429 | u16 hph_lut_bypass_reg = 0; |
| 1430 | u16 hph_comp_ctrl7 = 0; |
| 1431 | |
| 1432 | switch (interp_idx) { |
| 1433 | case INTERP_HPHL: |
| 1434 | hph_dly_mask = 1; |
| 1435 | hph_lut_bypass_reg = BOLERO_CDC_RX_TOP_HPHL_COMP_LUT; |
| 1436 | hph_comp_ctrl7 = BOLERO_CDC_RX_COMPANDER0_CTL7; |
| 1437 | break; |
| 1438 | case INTERP_HPHR: |
| 1439 | hph_dly_mask = 2; |
| 1440 | hph_lut_bypass_reg = BOLERO_CDC_RX_TOP_HPHR_COMP_LUT; |
| 1441 | hph_comp_ctrl7 = BOLERO_CDC_RX_COMPANDER1_CTL7; |
| 1442 | break; |
| 1443 | default: |
| 1444 | break; |
| 1445 | } |
| 1446 | |
| 1447 | if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) { |
| 1448 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_TEST0, |
| 1449 | hph_dly_mask, 0x0); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1450 | if (interp_idx == INTERP_HPHL) { |
| 1451 | if (rx_priv->is_ear_mode_on) |
| 1452 | snd_soc_update_bits(codec, |
| 1453 | BOLERO_CDC_RX_RX0_RX_PATH_CFG1, |
| 1454 | 0x02, 0x02); |
| 1455 | else |
| 1456 | snd_soc_update_bits(codec, |
| 1457 | hph_lut_bypass_reg, |
| 1458 | 0x80, 0x80); |
| 1459 | } else { |
| 1460 | snd_soc_update_bits(codec, |
| 1461 | hph_lut_bypass_reg, |
| 1462 | 0x80, 0x80); |
| 1463 | } |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1464 | } |
| 1465 | |
| 1466 | if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1467 | snd_soc_update_bits(codec, BOLERO_CDC_RX_CLSH_TEST0, |
| 1468 | hph_dly_mask, hph_dly_mask); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1469 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX0_RX_PATH_CFG1, |
| 1470 | 0x02, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1471 | snd_soc_update_bits(codec, hph_lut_bypass_reg, 0x80, 0x00); |
| 1472 | snd_soc_update_bits(codec, hph_comp_ctrl7, 0x20, 0x0); |
| 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | static int rx_macro_enable_interp_clk(struct snd_soc_codec *codec, |
| 1477 | int event, int interp_idx) |
| 1478 | { |
| 1479 | u16 main_reg = 0; |
| 1480 | struct device *rx_dev = NULL; |
| 1481 | struct rx_macro_priv *rx_priv = NULL; |
| 1482 | |
| 1483 | if (!codec) { |
| 1484 | pr_err("%s: codec is NULL\n", __func__); |
| 1485 | return -EINVAL; |
| 1486 | } |
| 1487 | |
| 1488 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1489 | return -EINVAL; |
| 1490 | |
| 1491 | main_reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + |
| 1492 | (interp_idx * RX_MACRO_RX_PATH_OFFSET); |
| 1493 | |
| 1494 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1495 | if (rx_priv->main_clk_users[interp_idx] == 0) { |
| 1496 | /* Main path PGA mute enable */ |
| 1497 | snd_soc_update_bits(codec, main_reg, 0x10, 0x10); |
| 1498 | /* Clk enable */ |
| 1499 | snd_soc_update_bits(codec, main_reg, 0x20, 0x20); |
| 1500 | rx_macro_idle_detect_control(codec, rx_priv, |
| 1501 | interp_idx, event); |
| 1502 | rx_macro_hd2_control(codec, interp_idx, event); |
| 1503 | rx_macro_hphdelay_lutbypass(codec, rx_priv, interp_idx, |
| 1504 | event); |
| 1505 | rx_macro_config_compander(codec, rx_priv, |
| 1506 | interp_idx, event); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1507 | rx_macro_config_classh(codec, rx_priv, |
| 1508 | interp_idx, event); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1509 | } |
| 1510 | rx_priv->main_clk_users[interp_idx]++; |
| 1511 | } |
| 1512 | |
| 1513 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1514 | rx_priv->main_clk_users[interp_idx]--; |
| 1515 | if (rx_priv->main_clk_users[interp_idx] <= 0) { |
| 1516 | rx_priv->main_clk_users[interp_idx] = 0; |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1517 | rx_macro_config_classh(codec, rx_priv, |
| 1518 | interp_idx, event); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1519 | rx_macro_config_compander(codec, rx_priv, |
| 1520 | interp_idx, event); |
| 1521 | rx_macro_hphdelay_lutbypass(codec, rx_priv, interp_idx, |
| 1522 | event); |
| 1523 | rx_macro_hd2_control(codec, interp_idx, event); |
| 1524 | rx_macro_idle_detect_control(codec, rx_priv, |
| 1525 | interp_idx, event); |
| 1526 | /* Clk Disable */ |
| 1527 | snd_soc_update_bits(codec, main_reg, 0x20, 0x00); |
| 1528 | /* Reset enable and disable */ |
| 1529 | snd_soc_update_bits(codec, main_reg, 0x40, 0x40); |
| 1530 | snd_soc_update_bits(codec, main_reg, 0x40, 0x00); |
| 1531 | /* Reset rate to 48K*/ |
| 1532 | snd_soc_update_bits(codec, main_reg, 0x0F, 0x04); |
| 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | dev_dbg(codec->dev, "%s event %d main_clk_users %d\n", |
| 1537 | __func__, event, rx_priv->main_clk_users[interp_idx]); |
| 1538 | |
| 1539 | return rx_priv->main_clk_users[interp_idx]; |
| 1540 | } |
| 1541 | |
| 1542 | static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, |
| 1543 | struct snd_kcontrol *kcontrol, int event) |
| 1544 | { |
| 1545 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 1546 | u16 sidetone_reg = 0; |
| 1547 | |
| 1548 | dev_dbg(codec->dev, "%s %d %d\n", __func__, event, w->shift); |
| 1549 | sidetone_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG1 + |
| 1550 | RX_MACRO_RX_PATH_OFFSET * (w->shift); |
| 1551 | |
| 1552 | switch (event) { |
| 1553 | case SND_SOC_DAPM_PRE_PMU: |
| 1554 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1555 | snd_soc_update_bits(codec, sidetone_reg, 0x10, 0x10); |
| 1556 | break; |
| 1557 | case SND_SOC_DAPM_POST_PMD: |
| 1558 | snd_soc_update_bits(codec, sidetone_reg, 0x10, 0x00); |
| 1559 | rx_macro_enable_interp_clk(codec, event, w->shift); |
| 1560 | break; |
| 1561 | default: |
| 1562 | break; |
| 1563 | }; |
| 1564 | return 0; |
| 1565 | } |
| 1566 | |
| 1567 | static void rx_macro_restore_iir_coeff(struct rx_macro_priv *rx_priv, int iir_idx, |
| 1568 | int band_idx) |
| 1569 | { |
| 1570 | u16 reg_add = 0, coeff_idx = 0, idx = 0; |
| 1571 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
| 1572 | |
| 1573 | regmap_write(regmap, |
| 1574 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 1575 | (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); |
| 1576 | |
| 1577 | reg_add = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; |
| 1578 | |
| 1579 | /* 5 coefficients per band and 4 writes per coefficient */ |
| 1580 | for (coeff_idx = 0; coeff_idx < RX_MACRO_SIDETONE_IIR_COEFF_MAX; |
| 1581 | coeff_idx++) { |
| 1582 | /* Four 8 bit values(one 32 bit) per coefficient */ |
| 1583 | regmap_write(regmap, reg_add, |
| 1584 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 1585 | regmap_write(regmap, reg_add, |
| 1586 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 1587 | regmap_write(regmap, reg_add, |
| 1588 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 1589 | regmap_write(regmap, reg_add, |
| 1590 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 1591 | } |
| 1592 | } |
| 1593 | |
| 1594 | static int rx_macro_iir_enable_audio_mixer_get(struct snd_kcontrol *kcontrol, |
| 1595 | struct snd_ctl_elem_value *ucontrol) |
| 1596 | { |
| 1597 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1598 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 1599 | kcontrol->private_value)->reg; |
| 1600 | int band_idx = ((struct soc_multi_mixer_control *) |
| 1601 | kcontrol->private_value)->shift; |
| 1602 | /* IIR filter band registers are at integer multiples of 0x80 */ |
| 1603 | u16 iir_reg = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL + 0x80 * iir_idx; |
| 1604 | |
| 1605 | ucontrol->value.integer.value[0] = (snd_soc_read(codec, iir_reg) & |
| 1606 | (1 << band_idx)) != 0; |
| 1607 | |
| 1608 | dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
| 1609 | iir_idx, band_idx, |
| 1610 | (uint32_t)ucontrol->value.integer.value[0]); |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | static int rx_macro_iir_enable_audio_mixer_put(struct snd_kcontrol *kcontrol, |
| 1615 | struct snd_ctl_elem_value *ucontrol) |
| 1616 | { |
| 1617 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1618 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 1619 | kcontrol->private_value)->reg; |
| 1620 | int band_idx = ((struct soc_multi_mixer_control *) |
| 1621 | kcontrol->private_value)->shift; |
| 1622 | bool iir_band_en_status = 0; |
| 1623 | int value = ucontrol->value.integer.value[0]; |
| 1624 | u16 iir_reg = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL + 0x80 * iir_idx; |
| 1625 | struct device *rx_dev = NULL; |
| 1626 | struct rx_macro_priv *rx_priv = NULL; |
| 1627 | |
| 1628 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1629 | return -EINVAL; |
| 1630 | |
| 1631 | rx_macro_restore_iir_coeff(rx_priv, iir_idx, band_idx); |
| 1632 | |
| 1633 | /* Mask first 5 bits, 6-8 are reserved */ |
| 1634 | snd_soc_update_bits(codec, iir_reg, (1 << band_idx), |
| 1635 | (value << band_idx)); |
| 1636 | |
| 1637 | iir_band_en_status = ((snd_soc_read(codec, iir_reg) & |
| 1638 | (1 << band_idx)) != 0); |
| 1639 | dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
| 1640 | iir_idx, band_idx, iir_band_en_status); |
| 1641 | return 0; |
| 1642 | } |
| 1643 | |
| 1644 | static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec, |
| 1645 | int iir_idx, int band_idx, |
| 1646 | int coeff_idx) |
| 1647 | { |
| 1648 | uint32_t value = 0; |
| 1649 | |
| 1650 | /* Address does not automatically update if reading */ |
| 1651 | snd_soc_write(codec, |
| 1652 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 1653 | ((band_idx * BAND_MAX + coeff_idx) |
| 1654 | * sizeof(uint32_t)) & 0x7F); |
| 1655 | |
| 1656 | value |= snd_soc_read(codec, |
| 1657 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx)); |
| 1658 | |
| 1659 | snd_soc_write(codec, |
| 1660 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 1661 | ((band_idx * BAND_MAX + coeff_idx) |
| 1662 | * sizeof(uint32_t) + 1) & 0x7F); |
| 1663 | |
| 1664 | value |= (snd_soc_read(codec, |
| 1665 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 1666 | 0x80 * iir_idx)) << 8); |
| 1667 | |
| 1668 | snd_soc_write(codec, |
| 1669 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 1670 | ((band_idx * BAND_MAX + coeff_idx) |
| 1671 | * sizeof(uint32_t) + 2) & 0x7F); |
| 1672 | |
| 1673 | value |= (snd_soc_read(codec, |
| 1674 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 1675 | 0x80 * iir_idx)) << 16); |
| 1676 | |
| 1677 | snd_soc_write(codec, |
| 1678 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 1679 | ((band_idx * BAND_MAX + coeff_idx) |
| 1680 | * sizeof(uint32_t) + 3) & 0x7F); |
| 1681 | |
| 1682 | /* Mask bits top 2 bits since they are reserved */ |
| 1683 | value |= ((snd_soc_read(codec, |
| 1684 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 1685 | 16 * iir_idx)) & 0x3F) << 24); |
| 1686 | |
| 1687 | return value; |
| 1688 | } |
| 1689 | |
| 1690 | static int rx_macro_iir_band_audio_mixer_get(struct snd_kcontrol *kcontrol, |
| 1691 | struct snd_ctl_elem_value *ucontrol) |
| 1692 | { |
| 1693 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1694 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 1695 | kcontrol->private_value)->reg; |
| 1696 | int band_idx = ((struct soc_multi_mixer_control *) |
| 1697 | kcontrol->private_value)->shift; |
| 1698 | |
| 1699 | ucontrol->value.integer.value[0] = |
| 1700 | get_iir_band_coeff(codec, iir_idx, band_idx, 0); |
| 1701 | ucontrol->value.integer.value[1] = |
| 1702 | get_iir_band_coeff(codec, iir_idx, band_idx, 1); |
| 1703 | ucontrol->value.integer.value[2] = |
| 1704 | get_iir_band_coeff(codec, iir_idx, band_idx, 2); |
| 1705 | ucontrol->value.integer.value[3] = |
| 1706 | get_iir_band_coeff(codec, iir_idx, band_idx, 3); |
| 1707 | ucontrol->value.integer.value[4] = |
| 1708 | get_iir_band_coeff(codec, iir_idx, band_idx, 4); |
| 1709 | |
| 1710 | dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" |
| 1711 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 1712 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 1713 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 1714 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 1715 | __func__, iir_idx, band_idx, |
| 1716 | (uint32_t)ucontrol->value.integer.value[0], |
| 1717 | __func__, iir_idx, band_idx, |
| 1718 | (uint32_t)ucontrol->value.integer.value[1], |
| 1719 | __func__, iir_idx, band_idx, |
| 1720 | (uint32_t)ucontrol->value.integer.value[2], |
| 1721 | __func__, iir_idx, band_idx, |
| 1722 | (uint32_t)ucontrol->value.integer.value[3], |
| 1723 | __func__, iir_idx, band_idx, |
| 1724 | (uint32_t)ucontrol->value.integer.value[4]); |
| 1725 | return 0; |
| 1726 | } |
| 1727 | |
| 1728 | static void set_iir_band_coeff(struct snd_soc_codec *codec, |
| 1729 | int iir_idx, int band_idx, |
| 1730 | uint32_t value) |
| 1731 | { |
| 1732 | snd_soc_write(codec, |
| 1733 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 1734 | (value & 0xFF)); |
| 1735 | |
| 1736 | snd_soc_write(codec, |
| 1737 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 1738 | (value >> 8) & 0xFF); |
| 1739 | |
| 1740 | snd_soc_write(codec, |
| 1741 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 1742 | (value >> 16) & 0xFF); |
| 1743 | |
| 1744 | /* Mask top 2 bits, 7-8 are reserved */ |
| 1745 | snd_soc_write(codec, |
| 1746 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 1747 | (value >> 24) & 0x3F); |
| 1748 | } |
| 1749 | |
| 1750 | static int rx_macro_iir_band_audio_mixer_put(struct snd_kcontrol *kcontrol, |
| 1751 | struct snd_ctl_elem_value *ucontrol) |
| 1752 | { |
| 1753 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 1754 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 1755 | kcontrol->private_value)->reg; |
| 1756 | int band_idx = ((struct soc_multi_mixer_control *) |
| 1757 | kcontrol->private_value)->shift; |
| 1758 | int coeff_idx, idx = 0; |
| 1759 | struct device *rx_dev = NULL; |
| 1760 | struct rx_macro_priv *rx_priv = NULL; |
| 1761 | |
| 1762 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 1763 | return -EINVAL; |
| 1764 | |
| 1765 | /* |
| 1766 | * Mask top bit it is reserved |
| 1767 | * Updates addr automatically for each B2 write |
| 1768 | */ |
| 1769 | snd_soc_write(codec, |
| 1770 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx), |
| 1771 | (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); |
| 1772 | |
| 1773 | /* Store the coefficients in sidetone coeff array */ |
| 1774 | for (coeff_idx = 0; coeff_idx < RX_MACRO_SIDETONE_IIR_COEFF_MAX; |
| 1775 | coeff_idx++) { |
| 1776 | uint32_t value = ucontrol->value.integer.value[coeff_idx]; |
| 1777 | |
| 1778 | set_iir_band_coeff(codec, iir_idx, band_idx, value); |
| 1779 | |
| 1780 | /* Four 8 bit values(one 32 bit) per coefficient */ |
| 1781 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 1782 | (value & 0xFF); |
| 1783 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 1784 | (value >> 8) & 0xFF; |
| 1785 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 1786 | (value >> 16) & 0xFF; |
| 1787 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 1788 | (value >> 24) & 0xFF; |
| 1789 | } |
| 1790 | |
| 1791 | pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n" |
| 1792 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 1793 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 1794 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 1795 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 1796 | __func__, iir_idx, band_idx, |
| 1797 | get_iir_band_coeff(codec, iir_idx, band_idx, 0), |
| 1798 | __func__, iir_idx, band_idx, |
| 1799 | get_iir_band_coeff(codec, iir_idx, band_idx, 1), |
| 1800 | __func__, iir_idx, band_idx, |
| 1801 | get_iir_band_coeff(codec, iir_idx, band_idx, 2), |
| 1802 | __func__, iir_idx, band_idx, |
| 1803 | get_iir_band_coeff(codec, iir_idx, band_idx, 3), |
| 1804 | __func__, iir_idx, band_idx, |
| 1805 | get_iir_band_coeff(codec, iir_idx, band_idx, 4)); |
| 1806 | return 0; |
| 1807 | } |
| 1808 | |
| 1809 | static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, |
| 1810 | struct snd_kcontrol *kcontrol, int event) |
| 1811 | { |
| 1812 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 1813 | |
| 1814 | dev_dbg(codec->dev, "%s: event = %d\n", __func__, event); |
| 1815 | |
| 1816 | switch (event) { |
| 1817 | case SND_SOC_DAPM_POST_PMU: /* fall through */ |
| 1818 | case SND_SOC_DAPM_PRE_PMD: |
| 1819 | if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { |
| 1820 | snd_soc_write(codec, |
| 1821 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, |
| 1822 | snd_soc_read(codec, |
| 1823 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)); |
| 1824 | snd_soc_write(codec, |
| 1825 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, |
| 1826 | snd_soc_read(codec, |
| 1827 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)); |
| 1828 | snd_soc_write(codec, |
| 1829 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, |
| 1830 | snd_soc_read(codec, |
| 1831 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)); |
| 1832 | snd_soc_write(codec, |
| 1833 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, |
| 1834 | snd_soc_read(codec, |
| 1835 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)); |
| 1836 | } else { |
| 1837 | snd_soc_write(codec, |
| 1838 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, |
| 1839 | snd_soc_read(codec, |
| 1840 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)); |
| 1841 | snd_soc_write(codec, |
| 1842 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, |
| 1843 | snd_soc_read(codec, |
| 1844 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)); |
| 1845 | snd_soc_write(codec, |
| 1846 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, |
| 1847 | snd_soc_read(codec, |
| 1848 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)); |
| 1849 | snd_soc_write(codec, |
| 1850 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, |
| 1851 | snd_soc_read(codec, |
| 1852 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)); |
| 1853 | } |
| 1854 | break; |
| 1855 | } |
| 1856 | return 0; |
| 1857 | } |
| 1858 | |
| 1859 | static const struct snd_kcontrol_new rx_macro_snd_controls[] = { |
| 1860 | SOC_SINGLE_SX_TLV("RX_RX0 Digital Volume", |
| 1861 | BOLERO_CDC_RX_RX0_RX_VOL_CTL, |
| 1862 | 0, -84, 40, digital_gain), |
| 1863 | SOC_SINGLE_SX_TLV("RX_RX1 Digital Volume", |
| 1864 | BOLERO_CDC_RX_RX1_RX_VOL_CTL, |
| 1865 | 0, -84, 40, digital_gain), |
| 1866 | SOC_SINGLE_SX_TLV("RX_RX2 Digital Volume", |
| 1867 | BOLERO_CDC_RX_RX2_RX_VOL_CTL, |
| 1868 | 0, -84, 40, digital_gain), |
| 1869 | SOC_SINGLE_SX_TLV("RX_RX0 Mix Digital Volume", |
| 1870 | BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 1871 | SOC_SINGLE_SX_TLV("RX_RX1 Mix Digital Volume", |
| 1872 | BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 1873 | SOC_SINGLE_SX_TLV("RX_RX2 Mix Digital Volume", |
| 1874 | BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 1875 | |
| 1876 | SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, |
| 1877 | rx_macro_get_compander, rx_macro_set_compander), |
| 1878 | SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0, |
| 1879 | rx_macro_get_compander, rx_macro_set_compander), |
| 1880 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1881 | SOC_ENUM_EXT("RX_EAR Mode", rx_macro_ear_mode_enum, |
| 1882 | rx_macro_get_ear_mode, rx_macro_put_ear_mode), |
| 1883 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1884 | SOC_SINGLE_SX_TLV("IIR0 INP0 Volume", |
| 1885 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0, -84, 40, |
| 1886 | digital_gain), |
| 1887 | SOC_SINGLE_SX_TLV("IIR0 INP1 Volume", |
| 1888 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0, -84, 40, |
| 1889 | digital_gain), |
| 1890 | SOC_SINGLE_SX_TLV("IIR0 INP2 Volume", |
| 1891 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0, -84, 40, |
| 1892 | digital_gain), |
| 1893 | SOC_SINGLE_SX_TLV("IIR0 INP3 Volume", |
| 1894 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0, -84, 40, |
| 1895 | digital_gain), |
| 1896 | SOC_SINGLE_SX_TLV("IIR1 INP0 Volume", |
| 1897 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0, -84, 40, |
| 1898 | digital_gain), |
| 1899 | SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", |
| 1900 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0, -84, 40, |
| 1901 | digital_gain), |
| 1902 | SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", |
| 1903 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0, -84, 40, |
| 1904 | digital_gain), |
| 1905 | SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", |
| 1906 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0, -84, 40, |
| 1907 | digital_gain), |
| 1908 | |
| 1909 | SOC_SINGLE_EXT("IIR0 Enable Band1", IIR0, BAND1, 1, 0, |
| 1910 | rx_macro_iir_enable_audio_mixer_get, |
| 1911 | rx_macro_iir_enable_audio_mixer_put), |
| 1912 | SOC_SINGLE_EXT("IIR0 Enable Band2", IIR0, BAND2, 1, 0, |
| 1913 | rx_macro_iir_enable_audio_mixer_get, |
| 1914 | rx_macro_iir_enable_audio_mixer_put), |
| 1915 | SOC_SINGLE_EXT("IIR0 Enable Band3", IIR0, BAND3, 1, 0, |
| 1916 | rx_macro_iir_enable_audio_mixer_get, |
| 1917 | rx_macro_iir_enable_audio_mixer_put), |
| 1918 | SOC_SINGLE_EXT("IIR0 Enable Band4", IIR0, BAND4, 1, 0, |
| 1919 | rx_macro_iir_enable_audio_mixer_get, |
| 1920 | rx_macro_iir_enable_audio_mixer_put), |
| 1921 | SOC_SINGLE_EXT("IIR0 Enable Band5", IIR0, BAND5, 1, 0, |
| 1922 | rx_macro_iir_enable_audio_mixer_get, |
| 1923 | rx_macro_iir_enable_audio_mixer_put), |
| 1924 | SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, |
| 1925 | rx_macro_iir_enable_audio_mixer_get, |
| 1926 | rx_macro_iir_enable_audio_mixer_put), |
| 1927 | SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, |
| 1928 | rx_macro_iir_enable_audio_mixer_get, |
| 1929 | rx_macro_iir_enable_audio_mixer_put), |
| 1930 | SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, |
| 1931 | rx_macro_iir_enable_audio_mixer_get, |
| 1932 | rx_macro_iir_enable_audio_mixer_put), |
| 1933 | SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, |
| 1934 | rx_macro_iir_enable_audio_mixer_get, |
| 1935 | rx_macro_iir_enable_audio_mixer_put), |
| 1936 | SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, |
| 1937 | rx_macro_iir_enable_audio_mixer_get, |
| 1938 | rx_macro_iir_enable_audio_mixer_put), |
| 1939 | |
| 1940 | SOC_SINGLE_MULTI_EXT("IIR0 Band1", IIR0, BAND1, 255, 0, 5, |
| 1941 | rx_macro_iir_band_audio_mixer_get, |
| 1942 | rx_macro_iir_band_audio_mixer_put), |
| 1943 | SOC_SINGLE_MULTI_EXT("IIR0 Band2", IIR0, BAND2, 255, 0, 5, |
| 1944 | rx_macro_iir_band_audio_mixer_get, |
| 1945 | rx_macro_iir_band_audio_mixer_put), |
| 1946 | SOC_SINGLE_MULTI_EXT("IIR0 Band3", IIR0, BAND3, 255, 0, 5, |
| 1947 | rx_macro_iir_band_audio_mixer_get, |
| 1948 | rx_macro_iir_band_audio_mixer_put), |
| 1949 | SOC_SINGLE_MULTI_EXT("IIR0 Band4", IIR0, BAND4, 255, 0, 5, |
| 1950 | rx_macro_iir_band_audio_mixer_get, |
| 1951 | rx_macro_iir_band_audio_mixer_put), |
| 1952 | SOC_SINGLE_MULTI_EXT("IIR0 Band5", IIR0, BAND5, 255, 0, 5, |
| 1953 | rx_macro_iir_band_audio_mixer_get, |
| 1954 | rx_macro_iir_band_audio_mixer_put), |
| 1955 | SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, |
| 1956 | rx_macro_iir_band_audio_mixer_get, |
| 1957 | rx_macro_iir_band_audio_mixer_put), |
| 1958 | SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, |
| 1959 | rx_macro_iir_band_audio_mixer_get, |
| 1960 | rx_macro_iir_band_audio_mixer_put), |
| 1961 | SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, |
| 1962 | rx_macro_iir_band_audio_mixer_get, |
| 1963 | rx_macro_iir_band_audio_mixer_put), |
| 1964 | SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, |
| 1965 | rx_macro_iir_band_audio_mixer_get, |
| 1966 | rx_macro_iir_band_audio_mixer_put), |
| 1967 | SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, |
| 1968 | rx_macro_iir_band_audio_mixer_get, |
| 1969 | rx_macro_iir_band_audio_mixer_put), |
| 1970 | }; |
| 1971 | |
| 1972 | static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { |
| 1973 | SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0, |
| 1974 | SND_SOC_NOPM, 0, 0), |
| 1975 | |
| 1976 | SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0, |
| 1977 | SND_SOC_NOPM, 0, 0), |
| 1978 | |
| 1979 | SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0, |
| 1980 | SND_SOC_NOPM, 0, 0), |
| 1981 | |
| 1982 | SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0, |
| 1983 | SND_SOC_NOPM, 0, 0), |
| 1984 | |
| 1985 | RX_MACRO_DAPM_MUX("RX_MACRO RX0 MUX", RX_MACRO_RX0, rx_macro_rx0), |
| 1986 | RX_MACRO_DAPM_MUX("RX_MACRO RX1 MUX", RX_MACRO_RX1, rx_macro_rx1), |
| 1987 | RX_MACRO_DAPM_MUX("RX_MACRO RX2 MUX", RX_MACRO_RX2, rx_macro_rx2), |
| 1988 | RX_MACRO_DAPM_MUX("RX_MACRO RX3 MUX", RX_MACRO_RX3, rx_macro_rx3), |
| 1989 | RX_MACRO_DAPM_MUX("RX_MACRO RX4 MUX", RX_MACRO_RX4, rx_macro_rx4), |
| 1990 | RX_MACRO_DAPM_MUX("RX_MACRO RX5 MUX", RX_MACRO_RX5, rx_macro_rx5), |
| 1991 | |
| 1992 | SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1993 | SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1994 | SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1995 | SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1996 | SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1997 | SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1998 | |
| 1999 | RX_MACRO_DAPM_MUX("IIR0 INP0 MUX", 0, iir0_inp0), |
| 2000 | RX_MACRO_DAPM_MUX("IIR0 INP1 MUX", 0, iir0_inp1), |
| 2001 | RX_MACRO_DAPM_MUX("IIR0 INP2 MUX", 0, iir0_inp2), |
| 2002 | RX_MACRO_DAPM_MUX("IIR0 INP3 MUX", 0, iir0_inp3), |
| 2003 | RX_MACRO_DAPM_MUX("IIR1 INP0 MUX", 0, iir1_inp0), |
| 2004 | RX_MACRO_DAPM_MUX("IIR1 INP1 MUX", 0, iir1_inp1), |
| 2005 | RX_MACRO_DAPM_MUX("IIR1 INP2 MUX", 0, iir1_inp2), |
| 2006 | RX_MACRO_DAPM_MUX("IIR1 INP3 MUX", 0, iir1_inp3), |
| 2007 | |
| 2008 | SND_SOC_DAPM_MIXER_E("IIR0", BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, |
| 2009 | 4, 0, NULL, 0, rx_macro_set_iir_gain, |
| 2010 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 2011 | SND_SOC_DAPM_MIXER_E("IIR1", BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, |
| 2012 | 4, 0, NULL, 0, rx_macro_set_iir_gain, |
| 2013 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 2014 | SND_SOC_DAPM_MIXER("SRC0", BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, |
| 2015 | 4, 0, NULL, 0), |
| 2016 | SND_SOC_DAPM_MIXER("SRC1", BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, |
| 2017 | 4, 0, NULL, 0), |
| 2018 | |
| 2019 | RX_MACRO_DAPM_MUX("RX MIX TX0 MUX", 0, rx_mix_tx0), |
| 2020 | RX_MACRO_DAPM_MUX("RX MIX TX1 MUX", 0, rx_mix_tx1), |
| 2021 | RX_MACRO_DAPM_MUX("RX MIX TX2 MUX", 0, rx_mix_tx2), |
| 2022 | RX_MACRO_DAPM_MUX("RX INT0 DEM MUX", 0, rx_int0_dem_inp), |
| 2023 | RX_MACRO_DAPM_MUX("RX INT1 DEM MUX", 0, rx_int1_dem_inp), |
| 2024 | |
| 2025 | SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, |
| 2026 | &rx_int0_2_mux, rx_macro_enable_mix_path, |
| 2027 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2028 | SND_SOC_DAPM_POST_PMD), |
| 2029 | SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, |
| 2030 | &rx_int1_2_mux, rx_macro_enable_mix_path, |
| 2031 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2032 | SND_SOC_DAPM_POST_PMD), |
| 2033 | SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0, |
| 2034 | &rx_int2_2_mux, rx_macro_enable_mix_path, |
| 2035 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2036 | SND_SOC_DAPM_POST_PMD), |
| 2037 | |
| 2038 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP0", 0, rx_int0_1_mix_inp0), |
| 2039 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP1", 0, rx_int0_1_mix_inp1), |
| 2040 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP2", 0, rx_int0_1_mix_inp2), |
| 2041 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP0", 0, rx_int1_1_mix_inp0), |
| 2042 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP1", 0, rx_int1_1_mix_inp1), |
| 2043 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP2", 0, rx_int1_1_mix_inp2), |
| 2044 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP0", 0, rx_int2_1_mix_inp0), |
| 2045 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP1", 0, rx_int2_1_mix_inp1), |
| 2046 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP2", 0, rx_int2_1_mix_inp2), |
| 2047 | |
| 2048 | SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, |
| 2049 | &rx_int0_1_interp_mux, rx_macro_enable_main_path, |
| 2050 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2051 | SND_SOC_DAPM_POST_PMD), |
| 2052 | SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, |
| 2053 | &rx_int1_1_interp_mux, rx_macro_enable_main_path, |
| 2054 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2055 | SND_SOC_DAPM_POST_PMD), |
| 2056 | SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0, |
| 2057 | &rx_int2_1_interp_mux, rx_macro_enable_main_path, |
| 2058 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2059 | SND_SOC_DAPM_POST_PMD), |
| 2060 | |
| 2061 | RX_MACRO_DAPM_MUX("RX INT0_2 INTERP", 0, rx_int0_2_interp), |
| 2062 | RX_MACRO_DAPM_MUX("RX INT1_2 INTERP", 0, rx_int1_2_interp), |
| 2063 | RX_MACRO_DAPM_MUX("RX INT2_2 INTERP", 0, rx_int2_2_interp), |
| 2064 | |
| 2065 | SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2066 | SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2067 | SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2068 | SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2069 | SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2070 | SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2071 | |
| 2072 | SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL, |
| 2073 | 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2074 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2075 | SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR, |
| 2076 | 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2077 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2078 | SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX, |
| 2079 | 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2080 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2081 | |
| 2082 | SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2083 | SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2084 | SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2085 | |
| 2086 | SND_SOC_DAPM_OUTPUT("HPHL_OUT"), |
| 2087 | SND_SOC_DAPM_OUTPUT("HPHR_OUT"), |
| 2088 | SND_SOC_DAPM_OUTPUT("AUX_OUT"), |
| 2089 | |
| 2090 | SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"), |
| 2091 | SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"), |
| 2092 | SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"), |
| 2093 | SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"), |
| 2094 | |
| 2095 | SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 2096 | rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2097 | }; |
| 2098 | |
| 2099 | static const struct snd_soc_dapm_route rx_audio_map[] = { |
| 2100 | {"RX AIF1 PB", NULL, "RX_MCLK"}, |
| 2101 | {"RX AIF2 PB", NULL, "RX_MCLK"}, |
| 2102 | {"RX AIF3 PB", NULL, "RX_MCLK"}, |
| 2103 | {"RX AIF4 PB", NULL, "RX_MCLK"}, |
| 2104 | |
| 2105 | {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2106 | {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2107 | {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2108 | {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2109 | {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2110 | {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2111 | |
| 2112 | {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2113 | {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2114 | {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2115 | {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2116 | {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2117 | {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2118 | |
| 2119 | {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2120 | {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2121 | {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2122 | {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2123 | {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2124 | {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2125 | |
| 2126 | {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2127 | {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2128 | {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2129 | {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2130 | {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2131 | {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2132 | |
| 2133 | {"RX_RX0", NULL, "RX_MACRO RX0 MUX"}, |
| 2134 | {"RX_RX1", NULL, "RX_MACRO RX1 MUX"}, |
| 2135 | {"RX_RX2", NULL, "RX_MACRO RX2 MUX"}, |
| 2136 | {"RX_RX3", NULL, "RX_MACRO RX3 MUX"}, |
| 2137 | {"RX_RX4", NULL, "RX_MACRO RX4 MUX"}, |
| 2138 | {"RX_RX5", NULL, "RX_MACRO RX5 MUX"}, |
| 2139 | |
| 2140 | {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 2141 | {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 2142 | {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 2143 | {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 2144 | {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 2145 | {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 2146 | {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 2147 | {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 2148 | {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 2149 | {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 2150 | {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 2151 | {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 2152 | {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 2153 | {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 2154 | {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 2155 | {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 2156 | {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 2157 | {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 2158 | {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 2159 | {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 2160 | {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 2161 | {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 2162 | {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 2163 | {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 2164 | |
| 2165 | {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 2166 | {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 2167 | {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 2168 | {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 2169 | {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 2170 | {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 2171 | {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 2172 | {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 2173 | {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 2174 | {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 2175 | {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 2176 | {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 2177 | {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 2178 | {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 2179 | {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 2180 | {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 2181 | {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 2182 | {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 2183 | {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 2184 | {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 2185 | {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 2186 | {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 2187 | {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 2188 | {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 2189 | |
| 2190 | {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 2191 | {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 2192 | {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 2193 | {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 2194 | {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 2195 | {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 2196 | {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 2197 | {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 2198 | {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 2199 | {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 2200 | {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 2201 | {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 2202 | {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 2203 | {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 2204 | {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 2205 | {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 2206 | {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 2207 | {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 2208 | {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 2209 | {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 2210 | {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 2211 | {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 2212 | {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 2213 | {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 2214 | |
| 2215 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"}, |
| 2216 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"}, |
| 2217 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"}, |
| 2218 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"}, |
| 2219 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"}, |
| 2220 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"}, |
| 2221 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"}, |
| 2222 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"}, |
| 2223 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"}, |
| 2224 | |
| 2225 | /* Mixing path INT0 */ |
| 2226 | {"RX INT0_2 MUX", "RX0", "RX_RX0"}, |
| 2227 | {"RX INT0_2 MUX", "RX1", "RX_RX1"}, |
| 2228 | {"RX INT0_2 MUX", "RX2", "RX_RX2"}, |
| 2229 | {"RX INT0_2 MUX", "RX3", "RX_RX3"}, |
| 2230 | {"RX INT0_2 MUX", "RX4", "RX_RX4"}, |
| 2231 | {"RX INT0_2 MUX", "RX5", "RX_RX5"}, |
| 2232 | {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"}, |
| 2233 | {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"}, |
| 2234 | |
| 2235 | /* Mixing path INT1 */ |
| 2236 | {"RX INT1_2 MUX", "RX0", "RX_RX0"}, |
| 2237 | {"RX INT1_2 MUX", "RX1", "RX_RX1"}, |
| 2238 | {"RX INT1_2 MUX", "RX2", "RX_RX2"}, |
| 2239 | {"RX INT1_2 MUX", "RX3", "RX_RX3"}, |
| 2240 | {"RX INT1_2 MUX", "RX4", "RX_RX4"}, |
| 2241 | {"RX INT1_2 MUX", "RX5", "RX_RX5"}, |
| 2242 | {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"}, |
| 2243 | {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"}, |
| 2244 | |
| 2245 | /* Mixing path INT2 */ |
| 2246 | {"RX INT2_2 MUX", "RX0", "RX_RX0"}, |
| 2247 | {"RX INT2_2 MUX", "RX1", "RX_RX1"}, |
| 2248 | {"RX INT2_2 MUX", "RX2", "RX_RX2"}, |
| 2249 | {"RX INT2_2 MUX", "RX3", "RX_RX3"}, |
| 2250 | {"RX INT2_2 MUX", "RX4", "RX_RX4"}, |
| 2251 | {"RX INT2_2 MUX", "RX5", "RX_RX5"}, |
| 2252 | {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"}, |
| 2253 | {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"}, |
| 2254 | |
| 2255 | {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"}, |
| 2256 | {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"}, |
| 2257 | {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"}, |
| 2258 | {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"}, |
| 2259 | {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, |
| 2260 | {"HPHL_OUT", NULL, "RX INT0 DEM MUX"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2261 | {"HPHL_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2262 | |
| 2263 | {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"}, |
| 2264 | {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"}, |
| 2265 | {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"}, |
| 2266 | {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"}, |
| 2267 | {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"}, |
| 2268 | {"HPHR_OUT", NULL, "RX INT1 DEM MUX"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2269 | {"HPHR_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2270 | |
| 2271 | {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"}, |
| 2272 | {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"}, |
| 2273 | {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"}, |
| 2274 | {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"}, |
| 2275 | {"AUX_OUT", NULL, "RX INT2 MIX2"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2276 | {"AUX_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2277 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2278 | {"IIR0", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2279 | {"IIR0", NULL, "IIR0 INP0 MUX"}, |
| 2280 | {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2281 | {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2282 | {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2283 | {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2284 | {"IIR0 INP0 MUX", "RX0", "RX_RX0"}, |
| 2285 | {"IIR0 INP0 MUX", "RX1", "RX_RX1"}, |
| 2286 | {"IIR0 INP0 MUX", "RX2", "RX_RX2"}, |
| 2287 | {"IIR0 INP0 MUX", "RX3", "RX_RX3"}, |
| 2288 | {"IIR0 INP0 MUX", "RX4", "RX_RX4"}, |
| 2289 | {"IIR0 INP0 MUX", "RX5", "RX_RX5"}, |
| 2290 | {"IIR0", NULL, "IIR0 INP1 MUX"}, |
| 2291 | {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2292 | {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2293 | {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2294 | {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2295 | {"IIR0 INP1 MUX", "RX0", "RX_RX0"}, |
| 2296 | {"IIR0 INP1 MUX", "RX1", "RX_RX1"}, |
| 2297 | {"IIR0 INP1 MUX", "RX2", "RX_RX2"}, |
| 2298 | {"IIR0 INP1 MUX", "RX3", "RX_RX3"}, |
| 2299 | {"IIR0 INP1 MUX", "RX4", "RX_RX4"}, |
| 2300 | {"IIR0 INP1 MUX", "RX5", "RX_RX5"}, |
| 2301 | {"IIR0", NULL, "IIR0 INP2 MUX"}, |
| 2302 | {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2303 | {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2304 | {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2305 | {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2306 | {"IIR0 INP2 MUX", "RX0", "RX_RX0"}, |
| 2307 | {"IIR0 INP2 MUX", "RX1", "RX_RX1"}, |
| 2308 | {"IIR0 INP2 MUX", "RX2", "RX_RX2"}, |
| 2309 | {"IIR0 INP2 MUX", "RX3", "RX_RX3"}, |
| 2310 | {"IIR0 INP2 MUX", "RX4", "RX_RX4"}, |
| 2311 | {"IIR0 INP2 MUX", "RX5", "RX_RX5"}, |
| 2312 | {"IIR0", NULL, "IIR0 INP3 MUX"}, |
| 2313 | {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2314 | {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2315 | {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2316 | {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2317 | {"IIR0 INP3 MUX", "RX0", "RX_RX0"}, |
| 2318 | {"IIR0 INP3 MUX", "RX1", "RX_RX1"}, |
| 2319 | {"IIR0 INP3 MUX", "RX2", "RX_RX2"}, |
| 2320 | {"IIR0 INP3 MUX", "RX3", "RX_RX3"}, |
| 2321 | {"IIR0 INP3 MUX", "RX4", "RX_RX4"}, |
| 2322 | {"IIR0 INP3 MUX", "RX5", "RX_RX5"}, |
| 2323 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2324 | {"IIR1", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2325 | {"IIR1", NULL, "IIR1 INP0 MUX"}, |
| 2326 | {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2327 | {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2328 | {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2329 | {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2330 | {"IIR1 INP0 MUX", "RX0", "RX_RX0"}, |
| 2331 | {"IIR1 INP0 MUX", "RX1", "RX_RX1"}, |
| 2332 | {"IIR1 INP0 MUX", "RX2", "RX_RX2"}, |
| 2333 | {"IIR1 INP0 MUX", "RX3", "RX_RX3"}, |
| 2334 | {"IIR1 INP0 MUX", "RX4", "RX_RX4"}, |
| 2335 | {"IIR1 INP0 MUX", "RX5", "RX_RX5"}, |
| 2336 | {"IIR1", NULL, "IIR1 INP1 MUX"}, |
| 2337 | {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2338 | {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2339 | {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2340 | {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2341 | {"IIR1 INP1 MUX", "RX0", "RX_RX0"}, |
| 2342 | {"IIR1 INP1 MUX", "RX1", "RX_RX1"}, |
| 2343 | {"IIR1 INP1 MUX", "RX2", "RX_RX2"}, |
| 2344 | {"IIR1 INP1 MUX", "RX3", "RX_RX3"}, |
| 2345 | {"IIR1 INP1 MUX", "RX4", "RX_RX4"}, |
| 2346 | {"IIR1 INP1 MUX", "RX5", "RX_RX5"}, |
| 2347 | {"IIR1", NULL, "IIR1 INP2 MUX"}, |
| 2348 | {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2349 | {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2350 | {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2351 | {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2352 | {"IIR1 INP2 MUX", "RX0", "RX_RX0"}, |
| 2353 | {"IIR1 INP2 MUX", "RX1", "RX_RX1"}, |
| 2354 | {"IIR1 INP2 MUX", "RX2", "RX_RX2"}, |
| 2355 | {"IIR1 INP2 MUX", "RX3", "RX_RX3"}, |
| 2356 | {"IIR1 INP2 MUX", "RX4", "RX_RX4"}, |
| 2357 | {"IIR1 INP2 MUX", "RX5", "RX_RX5"}, |
| 2358 | {"IIR1", NULL, "IIR1 INP3 MUX"}, |
| 2359 | {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 2360 | {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 2361 | {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 2362 | {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 2363 | {"IIR1 INP3 MUX", "RX0", "RX_RX0"}, |
| 2364 | {"IIR1 INP3 MUX", "RX1", "RX_RX1"}, |
| 2365 | {"IIR1 INP3 MUX", "RX2", "RX_RX2"}, |
| 2366 | {"IIR1 INP3 MUX", "RX3", "RX_RX3"}, |
| 2367 | {"IIR1 INP3 MUX", "RX4", "RX_RX4"}, |
| 2368 | {"IIR1 INP3 MUX", "RX5", "RX_RX5"}, |
| 2369 | |
| 2370 | {"SRC0", NULL, "IIR0"}, |
| 2371 | {"SRC1", NULL, "IIR1"}, |
| 2372 | {"RX INT0 MIX2 INP", "SRC0", "SRC0"}, |
| 2373 | {"RX INT0 MIX2 INP", "SRC1", "SRC1"}, |
| 2374 | {"RX INT1 MIX2 INP", "SRC0", "SRC0"}, |
| 2375 | {"RX INT1 MIX2 INP", "SRC1", "SRC1"}, |
| 2376 | {"RX INT2 MIX2 INP", "SRC0", "SRC0"}, |
| 2377 | {"RX INT2 MIX2 INP", "SRC1", "SRC1"}, |
| 2378 | }; |
| 2379 | |
| 2380 | static int rx_swrm_clock(void *handle, bool enable) |
| 2381 | { |
| 2382 | struct rx_macro_priv *rx_priv = (struct rx_macro_priv *) handle; |
| 2383 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
| 2384 | int ret = 0; |
| 2385 | |
| 2386 | mutex_lock(&rx_priv->swr_clk_lock); |
| 2387 | |
| 2388 | dev_dbg(rx_priv->dev, "%s: swrm clock %s\n", |
| 2389 | __func__, (enable ? "enable" : "disable")); |
| 2390 | if (enable) { |
| 2391 | if (rx_priv->swr_clk_users == 0) { |
| 2392 | ret = rx_macro_mclk_enable(rx_priv, 1, true); |
| 2393 | if (ret < 0) { |
| 2394 | dev_err(rx_priv->dev, |
| 2395 | "%s: rx request clock enable failed\n", |
| 2396 | __func__); |
| 2397 | goto exit; |
| 2398 | } |
| 2399 | regmap_update_bits(regmap, |
| 2400 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 2401 | 0x02, 0x02); |
| 2402 | regmap_update_bits(regmap, |
| 2403 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2404 | 0x01, 0x01); |
| 2405 | regmap_update_bits(regmap, |
| 2406 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 2407 | 0x02, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2408 | msm_cdc_pinctrl_select_active_state( |
| 2409 | rx_priv->rx_swr_gpio_p); |
| 2410 | } |
| 2411 | rx_priv->swr_clk_users++; |
| 2412 | } else { |
| 2413 | if (rx_priv->swr_clk_users <= 0) { |
| 2414 | dev_err(rx_priv->dev, |
| 2415 | "%s: rx swrm clock users already reset\n", |
| 2416 | __func__); |
| 2417 | rx_priv->swr_clk_users = 0; |
| 2418 | goto exit; |
| 2419 | } |
| 2420 | rx_priv->swr_clk_users--; |
| 2421 | if (rx_priv->swr_clk_users == 0) { |
| 2422 | regmap_update_bits(regmap, |
| 2423 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
| 2424 | 0x01, 0x00); |
| 2425 | msm_cdc_pinctrl_select_sleep_state( |
| 2426 | rx_priv->rx_swr_gpio_p); |
| 2427 | rx_macro_mclk_enable(rx_priv, 0, true); |
| 2428 | } |
| 2429 | } |
| 2430 | dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n", |
| 2431 | __func__, rx_priv->swr_clk_users); |
| 2432 | exit: |
| 2433 | mutex_unlock(&rx_priv->swr_clk_lock); |
| 2434 | return ret; |
| 2435 | } |
| 2436 | |
| 2437 | static int rx_macro_init(struct snd_soc_codec *codec) |
| 2438 | { |
| 2439 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
| 2440 | int ret = 0; |
| 2441 | struct device *rx_dev = NULL; |
| 2442 | struct rx_macro_priv *rx_priv = NULL; |
| 2443 | |
| 2444 | rx_dev = bolero_get_device_ptr(codec->dev, RX_MACRO); |
| 2445 | if (!rx_dev) { |
| 2446 | dev_err(codec->dev, |
| 2447 | "%s: null device for macro!\n", __func__); |
| 2448 | return -EINVAL; |
| 2449 | } |
| 2450 | rx_priv = dev_get_drvdata(rx_dev); |
| 2451 | if (!rx_priv) { |
| 2452 | dev_err(codec->dev, |
| 2453 | "%s: priv is null for macro!\n", __func__); |
| 2454 | return -EINVAL; |
| 2455 | } |
| 2456 | |
| 2457 | ret = snd_soc_dapm_new_controls(dapm, rx_macro_dapm_widgets, |
| 2458 | ARRAY_SIZE(rx_macro_dapm_widgets)); |
| 2459 | if (ret < 0) { |
| 2460 | dev_err(rx_dev, "%s: failed to add controls\n", __func__); |
| 2461 | return ret; |
| 2462 | } |
| 2463 | ret = snd_soc_dapm_add_routes(dapm, rx_audio_map, |
| 2464 | ARRAY_SIZE(rx_audio_map)); |
| 2465 | if (ret < 0) { |
| 2466 | dev_err(rx_dev, "%s: failed to add routes\n", __func__); |
| 2467 | return ret; |
| 2468 | } |
| 2469 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 2470 | if (ret < 0) { |
| 2471 | dev_err(rx_dev, "%s: failed to add widgets\n", __func__); |
| 2472 | return ret; |
| 2473 | } |
| 2474 | ret = snd_soc_add_codec_controls(codec, rx_macro_snd_controls, |
| 2475 | ARRAY_SIZE(rx_macro_snd_controls)); |
| 2476 | if (ret < 0) { |
| 2477 | dev_err(rx_dev, "%s: failed to add snd_ctls\n", __func__); |
| 2478 | return ret; |
| 2479 | } |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 2480 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL, 0x01, 0x01); |
| 2481 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL, 0x01, 0x01); |
| 2482 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x01, 0x01); |
| 2483 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX0_RX_PATH_SEC7, 0x07, 0x02); |
| 2484 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX1_RX_PATH_SEC7, 0x07, 0x02); |
| 2485 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX2_RX_PATH_SEC7, 0x07, 0x02); |
| 2486 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX0_RX_PATH_CFG3, 0x03, 0x02); |
| 2487 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX1_RX_PATH_CFG3, 0x03, 0x02); |
| 2488 | snd_soc_update_bits(codec, BOLERO_CDC_RX_RX2_RX_PATH_CFG3, 0x03, 0x02); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2489 | |
| 2490 | rx_priv->codec = codec; |
| 2491 | |
| 2492 | return 0; |
| 2493 | } |
| 2494 | |
| 2495 | static int rx_macro_deinit(struct snd_soc_codec *codec) |
| 2496 | { |
| 2497 | struct device *rx_dev = NULL; |
| 2498 | struct rx_macro_priv *rx_priv = NULL; |
| 2499 | |
| 2500 | if (!rx_macro_get_data(codec, &rx_dev, &rx_priv, __func__)) |
| 2501 | return -EINVAL; |
| 2502 | |
| 2503 | rx_priv->codec = NULL; |
| 2504 | |
| 2505 | return 0; |
| 2506 | } |
| 2507 | |
| 2508 | static void rx_macro_add_child_devices(struct work_struct *work) |
| 2509 | { |
| 2510 | struct rx_macro_priv *rx_priv = NULL; |
| 2511 | struct platform_device *pdev = NULL; |
| 2512 | struct device_node *node = NULL; |
| 2513 | struct rx_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; |
| 2514 | int ret = 0; |
| 2515 | u16 count = 0, ctrl_num = 0; |
| 2516 | struct rx_swr_ctrl_platform_data *platdata = NULL; |
| 2517 | char plat_dev_name[RX_SWR_STRING_LEN] = ""; |
| 2518 | bool rx_swr_master_node = false; |
| 2519 | |
| 2520 | rx_priv = container_of(work, struct rx_macro_priv, |
| 2521 | rx_macro_add_child_devices_work); |
| 2522 | if (!rx_priv) { |
| 2523 | pr_err("%s: Memory for rx_priv does not exist\n", |
| 2524 | __func__); |
| 2525 | return; |
| 2526 | } |
| 2527 | |
| 2528 | if (!rx_priv->dev) { |
| 2529 | pr_err("%s: RX device does not exist\n", __func__); |
| 2530 | return; |
| 2531 | } |
| 2532 | |
| 2533 | if(!rx_priv->dev->of_node) { |
| 2534 | dev_err(rx_priv->dev, |
| 2535 | "%s: DT node for RX dev does not exist\n", __func__); |
| 2536 | return; |
| 2537 | } |
| 2538 | |
| 2539 | platdata = &rx_priv->swr_plat_data; |
| 2540 | rx_priv->child_count = 0; |
| 2541 | |
| 2542 | for_each_available_child_of_node(rx_priv->dev->of_node, node) { |
| 2543 | rx_swr_master_node = false; |
| 2544 | if (strnstr(node->name, "rx_swr_master", |
| 2545 | strlen("rx_swr_master")) != NULL) |
| 2546 | rx_swr_master_node = true; |
| 2547 | |
| 2548 | if(rx_swr_master_node) |
| 2549 | strlcpy(plat_dev_name, "rx_swr_ctrl", |
| 2550 | (RX_SWR_STRING_LEN - 1)); |
| 2551 | else |
| 2552 | strlcpy(plat_dev_name, node->name, |
| 2553 | (RX_SWR_STRING_LEN - 1)); |
| 2554 | |
| 2555 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 2556 | if (!pdev) { |
| 2557 | dev_err(rx_priv->dev, "%s: pdev memory alloc failed\n", |
| 2558 | __func__); |
| 2559 | ret = -ENOMEM; |
| 2560 | goto err; |
| 2561 | } |
| 2562 | pdev->dev.parent = rx_priv->dev; |
| 2563 | pdev->dev.of_node = node; |
| 2564 | |
| 2565 | if (rx_swr_master_node) { |
| 2566 | ret = platform_device_add_data(pdev, platdata, |
| 2567 | sizeof(*platdata)); |
| 2568 | if (ret) { |
| 2569 | dev_err(&pdev->dev, |
| 2570 | "%s: cannot add plat data ctrl:%d\n", |
| 2571 | __func__, ctrl_num); |
| 2572 | goto fail_pdev_add; |
| 2573 | } |
| 2574 | } |
| 2575 | |
| 2576 | ret = platform_device_add(pdev); |
| 2577 | if (ret) { |
| 2578 | dev_err(&pdev->dev, |
| 2579 | "%s: Cannot add platform device\n", |
| 2580 | __func__); |
| 2581 | goto fail_pdev_add; |
| 2582 | } |
| 2583 | |
| 2584 | if (rx_swr_master_node) { |
| 2585 | temp = krealloc(swr_ctrl_data, |
| 2586 | (ctrl_num + 1) * sizeof( |
| 2587 | struct rx_swr_ctrl_data), |
| 2588 | GFP_KERNEL); |
| 2589 | if (!temp) { |
| 2590 | ret = -ENOMEM; |
| 2591 | goto fail_pdev_add; |
| 2592 | } |
| 2593 | swr_ctrl_data = temp; |
| 2594 | swr_ctrl_data[ctrl_num].rx_swr_pdev = pdev; |
| 2595 | ctrl_num++; |
| 2596 | dev_dbg(&pdev->dev, |
| 2597 | "%s: Added soundwire ctrl device(s)\n", |
| 2598 | __func__); |
| 2599 | rx_priv->swr_ctrl_data = swr_ctrl_data; |
| 2600 | } |
| 2601 | if (rx_priv->child_count < RX_MACRO_CHILD_DEVICES_MAX) |
| 2602 | rx_priv->pdev_child_devices[ |
| 2603 | rx_priv->child_count++] = pdev; |
| 2604 | else |
| 2605 | goto err; |
| 2606 | } |
| 2607 | return; |
| 2608 | fail_pdev_add: |
| 2609 | for (count = 0; count < rx_priv->child_count; count++) |
| 2610 | platform_device_put(rx_priv->pdev_child_devices[count]); |
| 2611 | err: |
| 2612 | return; |
| 2613 | } |
| 2614 | |
| 2615 | static void rx_macro_init_ops(struct macro_ops *ops, char __iomem *rx_io_base) |
| 2616 | { |
| 2617 | memset(ops, 0, sizeof(struct macro_ops)); |
| 2618 | ops->init = rx_macro_init; |
| 2619 | ops->exit = rx_macro_deinit; |
| 2620 | ops->io_base = rx_io_base; |
| 2621 | ops->dai_ptr = rx_macro_dai; |
| 2622 | ops->num_dais = ARRAY_SIZE(rx_macro_dai); |
| 2623 | ops->mclk_fn = rx_macro_mclk_ctrl; |
| 2624 | } |
| 2625 | |
| 2626 | static int rx_macro_probe(struct platform_device *pdev) |
| 2627 | { |
| 2628 | struct macro_ops ops = {0}; |
| 2629 | struct rx_macro_priv *rx_priv = NULL; |
| 2630 | u32 rx_base_addr = 0, muxsel = 0; |
| 2631 | char __iomem *rx_io_base = NULL, *muxsel_io = NULL; |
| 2632 | int ret = 0; |
| 2633 | struct clk *rx_core_clk = NULL, *rx_npl_clk = NULL; |
| 2634 | |
| 2635 | rx_priv = devm_kzalloc(&pdev->dev, sizeof(struct rx_macro_priv), |
| 2636 | GFP_KERNEL); |
| 2637 | if (!rx_priv) |
| 2638 | return -ENOMEM; |
| 2639 | |
| 2640 | rx_priv->dev = &pdev->dev; |
| 2641 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 2642 | &rx_base_addr); |
| 2643 | if (ret) { |
| 2644 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 2645 | __func__, "reg"); |
| 2646 | return ret; |
| 2647 | } |
| 2648 | ret = of_property_read_u32(pdev->dev.of_node, "qcom,rx_mclk_mode_muxsel", |
| 2649 | &muxsel); |
| 2650 | if (ret) { |
| 2651 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 2652 | __func__, "reg"); |
| 2653 | return ret; |
| 2654 | } |
| 2655 | rx_priv->rx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 2656 | "qcom,rx-swr-gpios", 0); |
| 2657 | if (!rx_priv->rx_swr_gpio_p) { |
| 2658 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 2659 | __func__); |
| 2660 | return -EINVAL; |
| 2661 | } |
| 2662 | rx_io_base = devm_ioremap(&pdev->dev, rx_base_addr, |
| 2663 | RX_MACRO_MAX_OFFSET); |
| 2664 | if (!rx_io_base) { |
| 2665 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 2666 | return -ENOMEM; |
| 2667 | } |
| 2668 | rx_priv->rx_io_base = rx_io_base; |
| 2669 | muxsel_io = devm_ioremap(&pdev->dev, muxsel, 0x4); |
| 2670 | if (!muxsel_io) { |
| 2671 | dev_err(&pdev->dev, "%s: ioremap failed for muxsel\n", |
| 2672 | __func__); |
| 2673 | return -ENOMEM; |
| 2674 | } |
| 2675 | rx_priv->rx_mclk_mode_muxsel = muxsel_io; |
| 2676 | INIT_WORK(&rx_priv->rx_macro_add_child_devices_work, |
| 2677 | rx_macro_add_child_devices); |
| 2678 | rx_priv->swr_plat_data.handle = (void *) rx_priv; |
| 2679 | rx_priv->swr_plat_data.read = NULL; |
| 2680 | rx_priv->swr_plat_data.write = NULL; |
| 2681 | rx_priv->swr_plat_data.bulk_write = NULL; |
| 2682 | rx_priv->swr_plat_data.clk = rx_swrm_clock; |
| 2683 | rx_priv->swr_plat_data.handle_irq = NULL; |
| 2684 | |
| 2685 | /* Register MCLK for rx macro */ |
| 2686 | rx_core_clk = devm_clk_get(&pdev->dev, "rx_core_clk"); |
| 2687 | if (IS_ERR(rx_core_clk)) { |
| 2688 | ret = PTR_ERR(rx_core_clk); |
| 2689 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 2690 | __func__, "rx_core_clk", ret); |
| 2691 | return ret; |
| 2692 | } |
| 2693 | rx_priv->rx_core_clk = rx_core_clk; |
| 2694 | /* Register npl clk for soundwire */ |
| 2695 | rx_npl_clk = devm_clk_get(&pdev->dev, "rx_npl_clk"); |
| 2696 | if (IS_ERR(rx_npl_clk)) { |
| 2697 | ret = PTR_ERR(rx_npl_clk); |
| 2698 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 2699 | __func__, "rx_npl_clk", ret); |
| 2700 | return ret; |
| 2701 | } |
| 2702 | rx_priv->rx_npl_clk = rx_npl_clk; |
| 2703 | dev_set_drvdata(&pdev->dev, rx_priv); |
| 2704 | mutex_init(&rx_priv->mclk_lock); |
| 2705 | mutex_init(&rx_priv->swr_clk_lock); |
| 2706 | rx_macro_init_ops(&ops, rx_io_base); |
| 2707 | |
| 2708 | ret = bolero_register_macro(&pdev->dev, RX_MACRO, &ops); |
| 2709 | if (ret) { |
| 2710 | dev_err(&pdev->dev, |
| 2711 | "%s: register macro failed\n", __func__); |
| 2712 | goto err_reg_macro; |
| 2713 | } |
| 2714 | schedule_work(&rx_priv->rx_macro_add_child_devices_work); |
| 2715 | |
| 2716 | return 0; |
| 2717 | |
| 2718 | err_reg_macro: |
| 2719 | mutex_destroy(&rx_priv->mclk_lock); |
| 2720 | mutex_destroy(&rx_priv->swr_clk_lock); |
| 2721 | return ret; |
| 2722 | } |
| 2723 | |
| 2724 | static int rx_macro_remove(struct platform_device *pdev) |
| 2725 | { |
| 2726 | struct rx_macro_priv *rx_priv = NULL; |
| 2727 | u16 count = 0; |
| 2728 | |
| 2729 | rx_priv = dev_get_drvdata(&pdev->dev); |
| 2730 | |
| 2731 | if (!rx_priv) |
| 2732 | return -EINVAL; |
| 2733 | |
| 2734 | for (count = 0; count < rx_priv->child_count && |
| 2735 | count < RX_MACRO_CHILD_DEVICES_MAX; count++) |
| 2736 | platform_device_unregister(rx_priv->pdev_child_devices[count]); |
| 2737 | |
| 2738 | bolero_unregister_macro(&pdev->dev, RX_MACRO); |
| 2739 | mutex_destroy(&rx_priv->mclk_lock); |
| 2740 | mutex_destroy(&rx_priv->swr_clk_lock); |
| 2741 | kfree(rx_priv->swr_ctrl_data); |
| 2742 | return 0; |
| 2743 | } |
| 2744 | |
| 2745 | static const struct of_device_id rx_macro_dt_match[] = { |
| 2746 | {.compatible = "qcom,rx-macro"}, |
| 2747 | {} |
| 2748 | }; |
| 2749 | |
| 2750 | static struct platform_driver rx_macro_driver = { |
| 2751 | .driver = { |
| 2752 | .name = "rx_macro", |
| 2753 | .owner = THIS_MODULE, |
| 2754 | .of_match_table = rx_macro_dt_match, |
| 2755 | }, |
| 2756 | .probe = rx_macro_probe, |
| 2757 | .remove = rx_macro_remove, |
| 2758 | }; |
| 2759 | |
| 2760 | module_platform_driver(rx_macro_driver); |
| 2761 | |
| 2762 | MODULE_DESCRIPTION("RX macro driver"); |
| 2763 | MODULE_LICENSE("GPL v2"); |