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Meng Wang43bbb872018-12-10 12:32:05 +08001/* SPDX-License-Identifier: GPL-2.0-only */
Vignesh Kulothunganf86a3552019-07-11 15:46:25 -07002/* Copyright (c) 2012-2017, 2019 The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +05303 */
4
5#ifndef __MSM_DAI_Q6_PDATA_H__
6
7#define __MSM_DAI_Q6_PDATA_H__
8
9#define MSM_MI2S_SD0 (1 << 0)
10#define MSM_MI2S_SD1 (1 << 1)
11#define MSM_MI2S_SD2 (1 << 2)
12#define MSM_MI2S_SD3 (1 << 3)
Dieter Luecking92c6a5f2018-09-28 15:05:43 +020013#define MSM_MI2S_SD4 (1 << 4)
14#define MSM_MI2S_SD5 (1 << 5)
15#define MSM_MI2S_SD6 (1 << 6)
16#define MSM_MI2S_SD7 (1 << 7)
17
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053018#define MSM_MI2S_CAP_RX 0
19#define MSM_MI2S_CAP_TX 1
20
21#define MSM_PRIM_MI2S 0
22#define MSM_SEC_MI2S 1
23#define MSM_TERT_MI2S 2
24#define MSM_QUAT_MI2S 3
Rohit kumarb242df42017-10-16 15:37:05 +053025#define MSM_QUIN_MI2S 4
Aditya Bavanari18129b12019-07-03 17:22:20 +053026#define MSM_SENARY_MI2S 5
27#define MSM_SEC_MI2S_SD1 6
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053028#define MSM_INT0_MI2S 7
29#define MSM_INT1_MI2S 8
30#define MSM_INT2_MI2S 9
31#define MSM_INT3_MI2S 10
32#define MSM_INT4_MI2S 11
33#define MSM_INT5_MI2S 12
34#define MSM_INT6_MI2S 13
35#define MSM_MI2S_MIN MSM_PRIM_MI2S
36#define MSM_MI2S_MAX MSM_INT6_MI2S
37
Vignesh Kulothunganf86a3552019-07-11 15:46:25 -070038#define MSM_DISPLAY_PORT 0
39#define MSM_DISPLAY_PORT1 1
40
Ralf Herz29e07132019-07-26 15:15:21 +020041#define MSM_PRIM_META_MI2S 0
42#define MSM_SEC_META_MI2S 1
43#define MSM_META_MI2S_MIN MSM_PRIM_META_MI2S
44#define MSM_META_MI2S_MAX MSM_SEC_META_MI2S
45
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053046struct msm_dai_auxpcm_config {
47 u16 mode;
48 u16 sync;
49 u16 frame;
50 u16 quant;
51 u16 num_slots;
52 u16 *slot_mapping;
53 u16 data;
54 u32 pcm_clk_rate;
55};
56
57struct msm_dai_auxpcm_pdata {
58 struct msm_dai_auxpcm_config mode_8k;
59 struct msm_dai_auxpcm_config mode_16k;
60};
61
62struct msm_mi2s_pdata {
63 u16 rx_sd_lines;
64 u16 tx_sd_lines;
65 u16 intf_id;
66};
67
Ralf Herz29e07132019-07-26 15:15:21 +020068struct msm_meta_mi2s_pdata {
69 u32 num_member_ports;
70 u32 member_port[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
71 u32 sd_lines[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
72 u16 intf_id;
73};
74
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053075struct msm_i2s_data {
76 u32 capability; /* RX or TX */
77 u16 sd_lines;
78};
79
80struct msm_dai_tdm_group_config {
81 u16 group_id;
82 u16 num_ports;
83 u16 *port_id;
84 u32 clk_rate;
85};
86
87struct msm_dai_tdm_config {
88 u16 sync_mode;
89 u16 sync_src;
90 u16 data_out;
91 u16 invert_sync;
92 u16 data_delay;
93 u32 data_align;
94 u16 header_start_offset;
95 u16 header_width;
96 u16 header_num_frame_repeat;
97};
98
99struct msm_dai_tdm_pdata {
100 struct msm_dai_tdm_group_config group_config;
101 struct msm_dai_tdm_config config;
102};
103
104#endif