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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / c1a5a5068a2fd37c06456f18c2a27de0aeb99c5b / . / asoc / sdm660-common.c
blob: 1cceb7acfcb187acfc6dc9285a5f9722b999c89e [file] [log] [blame]
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1/* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/input.h>
14#include <linux/of_gpio.h>
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of_device.h>
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]18#include <sound/pcm_params.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]19#include <dsp/q6afe-v2.h>
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]20#include <dsp/audio_notifier.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]21#include "msm-pcm-routing-v2.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]22#include "sdm660-common.h"
23#include "sdm660-internal.h"
24#include "sdm660-external.h"
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]25#include "codecs/msm-cdc-pinctrl.h"
26#include "codecs/sdm660_cdc/msm-analog-cdc.h"
27#include "codecs/wsa881x.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]28
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]29#define __CHIPSET__ "SDM660 "
30#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
31
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]32#define DRV_NAME "sdm660-asoc-snd"
33
34#define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
35#define PMIC_INT_ANALOG_CODEC "analog-codec"
36
37#define DEV_NAME_STR_LEN 32
38#define DEFAULT_MCLK_RATE 9600000
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]39#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]40
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]41enum {
42 DP_RX_IDX,
43 EXT_DISP_RX_IDX_MAX,
44};
45
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]46enum {
47 PRIMARY_TDM_RX_0,
48 PRIMARY_TDM_RX_1,
49 PRIMARY_TDM_RX_2,
50 PRIMARY_TDM_RX_3,
51 PRIMARY_TDM_RX_4,
52 PRIMARY_TDM_RX_5,
53 PRIMARY_TDM_RX_6,
54 PRIMARY_TDM_RX_7,
55 TDM_MAX_RX,
56};
57enum {
58 PRIMARY_TDM_TX_0,
59 PRIMARY_TDM_TX_1,
60 PRIMARY_TDM_TX_2,
61 PRIMARY_TDM_TX_3,
62 PRIMARY_TDM_TX_4,
63 PRIMARY_TDM_TX_5,
64 PRIMARY_TDM_TX_6,
65 PRIMARY_TDM_TX_7,
66 TDM_MAX_TX,
67};
68
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]69bool codec_reg_done;
70
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]71struct tdm_dai_data {
72 DECLARE_BITMAP(status_mask, 3);
73 u32 rate;
74 u32 channels;
75 u32 bitwidth;
76 u32 num_group_ports;
77 struct afe_clk_set clk_set; /* hold LPASS clock config. */
78 union afe_port_group_config group_cfg; /* hold tdm group config */
79 struct afe_tdm_port_config port_cfg; /* hold tdm config */
80};
81
82
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]83/* TDM default config */
84static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
85 { /* PRI TDM */
86 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
87 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
88 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
89 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
90 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
91 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
92 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
93 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
94 },
95 { /* SEC TDM */
96 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
97 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
98 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
99 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
100 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
101 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
102 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
103 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
104 },
105 { /* TERT TDM */
106 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
107 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
108 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
109 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
110 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
111 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
112 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
113 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
114 },
115 { /* QUAT TDM */
116 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
117 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
118 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
119 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
120 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
121 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
122 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
123 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]124 },
125 { /* QUIN TDM */
126 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
127 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
128 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
129 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
130 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
131 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
132 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
133 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]134 }
135};
136
137/* TDM default config */
138static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
139 { /* PRI TDM */
140 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
141 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
142 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
143 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
144 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
145 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
146 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
147 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
148 },
149 { /* SEC TDM */
150 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
151 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
152 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
153 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
154 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
155 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
156 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
157 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
158 },
159 { /* TERT TDM */
160 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
161 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
162 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
163 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
164 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
165 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
166 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
167 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
168 },
169 { /* QUAT TDM */
170 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
171 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
172 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
173 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
174 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
175 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
176 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
177 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]178 },
179 { /* QUIN TDM */
180 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
181 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
182 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
183 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
184 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
185 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
186 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
187 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]188 }
189};
190
191/* Default configuration of external display BE */
192static struct dev_config ext_disp_rx_cfg[] = {
193 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
194};
195static struct dev_config usb_rx_cfg = {
196 .sample_rate = SAMPLING_RATE_48KHZ,
197 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
198 .channels = 2,
199};
200
201static struct dev_config usb_tx_cfg = {
202 .sample_rate = SAMPLING_RATE_48KHZ,
203 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
204 .channels = 1,
205};
206
207enum {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]208 PRIM_AUX_PCM = 0,
209 SEC_AUX_PCM,
210 TERT_AUX_PCM,
211 QUAT_AUX_PCM,
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]212 QUIN_AUX_PCM,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]213 AUX_PCM_MAX,
214};
215
216enum {
217 PCM_I2S_SEL_PRIM = 0,
218 PCM_I2S_SEL_SEC,
219 PCM_I2S_SEL_TERT,
220 PCM_I2S_SEL_QUAT,
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]221 PCM_I2S_SEL_QUIN,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]222 PCM_I2S_SEL_MAX,
223};
224
225struct mi2s_conf {
226 struct mutex lock;
227 u32 ref_cnt;
228 u32 msm_is_mi2s_master;
229 u32 msm_is_ext_mclk;
230};
231
232static u32 mi2s_ebit_clk[MI2S_MAX] = {
233 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
234 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
235 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]236 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
237 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]238};
239
240struct msm_wsa881x_dev_info {
241 struct device_node *of_node;
242 u32 index;
243};
244static struct snd_soc_aux_dev *msm_aux_dev;
245static struct snd_soc_codec_conf *msm_codec_conf;
246
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]247static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]248
249static struct wcd_mbhc_config mbhc_cfg = {
250 .read_fw_bin = false,
251 .calibration = NULL,
252 .detect_extn_cable = true,
253 .mono_stero_detection = false,
254 .swap_gnd_mic = NULL,
255 .hs_ext_micbias = true,
256 .key_code[0] = KEY_MEDIA,
257 .key_code[1] = KEY_VOICECOMMAND,
258 .key_code[2] = KEY_VOLUMEUP,
259 .key_code[3] = KEY_VOLUMEDOWN,
260 .key_code[4] = 0,
261 .key_code[5] = 0,
262 .key_code[6] = 0,
263 .key_code[7] = 0,
264 .linein_th = 5000,
265 .moisture_en = false,
266 .mbhc_micbias = 0,
267 .anc_micbias = 0,
268 .enable_anc_mic_detect = false,
269};
270
271static struct dev_config proxy_rx_cfg = {
272 .sample_rate = SAMPLING_RATE_48KHZ,
273 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
274 .channels = 2,
275};
276
277/* Default configuration of MI2S channels */
278static struct dev_config mi2s_rx_cfg[] = {
279 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
280 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
281 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
282 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]283 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]284};
285
286static struct dev_config mi2s_tx_cfg[] = {
287 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
288 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
289 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
290 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]291 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]292};
293
294static struct dev_config aux_pcm_rx_cfg[] = {
295 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
296 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
297 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
298 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]299 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]300};
301
302static struct dev_config aux_pcm_tx_cfg[] = {
303 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
304 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
305 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
306 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]307 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]308};
309
310static char const *ch_text[] = {"Two", "Three", "Four", "Five",
311 "Six", "Seven", "Eight"};
312static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
313static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
314 "KHZ_32", "KHZ_44P1", "KHZ_48",
315 "KHZ_96", "KHZ_192"};
316static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
317 "Five", "Six", "Seven",
318 "Eight"};
319static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
320 "S32_LE"};
321static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
322 "S32_LE"};
323static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]324 "Five", "Six", "Seven", "Eight",
325 "Nine", "Ten", "Eleven", "Twelve",
326 "Thirteen", "Fourteen", "Fifteen",
327 "Sixteen"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]328static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
329static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
330 "KHZ_44P1", "KHZ_48", "KHZ_96",
331 "KHZ_192", "KHZ_352P8", "KHZ_384"};
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]332static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
333 "Eight", "Sixteen", "ThirtyTwo"};
334static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]335static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
336 "Five", "Six", "Seven",
337 "Eight"};
338static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
339 "KHZ_16", "KHZ_22P05",
340 "KHZ_32", "KHZ_44P1", "KHZ_48",
341 "KHZ_96", "KHZ_192", "KHZ_384"};
342static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
343static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
344 "KHZ_192"};
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]345static const char *const qos_text[] = {"Disable", "Enable"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]346
347static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
348static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
349static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
350static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
351static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
352static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]353static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]354static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
355static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
356static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
357static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]358static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]359static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
360static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
361static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
362static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]363static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]364static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
365static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
366static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
367static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]368static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]369static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
370static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
371static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
372static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]373static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]374static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
375static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
376static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
377static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]378static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]379static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
380static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
381static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
382static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
383static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
384static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
385static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
386static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]387static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
388static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]389static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
390static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
391static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
392static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
393static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
394static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
395static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
396static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
397 ext_disp_sample_rate_text);
398static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
399static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
400static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
401static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
402static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
403static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]404static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
405static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]406static SOC_ENUM_SINGLE_EXT_DECL(qos_vote, qos_text);
407
408static int qos_vote_status;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]409
410static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
411 {
412 AFE_API_VERSION_I2S_CONFIG,
413 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
414 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
415 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
416 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
417 0,
418 },
419 {
420 AFE_API_VERSION_I2S_CONFIG,
421 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
422 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
423 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
424 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
425 0,
426 },
427 {
428 AFE_API_VERSION_I2S_CONFIG,
429 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
430 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
431 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
432 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
433 0,
434 },
435 {
436 AFE_API_VERSION_I2S_CONFIG,
437 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
438 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
439 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
440 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
441 0,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]442 },
443 {
444 AFE_API_VERSION_I2S_CONFIG,
445 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
446 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
447 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
448 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
449 0,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]450 }
451};
452
453static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
454 {
455 AFE_API_VERSION_I2S_CONFIG,
456 Q6AFE_LPASS_CLK_ID_MCLK_3,
457 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
458 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
459 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
460 0,
461 },
462 {
463 AFE_API_VERSION_I2S_CONFIG,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]464 Q6AFE_LPASS_CLK_ID_MCLK_2,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]465 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
466 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
467 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
468 0,
469 },
470 {
471 AFE_API_VERSION_I2S_CONFIG,
472 Q6AFE_LPASS_CLK_ID_MCLK_1,
473 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
474 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
475 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
476 0,
477 },
478 {
479 AFE_API_VERSION_I2S_CONFIG,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]480 Q6AFE_LPASS_CLK_ID_MCLK_1,
481 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
482 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
483 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
484 0,
485 },
486 {
487 AFE_API_VERSION_I2S_CONFIG,
488 Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]489 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
490 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
491 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
492 0,
493 }
494};
495
496static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
497
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]498/* TDM default slot config */
499struct tdm_slot_cfg {
500 u32 width;
501 u32 num;
502};
503
504static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
505 /* PRI TDM */
506 {32, 8},
507 /* SEC TDM */
508 {32, 8},
509 /* TERT TDM */
510 {32, 8},
511 /* QUAT TDM */
512 {32, 8},
513 /* QUIN TDM */
514 {32, 8}
515};
516
517static unsigned int tdm_rx_slot_offset
518 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
519 {/* PRI TDM */
520 {0, 4, 8, 12, 16, 20, 24, 28,
521 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
522 {0xFFFF}, /* not used */
523 {0xFFFF}, /* not used */
524 {0xFFFF}, /* not used */
525 {0xFFFF}, /* not used */
526 {0xFFFF}, /* not used */
527 {0xFFFF}, /* not used */
528 {0xFFFF}, /* not used */
529 },
530 {/* SEC TDM */
531 {0, 4, 8, 12, 16, 20, 24, 28,
532 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
533 {0xFFFF}, /* not used */
534 {0xFFFF}, /* not used */
535 {0xFFFF}, /* not used */
536 {0xFFFF}, /* not used */
537 {0xFFFF}, /* not used */
538 {0xFFFF}, /* not used */
539 {0xFFFF}, /* not used */
540 },
541 {/* TERT TDM */
542 {0, 4, 8, 12, 16, 20, 24, 28,
543 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
544 {0xFFFF}, /* not used */
545 {0xFFFF}, /* not used */
546 {0xFFFF}, /* not used */
547 {0xFFFF}, /* not used */
548 {0xFFFF}, /* not used */
549 {0xFFFF}, /* not used */
550 {0xFFFF}, /* not used */
551 },
552 {/* QUAT TDM */
553 {0, 4, 8, 12, 16, 20, 24, 28,
554 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
555 {0xFFFF}, /* not used */
556 {0xFFFF}, /* not used */
557 {0xFFFF}, /* not used */
558 {0xFFFF}, /* not used */
559 {0xFFFF}, /* not used */
560 {0xFFFF}, /* not used */
561 },
562 {/* QUIN TDM */
563 {0, 4, 8, 12, 16, 20, 24, 28,
564 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
565 {0xFFFF}, /* not used */
566 {0xFFFF}, /* not used */
567 {0xFFFF}, /* not used */
568 {0xFFFF}, /* not used */
569 {0xFFFF}, /* not used */
570 {0xFFFF}, /* not used */
571 }
572};
573
574static unsigned int tdm_tx_slot_offset
575 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
576 {/* PRI TDM */
577 {0, 4, 8, 12, 16, 20, 24, 28,
578 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
579 {0xFFFF}, /* not used */
580 {0xFFFF}, /* not used */
581 {0xFFFF}, /* not used */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
584 {0xFFFF}, /* not used */
585 {0xFFFF}, /* not used */
586 },
587 {/* SEC TDM */
588 {0, 4, 8, 12, 16, 20, 24, 28,
589 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
590 {0xFFFF}, /* not used */
591 {0xFFFF}, /* not used */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
594 {0xFFFF}, /* not used */
595 {0xFFFF}, /* not used */
596 {0xFFFF}, /* not used */
597 },
598 {/* TERT TDM */
599 {0, 4, 8, 12, 16, 20, 24, 28,
600 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
601 {0xFFFF}, /* not used */
602 {0xFFFF}, /* not used */
603 {0xFFFF}, /* not used */
604 {0xFFFF}, /* not used */
605 {0xFFFF}, /* not used */
606 {0xFFFF}, /* not used */
607 {0xFFFF}, /* not used */
608 },
609 {/* QUAT TDM */
610 {0, 4, 8, 12, 16, 20, 24, 28,
611 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},/*MIC ARR*/
612 {0xFFFF}, /* not used */
613 {0xFFFF}, /* not used */
614 {0xFFFF}, /* not used */
615 {0xFFFF}, /* not used */
616 {0xFFFF}, /* not used */
617 {0xFFFF}, /* not used */
618 {0xFFFF}, /* not used */
619 },
620 {/* QUIN TDM */
621 {0, 4, 8, 12, 16, 20, 24, 28,
622 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
623 {0xFFFF}, /* not used */
624 {0xFFFF}, /* not used */
625 {0xFFFF}, /* not used */
626 {0xFFFF}, /* not used */
627 {0xFFFF}, /* not used */
628 {0xFFFF}, /* not used */
629 }
630};
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]631
632static unsigned int tdm_param_set_slot_mask(u16 port_id, int slot_width,
633 int slots, int tdm_interface)
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]634{
635 unsigned int slot_mask = 0;
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]636 int upper, lower, i, j, rx_path = 0;
637 unsigned int *slot_offset;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]638
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]639 switch (port_id) {
640 pr_err("port_id %x", port_id );
641 case AFE_PORT_ID_PRIMARY_TDM_RX:
642 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
643 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
644 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
645 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
646 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
647 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
648 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
649 lower = PRIMARY_TDM_RX_0;
650 upper = PRIMARY_TDM_RX_7;
651 rx_path = 1;
652 break;
653 case AFE_PORT_ID_PRIMARY_TDM_TX:
654 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
655 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
656 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
657 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
658 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
659 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
660 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
661 lower = PRIMARY_TDM_TX_0;
662 upper = PRIMARY_TDM_TX_7;
663 break;
664 default:
665 return slot_mask;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]666 }
667
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]668 for (i = lower; i <= upper; i++) {
669 if (rx_path)
670 slot_offset = tdm_rx_slot_offset[tdm_interface][i];
671 else
672 slot_offset = tdm_tx_slot_offset[tdm_interface][i];
673
674 for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) {
675 if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) {
676 /*
677 * set the mask of active slot according to
678 * the offset table for the group of devices
679 */
680 slot_mask |=
681 (1 << ((slot_offset[j] * 8) / slot_width));
682 } else {
683 break;
684 }
685 }
686 }
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]687
688 return slot_mask;
689}
690
691int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream,
692 struct snd_pcm_hw_params *params)
693{
694 struct snd_soc_pcm_runtime *rtd = substream->private_data;
695 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
696 int ret = 0;
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]697 int channels, slot_width, slots, rate, format, tdm_interface;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]698 unsigned int slot_mask;
699 unsigned int *slot_offset;
700 int offset_channels = 0;
701 int i;
702 int clk_freq;
703
704 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
705
706 channels = params_channels(params);
707 if (channels < 1 || channels > 32) {
708 pr_err("%s: invalid param channels %d\n",
709 __func__, channels);
710 return -EINVAL;
711 }
712
713 format = params_format(params);
714 if (format != SNDRV_PCM_FORMAT_S32_LE &&
715 format != SNDRV_PCM_FORMAT_S24_LE &&
716 format != SNDRV_PCM_FORMAT_S16_LE) {
717 /*
718 * up to 8 channels HW config should
719 * use 32 bit slot width for max support of
720 * stream bit width. (slot_width > bit_width)
721 */
722 pr_err("%s: invalid param format 0x%x\n",
723 __func__, format);
724 return -EINVAL;
725 }
726
727 switch (cpu_dai->id) {
728 case AFE_PORT_ID_PRIMARY_TDM_RX:
729 slots = tdm_slot[TDM_PRI].num;
730 slot_width = tdm_slot[TDM_PRI].width;
731 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]732 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]733 break;
734 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
735 slots = tdm_slot[TDM_PRI].num;
736 slot_width = tdm_slot[TDM_PRI].width;
737 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]738 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]739 break;
740 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
741 slots = tdm_slot[TDM_PRI].num;
742 slot_width = tdm_slot[TDM_PRI].width;
743 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]744 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]745 break;
746 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
747 slots = tdm_slot[TDM_PRI].num;
748 slot_width = tdm_slot[TDM_PRI].width;
749 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]750 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]751 break;
752 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
753 slots = tdm_slot[TDM_PRI].num;
754 slot_width = tdm_slot[TDM_PRI].width;
755 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]756 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]757 break;
758 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
759 slots = tdm_slot[TDM_PRI].num;
760 slot_width = tdm_slot[TDM_PRI].width;
761 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]762 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]763 break;
764 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
765 slots = tdm_slot[TDM_PRI].num;
766 slot_width = tdm_slot[TDM_PRI].width;
767 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]768 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]769 break;
770 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
771 slots = tdm_slot[TDM_PRI].num;
772 slot_width = tdm_slot[TDM_PRI].width;
773 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]774 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]775 break;
776 case AFE_PORT_ID_PRIMARY_TDM_TX:
777 slots = tdm_slot[TDM_PRI].num;
778 slot_width = tdm_slot[TDM_PRI].width;
779 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]780 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]781 break;
782 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
783 slots = tdm_slot[TDM_PRI].num;
784 slot_width = tdm_slot[TDM_PRI].width;
785 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]786 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]787 break;
788 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
789 slots = tdm_slot[TDM_PRI].num;
790 slot_width = tdm_slot[TDM_PRI].width;
791 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]792 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]793 break;
794 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
795 slots = tdm_slot[TDM_PRI].num;
796 slot_width = tdm_slot[TDM_PRI].width;
797 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]798 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]799 break;
800 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
801 slots = tdm_slot[TDM_PRI].num;
802 slot_width = tdm_slot[TDM_PRI].width;
803 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]804 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]805 break;
806 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
807 slots = tdm_slot[TDM_PRI].num;
808 slot_width = tdm_slot[TDM_PRI].width;
809 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]810 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]811 break;
812 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
813 slots = tdm_slot[TDM_PRI].num;
814 slot_width = tdm_slot[TDM_PRI].width;
815 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]816 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]817 break;
818 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
819 slots = tdm_slot[TDM_PRI].num;
820 slot_width = tdm_slot[TDM_PRI].width;
821 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]822 tdm_interface = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]823 break;
824 case AFE_PORT_ID_SECONDARY_TDM_RX:
825 slots = tdm_slot[TDM_SEC].num;
826 slot_width = tdm_slot[TDM_SEC].width;
827 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]828 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]829 break;
830 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
831 slots = tdm_slot[TDM_SEC].num;
832 slot_width = tdm_slot[TDM_SEC].width;
833 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]834 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]835 break;
836 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
837 slots = tdm_slot[TDM_SEC].num;
838 slot_width = tdm_slot[TDM_SEC].width;
839 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]840 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]841 break;
842 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
843 slots = tdm_slot[TDM_SEC].num;
844 slot_width = tdm_slot[TDM_SEC].width;
845 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]846 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]847 break;
848 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
849 slots = tdm_slot[TDM_SEC].num;
850 slot_width = tdm_slot[TDM_SEC].width;
851 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]852 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]853 break;
854 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
855 slots = tdm_slot[TDM_SEC].num;
856 slot_width = tdm_slot[TDM_SEC].width;
857 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]858 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]859 break;
860 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
861 slots = tdm_slot[TDM_SEC].num;
862 slot_width = tdm_slot[TDM_SEC].width;
863 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]864 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]865 break;
866 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
867 slots = tdm_slot[TDM_SEC].num;
868 slot_width = tdm_slot[TDM_SEC].width;
869 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]870 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]871 break;
872 case AFE_PORT_ID_SECONDARY_TDM_TX:
873 slots = tdm_slot[TDM_SEC].num;
874 slot_width = tdm_slot[TDM_SEC].width;
875 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]876 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]877 break;
878 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
879 slots = tdm_slot[TDM_SEC].num;
880 slot_width = tdm_slot[TDM_SEC].width;
881 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]882 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]883 break;
884 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
885 slots = tdm_slot[TDM_SEC].num;
886 slot_width = tdm_slot[TDM_SEC].width;
887 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]888 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]889 break;
890 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
891 slots = tdm_slot[TDM_SEC].num;
892 slot_width = tdm_slot[TDM_SEC].width;
893 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]894 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]895 break;
896 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
897 slots = tdm_slot[TDM_SEC].num;
898 slot_width = tdm_slot[TDM_SEC].width;
899 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]900 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]901 break;
902 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
903 slots = tdm_slot[TDM_SEC].num;
904 slot_width = tdm_slot[TDM_SEC].width;
905 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]906 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]907 break;
908 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
909 slots = tdm_slot[TDM_SEC].num;
910 slot_width = tdm_slot[TDM_SEC].width;
911 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]912 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]913 break;
914 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
915 slots = tdm_slot[TDM_SEC].num;
916 slot_width = tdm_slot[TDM_SEC].width;
917 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]918 tdm_interface = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]919 break;
920 case AFE_PORT_ID_TERTIARY_TDM_RX:
921 slots = tdm_slot[TDM_TERT].num;
922 slot_width = tdm_slot[TDM_TERT].width;
923 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]924 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]925 break;
926 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
927 slots = tdm_slot[TDM_TERT].num;
928 slot_width = tdm_slot[TDM_TERT].width;
929 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]930 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]931 break;
932 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
933 slots = tdm_slot[TDM_TERT].num;
934 slot_width = tdm_slot[TDM_TERT].width;
935 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]936 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]937 break;
938 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
939 slots = tdm_slot[TDM_TERT].num;
940 slot_width = tdm_slot[TDM_TERT].width;
941 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]942 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]943 break;
944 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
945 slots = tdm_slot[TDM_TERT].num;
946 slot_width = tdm_slot[TDM_TERT].width;
947 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]948 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]949 break;
950 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
951 slots = tdm_slot[TDM_TERT].num;
952 slot_width = tdm_slot[TDM_TERT].width;
953 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]954 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]955 break;
956 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
957 slots = tdm_slot[TDM_TERT].num;
958 slot_width = tdm_slot[TDM_TERT].width;
959 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]960 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]961 break;
962 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
963 slots = tdm_slot[TDM_TERT].num;
964 slot_width = tdm_slot[TDM_TERT].width;
965 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]966 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]967 break;
968 case AFE_PORT_ID_TERTIARY_TDM_TX:
969 slots = tdm_slot[TDM_TERT].num;
970 slot_width = tdm_slot[TDM_TERT].width;
971 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]972 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]973 break;
974 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
975 slots = tdm_slot[TDM_TERT].num;
976 slot_width = tdm_slot[TDM_TERT].width;
977 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]978 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]979 break;
980 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
981 slots = tdm_slot[TDM_TERT].num;
982 slot_width = tdm_slot[TDM_TERT].width;
983 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]984 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]985 break;
986 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
987 slots = tdm_slot[TDM_TERT].num;
988 slot_width = tdm_slot[TDM_TERT].width;
989 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]990 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]991 break;
992 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
993 slots = tdm_slot[TDM_TERT].num;
994 slot_width = tdm_slot[TDM_TERT].width;
995 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]996 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]997 break;
998 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
999 slots = tdm_slot[TDM_TERT].num;
1000 slot_width = tdm_slot[TDM_TERT].width;
1001 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1002 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1003 break;
1004 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
1005 slots = tdm_slot[TDM_TERT].num;
1006 slot_width = tdm_slot[TDM_TERT].width;
1007 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1008 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1009 break;
1010 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
1011 slots = tdm_slot[TDM_TERT].num;
1012 slot_width = tdm_slot[TDM_TERT].width;
1013 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1014 tdm_interface = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1015 break;
1016 case AFE_PORT_ID_QUATERNARY_TDM_RX:
1017 slots = tdm_slot[TDM_QUAT].num;
1018 slot_width = tdm_slot[TDM_QUAT].width;
1019 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1020 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1021 break;
1022 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
1023 slots = tdm_slot[TDM_QUAT].num;
1024 slot_width = tdm_slot[TDM_QUAT].width;
1025 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1026 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1027 break;
1028 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
1029 slots = tdm_slot[TDM_QUAT].num;
1030 slot_width = tdm_slot[TDM_QUAT].width;
1031 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1032 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1033 break;
1034 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
1035 slots = tdm_slot[TDM_QUAT].num;
1036 slot_width = tdm_slot[TDM_QUAT].width;
1037 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1038 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1039 break;
1040 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
1041 slots = tdm_slot[TDM_QUAT].num;
1042 slot_width = tdm_slot[TDM_QUAT].width;
1043 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1044 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1045 break;
1046 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
1047 slots = tdm_slot[TDM_QUAT].num;
1048 slot_width = tdm_slot[TDM_QUAT].width;
1049 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1050 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1051 break;
1052 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
1053 slots = tdm_slot[TDM_QUAT].num;
1054 slot_width = tdm_slot[TDM_QUAT].width;
1055 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1056 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1057 break;
1058 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
1059 slots = tdm_slot[TDM_QUAT].num;
1060 slot_width = tdm_slot[TDM_QUAT].width;
1061 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1062 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1063 break;
1064 case AFE_PORT_ID_QUATERNARY_TDM_TX:
1065 slots = tdm_slot[TDM_QUAT].num;
1066 slot_width = tdm_slot[TDM_QUAT].width;
1067 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1068 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1069 break;
1070 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
1071 slots = tdm_slot[TDM_QUAT].num;
1072 slot_width = tdm_slot[TDM_QUAT].width;
1073 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1074 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1075 break;
1076 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
1077 slots = tdm_slot[TDM_QUAT].num;
1078 slot_width = tdm_slot[TDM_QUAT].width;
1079 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1080 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1081 break;
1082 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
1083 slots = tdm_slot[TDM_QUAT].num;
1084 slot_width = tdm_slot[TDM_QUAT].width;
1085 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1086 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1087 break;
1088 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
1089 slots = tdm_slot[TDM_QUAT].num;
1090 slot_width = tdm_slot[TDM_QUAT].width;
1091 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1092 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1093 break;
1094 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
1095 slots = tdm_slot[TDM_QUAT].num;
1096 slot_width = tdm_slot[TDM_QUAT].width;
1097 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1098 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1099 break;
1100 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
1101 slots = tdm_slot[TDM_QUAT].num;
1102 slot_width = tdm_slot[TDM_QUAT].width;
1103 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1104 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1105 break;
1106 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
1107 slots = tdm_slot[TDM_QUAT].num;
1108 slot_width = tdm_slot[TDM_QUAT].width;
1109 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1110 tdm_interface = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1111 break;
1112 case AFE_PORT_ID_QUINARY_TDM_RX:
1113 slots = tdm_slot[TDM_QUIN].num;
1114 slot_width = tdm_slot[TDM_QUIN].width;
1115 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1116 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1117 break;
1118 case AFE_PORT_ID_QUINARY_TDM_RX_1:
1119 slots = tdm_slot[TDM_QUIN].num;
1120 slot_width = tdm_slot[TDM_QUIN].width;
1121 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1122 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1123 break;
1124 case AFE_PORT_ID_QUINARY_TDM_RX_2:
1125 slots = tdm_slot[TDM_QUIN].num;
1126 slot_width = tdm_slot[TDM_QUIN].width;
1127 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1128 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1129 break;
1130 case AFE_PORT_ID_QUINARY_TDM_RX_3:
1131 slots = tdm_slot[TDM_QUIN].num;
1132 slot_width = tdm_slot[TDM_QUIN].width;
1133 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1134 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1135 break;
1136 case AFE_PORT_ID_QUINARY_TDM_RX_4:
1137 slots = tdm_slot[TDM_QUIN].num;
1138 slot_width = tdm_slot[TDM_QUIN].width;
1139 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1140 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1141 break;
1142 case AFE_PORT_ID_QUINARY_TDM_RX_5:
1143 slots = tdm_slot[TDM_QUIN].num;
1144 slot_width = tdm_slot[TDM_QUIN].width;
1145 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1146 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1147 break;
1148 case AFE_PORT_ID_QUINARY_TDM_RX_6:
1149 slots = tdm_slot[TDM_QUIN].num;
1150 slot_width = tdm_slot[TDM_QUIN].width;
1151 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1152 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1153 break;
1154 case AFE_PORT_ID_QUINARY_TDM_RX_7:
1155 slots = tdm_slot[TDM_QUIN].num;
1156 slot_width = tdm_slot[TDM_QUIN].width;
1157 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1158 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1159 break;
1160 case AFE_PORT_ID_QUINARY_TDM_TX:
1161 slots = tdm_slot[TDM_QUIN].num;
1162 slot_width = tdm_slot[TDM_QUIN].width;
1163 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1164 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1165 break;
1166 case AFE_PORT_ID_QUINARY_TDM_TX_1:
1167 slots = tdm_slot[TDM_QUIN].num;
1168 slot_width = tdm_slot[TDM_QUIN].width;
1169 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1170 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1171 break;
1172 case AFE_PORT_ID_QUINARY_TDM_TX_2:
1173 slots = tdm_slot[TDM_QUIN].num;
1174 slot_width = tdm_slot[TDM_QUIN].width;
1175 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1176 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1177 break;
1178 case AFE_PORT_ID_QUINARY_TDM_TX_3:
1179 slots = tdm_slot[TDM_QUIN].num;
1180 slot_width = tdm_slot[TDM_QUIN].width;
1181 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1182 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1183 break;
1184 case AFE_PORT_ID_QUINARY_TDM_TX_4:
1185 slots = tdm_slot[TDM_QUIN].num;
1186 slot_width = tdm_slot[TDM_QUIN].width;
1187 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_4];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1188 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1189 break;
1190 case AFE_PORT_ID_QUINARY_TDM_TX_5:
1191 slots = tdm_slot[TDM_QUIN].num;
1192 slot_width = tdm_slot[TDM_QUIN].width;
1193 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_5];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1194 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1195 break;
1196 case AFE_PORT_ID_QUINARY_TDM_TX_6:
1197 slots = tdm_slot[TDM_QUIN].num;
1198 slot_width = tdm_slot[TDM_QUIN].width;
1199 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_6];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1200 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1201 break;
1202 case AFE_PORT_ID_QUINARY_TDM_TX_7:
1203 slots = tdm_slot[TDM_QUIN].num;
1204 slot_width = tdm_slot[TDM_QUIN].width;
1205 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_7];
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1206 tdm_interface = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1207 break;
1208 default:
1209 pr_err("%s: dai id 0x%x not supported\n",
1210 __func__, cpu_dai->id);
1211 return -EINVAL;
1212 }
1213
1214 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1215 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
1216 offset_channels++;
1217 else
1218 break;
1219 }
1220
1221 if (offset_channels == 0) {
1222 pr_err("%s: slot offset not supported, offset_channels %d\n",
1223 __func__, offset_channels);
1224 return -EINVAL;
1225 }
1226
1227 if (channels > offset_channels) {
1228 pr_err("%s: channels %d exceed offset_channels %d\n",
1229 __func__, channels, offset_channels);
1230 return -EINVAL;
1231 }
1232
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1233 slot_mask = tdm_param_set_slot_mask(cpu_dai->id,
1234 slot_width, slots, tdm_interface);
1235 pr_debug("%s: slot_mask :%x\n", __func__, slot_mask);
1236
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1237 if (!slot_mask) {
1238 pr_err("%s: invalid slot_mask 0x%x\n",
1239 __func__, slot_mask);
1240 return -EINVAL;
1241 }
1242
1243 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1244 pr_debug("%s: slot_width %d\n", __func__, slot_width);
1245 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
1246 slots, slot_width);
1247 if (ret < 0) {
1248 pr_err("%s: failed to set tdm slot, err:%d\n",
1249 __func__, ret);
1250 goto end;
1251 }
1252
1253 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
1254 channels, slot_offset);
1255 if (ret < 0) {
1256 pr_err("%s: failed to set channel map, err:%d\n",
1257 __func__, ret);
1258 goto end;
1259 }
1260 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]1261
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1262 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
1263 slots, slot_width);
1264 if (ret < 0) {
1265 pr_err("%s: failed to set tdm slot, err:%d\n",
1266 __func__, ret);
1267 goto end;
1268 }
1269
1270 ret = snd_soc_dai_set_channel_map(cpu_dai, channels,
1271 slot_offset, 0, NULL);
1272 if (ret < 0) {
1273 pr_err("%s: failed to set channel map, err:%d\n",
1274 __func__, ret);
1275 goto end;
1276 }
1277 } else {
1278 ret = -EINVAL;
1279 pr_err("%s: invalid use case, err:%d\n",
1280 __func__, ret);
1281 goto end;
1282 }
1283
1284 rate = params_rate(params);
1285 clk_freq = rate * slot_width * slots;
1286 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
1287 if (ret < 0) {
1288 pr_err("%s: failed to set tdm clk, err:%d\n",
1289 __func__, ret);
1290 }
1291
1292end:
1293 return ret;
1294}
1295EXPORT_SYMBOL(msm_tdm_snd_hw_params);
1296
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1297static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1298 struct snd_ctl_elem_value *ucontrol)
1299{
1300 pr_debug("%s: proxy_rx channels = %d\n",
1301 __func__, proxy_rx_cfg.channels);
1302 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1303
1304 return 0;
1305}
1306
1307static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1308 struct snd_ctl_elem_value *ucontrol)
1309{
1310 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1311 pr_debug("%s: proxy_rx channels = %d\n",
1312 __func__, proxy_rx_cfg.channels);
1313
1314 return 1;
1315}
1316
1317static int tdm_get_sample_rate(int value)
1318{
1319 int sample_rate = 0;
1320
1321 switch (value) {
1322 case 0:
1323 sample_rate = SAMPLING_RATE_8KHZ;
1324 break;
1325 case 1:
1326 sample_rate = SAMPLING_RATE_16KHZ;
1327 break;
1328 case 2:
1329 sample_rate = SAMPLING_RATE_32KHZ;
1330 break;
1331 case 3:
1332 sample_rate = SAMPLING_RATE_44P1KHZ;
1333 break;
1334 case 4:
1335 sample_rate = SAMPLING_RATE_48KHZ;
1336 break;
1337 case 5:
1338 sample_rate = SAMPLING_RATE_96KHZ;
1339 break;
1340 case 6:
1341 sample_rate = SAMPLING_RATE_192KHZ;
1342 break;
1343 case 7:
1344 sample_rate = SAMPLING_RATE_352P8KHZ;
1345 break;
1346 case 8:
1347 sample_rate = SAMPLING_RATE_384KHZ;
1348 break;
1349 default:
1350 sample_rate = SAMPLING_RATE_48KHZ;
1351 break;
1352 }
1353 return sample_rate;
1354}
1355
1356static int tdm_get_sample_rate_val(int sample_rate)
1357{
1358 int sample_rate_val = 0;
1359
1360 switch (sample_rate) {
1361 case SAMPLING_RATE_8KHZ:
1362 sample_rate_val = 0;
1363 break;
1364 case SAMPLING_RATE_16KHZ:
1365 sample_rate_val = 1;
1366 break;
1367 case SAMPLING_RATE_32KHZ:
1368 sample_rate_val = 2;
1369 break;
1370 case SAMPLING_RATE_44P1KHZ:
1371 sample_rate_val = 3;
1372 break;
1373 case SAMPLING_RATE_48KHZ:
1374 sample_rate_val = 4;
1375 break;
1376 case SAMPLING_RATE_96KHZ:
1377 sample_rate_val = 5;
1378 break;
1379 case SAMPLING_RATE_192KHZ:
1380 sample_rate_val = 6;
1381 break;
1382 case SAMPLING_RATE_352P8KHZ:
1383 sample_rate_val = 7;
1384 break;
1385 case SAMPLING_RATE_384KHZ:
1386 sample_rate_val = 8;
1387 break;
1388 default:
1389 sample_rate_val = 4;
1390 break;
1391 }
1392 return sample_rate_val;
1393}
1394
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1395static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1396{
1397 int mode;
1398
1399 if (strnstr(kcontrol->id.name, "PRI",
1400 sizeof(kcontrol->id.name))) {
1401 mode = TDM_PRI;
1402 } else if (strnstr(kcontrol->id.name, "SEC",
1403 sizeof(kcontrol->id.name))) {
1404 mode = TDM_SEC;
1405 } else if (strnstr(kcontrol->id.name, "TERT",
1406 sizeof(kcontrol->id.name))) {
1407 mode = TDM_TERT;
1408 } else if (strnstr(kcontrol->id.name, "QUAT",
1409 sizeof(kcontrol->id.name))) {
1410 mode = TDM_QUAT;
1411 } else if (strnstr(kcontrol->id.name, "QUIN",
1412 sizeof(kcontrol->id.name))) {
1413 mode = TDM_QUIN;
1414 } else {
1415 pr_err("%s: unsupported mode in: %s\n",
1416 __func__, kcontrol->id.name);
1417 mode = -EINVAL;
1418 }
1419
1420 return mode;
1421}
1422
1423static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1424{
1425 int channel;
1426
1427 if (strnstr(kcontrol->id.name, "RX_0",
1428 sizeof(kcontrol->id.name)) ||
1429 strnstr(kcontrol->id.name, "TX_0",
1430 sizeof(kcontrol->id.name))) {
1431 channel = TDM_0;
1432 } else if (strnstr(kcontrol->id.name, "RX_1",
1433 sizeof(kcontrol->id.name)) ||
1434 strnstr(kcontrol->id.name, "TX_1",
1435 sizeof(kcontrol->id.name))) {
1436 channel = TDM_1;
1437 } else if (strnstr(kcontrol->id.name, "RX_2",
1438 sizeof(kcontrol->id.name)) ||
1439 strnstr(kcontrol->id.name, "TX_2",
1440 sizeof(kcontrol->id.name))) {
1441 channel = TDM_2;
1442 } else if (strnstr(kcontrol->id.name, "RX_3",
1443 sizeof(kcontrol->id.name)) ||
1444 strnstr(kcontrol->id.name, "TX_3",
1445 sizeof(kcontrol->id.name))) {
1446 channel = TDM_3;
1447 } else if (strnstr(kcontrol->id.name, "RX_4",
1448 sizeof(kcontrol->id.name)) ||
1449 strnstr(kcontrol->id.name, "TX_4",
1450 sizeof(kcontrol->id.name))) {
1451 channel = TDM_4;
1452 } else if (strnstr(kcontrol->id.name, "RX_5",
1453 sizeof(kcontrol->id.name)) ||
1454 strnstr(kcontrol->id.name, "TX_5",
1455 sizeof(kcontrol->id.name))) {
1456 channel = TDM_5;
1457 } else if (strnstr(kcontrol->id.name, "RX_6",
1458 sizeof(kcontrol->id.name)) ||
1459 strnstr(kcontrol->id.name, "TX_6",
1460 sizeof(kcontrol->id.name))) {
1461 channel = TDM_6;
1462 } else if (strnstr(kcontrol->id.name, "RX_7",
1463 sizeof(kcontrol->id.name)) ||
1464 strnstr(kcontrol->id.name, "TX_7",
1465 sizeof(kcontrol->id.name))) {
1466 channel = TDM_7;
1467 } else {
1468 pr_err("%s: unsupported channel in: %s\n",
1469 __func__, kcontrol->id.name);
1470 channel = -EINVAL;
1471 }
1472
1473 return channel;
1474}
1475
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1476static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1477 struct tdm_port *port)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1478{
1479 if (port) {
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1480 port->mode = tdm_get_mode(kcontrol);
1481 if (port->mode < 0)
1482 return port->mode;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1483
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1484 port->channel = tdm_get_channel(kcontrol);
1485 if (port->channel < 0)
1486 return port->channel;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1487 } else
1488 return -EINVAL;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1489
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1490 return 0;
1491}
1492
1493static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1494 struct snd_ctl_elem_value *ucontrol)
1495{
1496 struct tdm_port port;
1497 int ret = tdm_get_port_idx(kcontrol, &port);
1498
1499 if (ret) {
1500 pr_err("%s: unsupported control: %s",
1501 __func__, kcontrol->id.name);
1502 } else {
1503 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1504 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1505
1506 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1507 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1508 ucontrol->value.enumerated.item[0]);
1509 }
1510 return ret;
1511}
1512
1513static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1514 struct snd_ctl_elem_value *ucontrol)
1515{
1516 struct tdm_port port;
1517 int ret = tdm_get_port_idx(kcontrol, &port);
1518
1519 if (ret) {
1520 pr_err("%s: unsupported control: %s",
1521 __func__, kcontrol->id.name);
1522 } else {
1523 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1524 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1525
1526 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1527 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1528 ucontrol->value.enumerated.item[0]);
1529 }
1530 return ret;
1531}
1532
1533static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1534 struct snd_ctl_elem_value *ucontrol)
1535{
1536 struct tdm_port port;
1537 int ret = tdm_get_port_idx(kcontrol, &port);
1538
1539 if (ret) {
1540 pr_err("%s: unsupported control: %s",
1541 __func__, kcontrol->id.name);
1542 } else {
1543 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1544 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1545
1546 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1547 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1548 ucontrol->value.enumerated.item[0]);
1549 }
1550 return ret;
1551}
1552
1553static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1554 struct snd_ctl_elem_value *ucontrol)
1555{
1556 struct tdm_port port;
1557 int ret = tdm_get_port_idx(kcontrol, &port);
1558
1559 if (ret) {
1560 pr_err("%s: unsupported control: %s",
1561 __func__, kcontrol->id.name);
1562 } else {
1563 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1564 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1565
1566 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1567 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1568 ucontrol->value.enumerated.item[0]);
1569 }
1570 return ret;
1571}
1572
1573static int tdm_get_format(int value)
1574{
1575 int format = 0;
1576
1577 switch (value) {
1578 case 0:
1579 format = SNDRV_PCM_FORMAT_S16_LE;
1580 break;
1581 case 1:
1582 format = SNDRV_PCM_FORMAT_S24_LE;
1583 break;
1584 case 2:
1585 format = SNDRV_PCM_FORMAT_S32_LE;
1586 break;
1587 default:
1588 format = SNDRV_PCM_FORMAT_S16_LE;
1589 break;
1590 }
1591 return format;
1592}
1593
1594static int tdm_get_format_val(int format)
1595{
1596 int value = 0;
1597
1598 switch (format) {
1599 case SNDRV_PCM_FORMAT_S16_LE:
1600 value = 0;
1601 break;
1602 case SNDRV_PCM_FORMAT_S24_LE:
1603 value = 1;
1604 break;
1605 case SNDRV_PCM_FORMAT_S32_LE:
1606 value = 2;
1607 break;
1608 default:
1609 value = 0;
1610 break;
1611 }
1612 return value;
1613}
1614
1615static int mi2s_get_format(int value)
1616{
1617 int format = 0;
1618
1619 switch (value) {
1620 case 0:
1621 format = SNDRV_PCM_FORMAT_S16_LE;
1622 break;
1623 case 1:
1624 format = SNDRV_PCM_FORMAT_S24_LE;
1625 break;
1626 case 2:
1627 format = SNDRV_PCM_FORMAT_S24_3LE;
1628 break;
1629 case 3:
1630 format = SNDRV_PCM_FORMAT_S32_LE;
1631 break;
1632 default:
1633 format = SNDRV_PCM_FORMAT_S16_LE;
1634 break;
1635 }
1636 return format;
1637}
1638
1639static int mi2s_get_format_value(int format)
1640{
1641 int value = 0;
1642
1643 switch (format) {
1644 case SNDRV_PCM_FORMAT_S16_LE:
1645 value = 0;
1646 break;
1647 case SNDRV_PCM_FORMAT_S24_LE:
1648 value = 1;
1649 break;
1650 case SNDRV_PCM_FORMAT_S24_3LE:
1651 value = 2;
1652 break;
1653 case SNDRV_PCM_FORMAT_S32_LE:
1654 value = 3;
1655 break;
1656 default:
1657 value = 0;
1658 break;
1659 }
1660 return value;
1661}
1662
1663static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1664 struct snd_ctl_elem_value *ucontrol)
1665{
1666 struct tdm_port port;
1667 int ret = tdm_get_port_idx(kcontrol, &port);
1668
1669 if (ret) {
1670 pr_err("%s: unsupported control: %s",
1671 __func__, kcontrol->id.name);
1672 } else {
1673 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1674 tdm_rx_cfg[port.mode][port.channel].bit_format);
1675
1676 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1677 tdm_rx_cfg[port.mode][port.channel].bit_format,
1678 ucontrol->value.enumerated.item[0]);
1679 }
1680 return ret;
1681}
1682
1683static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1684 struct snd_ctl_elem_value *ucontrol)
1685{
1686 struct tdm_port port;
1687 int ret = tdm_get_port_idx(kcontrol, &port);
1688
1689 if (ret) {
1690 pr_err("%s: unsupported control: %s",
1691 __func__, kcontrol->id.name);
1692 } else {
1693 tdm_rx_cfg[port.mode][port.channel].bit_format =
1694 tdm_get_format(ucontrol->value.enumerated.item[0]);
1695
1696 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1697 tdm_rx_cfg[port.mode][port.channel].bit_format,
1698 ucontrol->value.enumerated.item[0]);
1699 }
1700 return ret;
1701}
1702
1703static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_value *ucontrol)
1705{
1706 struct tdm_port port;
1707 int ret = tdm_get_port_idx(kcontrol, &port);
1708
1709 if (ret) {
1710 pr_err("%s: unsupported control: %s",
1711 __func__, kcontrol->id.name);
1712 } else {
1713 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1714 tdm_tx_cfg[port.mode][port.channel].bit_format);
1715
1716 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1717 tdm_tx_cfg[port.mode][port.channel].bit_format,
1718 ucontrol->value.enumerated.item[0]);
1719 }
1720 return ret;
1721}
1722
1723static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1724 struct snd_ctl_elem_value *ucontrol)
1725{
1726 struct tdm_port port;
1727 int ret = tdm_get_port_idx(kcontrol, &port);
1728
1729 if (ret) {
1730 pr_err("%s: unsupported control: %s",
1731 __func__, kcontrol->id.name);
1732 } else {
1733 tdm_tx_cfg[port.mode][port.channel].bit_format =
1734 tdm_get_format(ucontrol->value.enumerated.item[0]);
1735
1736 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1737 tdm_tx_cfg[port.mode][port.channel].bit_format,
1738 ucontrol->value.enumerated.item[0]);
1739 }
1740 return ret;
1741}
1742
1743static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1744 struct snd_ctl_elem_value *ucontrol)
1745{
1746 struct tdm_port port;
1747 int ret = tdm_get_port_idx(kcontrol, &port);
1748
1749 if (ret) {
1750 pr_err("%s: unsupported control: %s",
1751 __func__, kcontrol->id.name);
1752 } else {
1753
1754 ucontrol->value.enumerated.item[0] =
1755 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1756
1757 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1758 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1759 ucontrol->value.enumerated.item[0]);
1760 }
1761 return ret;
1762}
1763
1764static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1765 struct snd_ctl_elem_value *ucontrol)
1766{
1767 struct tdm_port port;
1768 int ret = tdm_get_port_idx(kcontrol, &port);
1769
1770 if (ret) {
1771 pr_err("%s: unsupported control: %s",
1772 __func__, kcontrol->id.name);
1773 } else {
1774 tdm_rx_cfg[port.mode][port.channel].channels =
1775 ucontrol->value.enumerated.item[0] + 1;
1776
1777 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1778 tdm_rx_cfg[port.mode][port.channel].channels,
1779 ucontrol->value.enumerated.item[0] + 1);
1780 }
1781 return ret;
1782}
1783
1784static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1785 struct snd_ctl_elem_value *ucontrol)
1786{
1787 struct tdm_port port;
1788 int ret = tdm_get_port_idx(kcontrol, &port);
1789
1790 if (ret) {
1791 pr_err("%s: unsupported control: %s",
1792 __func__, kcontrol->id.name);
1793 } else {
1794 ucontrol->value.enumerated.item[0] =
1795 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1796
1797 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1798 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1799 ucontrol->value.enumerated.item[0]);
1800 }
1801 return ret;
1802}
1803
1804static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1805 struct snd_ctl_elem_value *ucontrol)
1806{
1807 struct tdm_port port;
1808 int ret = tdm_get_port_idx(kcontrol, &port);
1809
1810 if (ret) {
1811 pr_err("%s: unsupported control: %s",
1812 __func__, kcontrol->id.name);
1813 } else {
1814 tdm_tx_cfg[port.mode][port.channel].channels =
1815 ucontrol->value.enumerated.item[0] + 1;
1816
1817 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1818 tdm_tx_cfg[port.mode][port.channel].channels,
1819 ucontrol->value.enumerated.item[0] + 1);
1820 }
1821 return ret;
1822}
1823
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1824static int tdm_get_slot_num_val(int slot_num)
1825{
1826 int slot_num_val;
1827
1828 switch (slot_num) {
1829 case 1:
1830 slot_num_val = 0;
1831 break;
1832 case 2:
1833 slot_num_val = 1;
1834 break;
1835 case 4:
1836 slot_num_val = 2;
1837 break;
1838 case 8:
1839 slot_num_val = 3;
1840 break;
1841 case 16:
1842 slot_num_val = 4;
1843 break;
1844 case 32:
1845 slot_num_val = 5;
1846 break;
1847 default:
1848 slot_num_val = 5;
1849 break;
1850 }
1851 return slot_num_val;
1852}
1853
1854static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1855 struct snd_ctl_elem_value *ucontrol)
1856{
1857 int mode = tdm_get_mode(kcontrol);
1858
1859 if (mode < 0) {
1860 pr_err("%s: unsupported control: %s\n",
1861 __func__, kcontrol->id.name);
1862 return mode;
1863 }
1864
1865 ucontrol->value.enumerated.item[0] =
1866 tdm_get_slot_num_val(tdm_slot[mode].num);
1867
1868 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1869 mode, tdm_slot[mode].num,
1870 ucontrol->value.enumerated.item[0]);
1871
1872 return 0;
1873}
1874
1875static int tdm_get_slot_num(int value)
1876{
1877 int slot_num;
1878
1879 switch (value) {
1880 case 0:
1881 slot_num = 1;
1882 break;
1883 case 1:
1884 slot_num = 2;
1885 break;
1886 case 2:
1887 slot_num = 4;
1888 break;
1889 case 3:
1890 slot_num = 8;
1891 break;
1892 case 4:
1893 slot_num = 16;
1894 break;
1895 case 5:
1896 slot_num = 32;
1897 break;
1898 default:
1899 slot_num = 8;
1900 break;
1901 }
1902 return slot_num;
1903}
1904
1905static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1906 struct snd_ctl_elem_value *ucontrol)
1907{
1908 int mode = tdm_get_mode(kcontrol);
1909
1910 if (mode < 0) {
1911 pr_err("%s: unsupported control: %s\n",
1912 __func__, kcontrol->id.name);
1913 return mode;
1914 }
1915
1916 tdm_slot[mode].num =
1917 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1918
1919 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1920 mode, tdm_slot[mode].num,
1921 ucontrol->value.enumerated.item[0]);
1922
1923 return 0;
1924}
1925
1926static int tdm_get_slot_width_val(int slot_width)
1927{
1928 int slot_width_val;
1929
1930 switch (slot_width) {
1931 case 16:
1932 slot_width_val = 0;
1933 break;
1934 case 24:
1935 slot_width_val = 1;
1936 break;
1937 case 32:
1938 slot_width_val = 2;
1939 break;
1940 default:
1941 slot_width_val = 2;
1942 break;
1943 }
1944 return slot_width_val;
1945}
1946
1947static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1948 struct snd_ctl_elem_value *ucontrol)
1949{
1950 int mode = tdm_get_mode(kcontrol);
1951
1952 if (mode < 0) {
1953 pr_err("%s: unsupported control: %s\n",
1954 __func__, kcontrol->id.name);
1955 return mode;
1956 }
1957
1958 ucontrol->value.enumerated.item[0] =
1959 tdm_get_slot_width_val(tdm_slot[mode].width);
1960
1961 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1962 mode, tdm_slot[mode].width,
1963 ucontrol->value.enumerated.item[0]);
1964
1965 return 0;
1966}
1967
1968static int tdm_get_slot_width(int value)
1969{
1970 int slot_width;
1971
1972 switch (value) {
1973 case 0:
1974 slot_width = 16;
1975 break;
1976 case 1:
1977 slot_width = 24;
1978 break;
1979 case 2:
1980 slot_width = 32;
1981 break;
1982 default:
1983 slot_width = 32;
1984 break;
1985 }
1986 return slot_width;
1987}
1988
1989static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1990 struct snd_ctl_elem_value *ucontrol)
1991{
1992 int mode = tdm_get_mode(kcontrol);
1993
1994 if (mode < 0) {
1995 pr_err("%s: unsupported control: %s\n",
1996 __func__, kcontrol->id.name);
1997 return mode;
1998 }
1999
2000 tdm_slot[mode].width =
2001 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
2002
2003 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
2004 mode, tdm_slot[mode].width,
2005 ucontrol->value.enumerated.item[0]);
2006
2007 return 0;
2008}
2009
2010static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
2012{
2013 unsigned int *slot_offset;
2014 int i;
2015 struct tdm_port port;
2016 int ret = tdm_get_port_idx(kcontrol, &port);
2017
2018 if (ret) {
2019 pr_err("%s: unsupported control: %s\n",
2020 __func__, kcontrol->id.name);
2021 } else {
2022 if (port.mode < TDM_INTERFACE_MAX &&
2023 port.channel < TDM_PORT_MAX) {
2024 slot_offset =
2025 tdm_rx_slot_offset[port.mode][port.channel];
2026 pr_debug("%s: mode = %d, channel = %d\n",
2027 __func__, port.mode, port.channel);
2028 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2029 ucontrol->value.integer.value[i] =
2030 slot_offset[i];
2031 pr_debug("%s: offset %d, value %d\n",
2032 __func__, i, slot_offset[i]);
2033 }
2034 } else {
2035 pr_err("%s: unsupported mode/channel\n", __func__);
2036 }
2037 }
2038 return ret;
2039}
2040
2041static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2042 struct snd_ctl_elem_value *ucontrol)
2043{
2044 unsigned int *slot_offset;
2045 int i;
2046 struct tdm_port port;
2047 int ret = tdm_get_port_idx(kcontrol, &port);
2048
2049 if (ret) {
2050 pr_err("%s: unsupported control: %s\n",
2051 __func__, kcontrol->id.name);
2052 } else {
2053 if (port.mode < TDM_INTERFACE_MAX &&
2054 port.channel < TDM_PORT_MAX) {
2055 slot_offset =
2056 tdm_rx_slot_offset[port.mode][port.channel];
2057 pr_debug("%s: mode = %d, channel = %d\n",
2058 __func__, port.mode, port.channel);
2059 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2060 slot_offset[i] =
2061 ucontrol->value.integer.value[i];
2062 pr_debug("%s: offset %d, value %d\n",
2063 __func__, i, slot_offset[i]);
2064 }
2065 } else {
2066 pr_err("%s: unsupported mode/channel\n", __func__);
2067 }
2068 }
2069 return ret;
2070}
2071
2072static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2073 struct snd_ctl_elem_value *ucontrol)
2074{
2075 unsigned int *slot_offset;
2076 int i;
2077 struct tdm_port port;
2078 int ret = tdm_get_port_idx(kcontrol, &port);
2079
2080 if (ret) {
2081 pr_err("%s: unsupported control: %s\n",
2082 __func__, kcontrol->id.name);
2083 } else {
2084 if (port.mode < TDM_INTERFACE_MAX &&
2085 port.channel < TDM_PORT_MAX) {
2086 slot_offset =
2087 tdm_tx_slot_offset[port.mode][port.channel];
2088 pr_debug("%s: mode = %d, channel = %d\n",
2089 __func__, port.mode, port.channel);
2090 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2091 ucontrol->value.integer.value[i] =
2092 slot_offset[i];
2093 pr_debug("%s: offset %d, value %d\n",
2094 __func__, i, slot_offset[i]);
2095 }
2096 } else {
2097 pr_err("%s: unsupported mode/channel\n", __func__);
2098 }
2099 }
2100 return ret;
2101}
2102
2103static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2104 struct snd_ctl_elem_value *ucontrol)
2105{
2106 unsigned int *slot_offset;
2107 int i;
2108 struct tdm_port port;
2109 int ret = tdm_get_port_idx(kcontrol, &port);
2110
2111 if (ret) {
2112 pr_err("%s: unsupported control: %s\n",
2113 __func__, kcontrol->id.name);
2114 } else {
2115 if (port.mode < TDM_INTERFACE_MAX &&
2116 port.channel < TDM_PORT_MAX) {
2117 slot_offset =
2118 tdm_tx_slot_offset[port.mode][port.channel];
2119 pr_debug("%s: mode = %d, channel = %d\n",
2120 __func__, port.mode, port.channel);
2121 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2122 slot_offset[i] =
2123 ucontrol->value.integer.value[i];
2124 pr_debug("%s: offset %d, value %d\n",
2125 __func__, i, slot_offset[i]);
2126 }
2127 } else {
2128 pr_err("%s: unsupported mode/channel\n", __func__);
2129 }
2130 }
2131 return ret;
2132}
2133
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2134static int aux_pcm_get_sample_rate(int value)
2135{
2136 int sample_rate;
2137
2138 switch (value) {
2139 case 1:
2140 sample_rate = SAMPLING_RATE_16KHZ;
2141 break;
2142 case 0:
2143 default:
2144 sample_rate = SAMPLING_RATE_8KHZ;
2145 break;
2146 }
2147 return sample_rate;
2148}
2149
2150static int aux_pcm_get_sample_rate_val(int sample_rate)
2151{
2152 int sample_rate_val;
2153
2154 switch (sample_rate) {
2155 case SAMPLING_RATE_16KHZ:
2156 sample_rate_val = 1;
2157 break;
2158 case SAMPLING_RATE_8KHZ:
2159 default:
2160 sample_rate_val = 0;
2161 break;
2162 }
2163 return sample_rate_val;
2164}
2165
2166static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2167{
2168 int idx;
2169
2170 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2171 sizeof("PRIM_AUX_PCM")))
2172 idx = PRIM_AUX_PCM;
2173 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2174 sizeof("SEC_AUX_PCM")))
2175 idx = SEC_AUX_PCM;
2176 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2177 sizeof("TERT_AUX_PCM")))
2178 idx = TERT_AUX_PCM;
2179 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2180 sizeof("QUAT_AUX_PCM")))
2181 idx = QUAT_AUX_PCM;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2182 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2183 sizeof("QUIN_AUX_PCM")))
2184 idx = QUIN_AUX_PCM;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2185 else {
2186 pr_err("%s: unsupported port: %s",
2187 __func__, kcontrol->id.name);
2188 idx = -EINVAL;
2189 }
2190
2191 return idx;
2192}
2193
2194static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2195 struct snd_ctl_elem_value *ucontrol)
2196{
2197 int idx = aux_pcm_get_port_idx(kcontrol);
2198
2199 if (idx < 0)
2200 return idx;
2201
2202 aux_pcm_rx_cfg[idx].sample_rate =
2203 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2204
2205 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2206 idx, aux_pcm_rx_cfg[idx].sample_rate,
2207 ucontrol->value.enumerated.item[0]);
2208
2209 return 0;
2210}
2211
2212static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2213 struct snd_ctl_elem_value *ucontrol)
2214{
2215 int idx = aux_pcm_get_port_idx(kcontrol);
2216
2217 if (idx < 0)
2218 return idx;
2219
2220 ucontrol->value.enumerated.item[0] =
2221 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2222
2223 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2224 idx, aux_pcm_rx_cfg[idx].sample_rate,
2225 ucontrol->value.enumerated.item[0]);
2226
2227 return 0;
2228}
2229
2230static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2231 struct snd_ctl_elem_value *ucontrol)
2232{
2233 int idx = aux_pcm_get_port_idx(kcontrol);
2234
2235 if (idx < 0)
2236 return idx;
2237
2238 aux_pcm_tx_cfg[idx].sample_rate =
2239 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2240
2241 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2242 idx, aux_pcm_tx_cfg[idx].sample_rate,
2243 ucontrol->value.enumerated.item[0]);
2244
2245 return 0;
2246}
2247
2248static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2249 struct snd_ctl_elem_value *ucontrol)
2250{
2251 int idx = aux_pcm_get_port_idx(kcontrol);
2252
2253 if (idx < 0)
2254 return idx;
2255
2256 ucontrol->value.enumerated.item[0] =
2257 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2258
2259 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2260 idx, aux_pcm_tx_cfg[idx].sample_rate,
2261 ucontrol->value.enumerated.item[0]);
2262
2263 return 0;
2264}
2265
2266static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2267{
2268 int idx;
2269
2270 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2271 sizeof("PRIM_MI2S_RX")))
2272 idx = PRIM_MI2S;
2273 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2274 sizeof("SEC_MI2S_RX")))
2275 idx = SEC_MI2S;
2276 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2277 sizeof("TERT_MI2S_RX")))
2278 idx = TERT_MI2S;
2279 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2280 sizeof("QUAT_MI2S_RX")))
2281 idx = QUAT_MI2S;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2282 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2283 sizeof("QUIN_MI2S_RX")))
2284 idx = QUIN_MI2S;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2285 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2286 sizeof("PRIM_MI2S_TX")))
2287 idx = PRIM_MI2S;
2288 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2289 sizeof("SEC_MI2S_TX")))
2290 idx = SEC_MI2S;
2291 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2292 sizeof("TERT_MI2S_TX")))
2293 idx = TERT_MI2S;
2294 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2295 sizeof("QUAT_MI2S_TX")))
2296 idx = QUAT_MI2S;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2297 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2298 sizeof("QUIN_MI2S_TX")))
2299 idx = QUIN_MI2S;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2300 else {
2301 pr_err("%s: unsupported channel: %s",
2302 __func__, kcontrol->id.name);
2303 idx = -EINVAL;
2304 }
2305
2306 return idx;
2307}
2308
2309static int mi2s_get_sample_rate_val(int sample_rate)
2310{
2311 int sample_rate_val;
2312
2313 switch (sample_rate) {
2314 case SAMPLING_RATE_8KHZ:
2315 sample_rate_val = 0;
2316 break;
2317 case SAMPLING_RATE_16KHZ:
2318 sample_rate_val = 1;
2319 break;
2320 case SAMPLING_RATE_32KHZ:
2321 sample_rate_val = 2;
2322 break;
2323 case SAMPLING_RATE_44P1KHZ:
2324 sample_rate_val = 3;
2325 break;
2326 case SAMPLING_RATE_48KHZ:
2327 sample_rate_val = 4;
2328 break;
2329 case SAMPLING_RATE_96KHZ:
2330 sample_rate_val = 5;
2331 break;
2332 case SAMPLING_RATE_192KHZ:
2333 sample_rate_val = 6;
2334 break;
2335 default:
2336 sample_rate_val = 4;
2337 break;
2338 }
2339 return sample_rate_val;
2340}
2341
2342static int mi2s_get_sample_rate(int value)
2343{
2344 int sample_rate;
2345
2346 switch (value) {
2347 case 0:
2348 sample_rate = SAMPLING_RATE_8KHZ;
2349 break;
2350 case 1:
2351 sample_rate = SAMPLING_RATE_16KHZ;
2352 break;
2353 case 2:
2354 sample_rate = SAMPLING_RATE_32KHZ;
2355 break;
2356 case 3:
2357 sample_rate = SAMPLING_RATE_44P1KHZ;
2358 break;
2359 case 4:
2360 sample_rate = SAMPLING_RATE_48KHZ;
2361 break;
2362 case 5:
2363 sample_rate = SAMPLING_RATE_96KHZ;
2364 break;
2365 case 6:
2366 sample_rate = SAMPLING_RATE_192KHZ;
2367 break;
2368 default:
2369 sample_rate = SAMPLING_RATE_48KHZ;
2370 break;
2371 }
2372 return sample_rate;
2373}
2374
2375static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2376 struct snd_ctl_elem_value *ucontrol)
2377{
2378 int idx = mi2s_get_port_idx(kcontrol);
2379
2380 if (idx < 0)
2381 return idx;
2382
2383 mi2s_rx_cfg[idx].sample_rate =
2384 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2385
2386 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2387 idx, mi2s_rx_cfg[idx].sample_rate,
2388 ucontrol->value.enumerated.item[0]);
2389
2390 return 0;
2391}
2392
2393static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2394 struct snd_ctl_elem_value *ucontrol)
2395{
2396 int idx = mi2s_get_port_idx(kcontrol);
2397
2398 if (idx < 0)
2399 return idx;
2400
2401 ucontrol->value.enumerated.item[0] =
2402 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2403
2404 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2405 idx, mi2s_rx_cfg[idx].sample_rate,
2406 ucontrol->value.enumerated.item[0]);
2407
2408 return 0;
2409}
2410
2411static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2412 struct snd_ctl_elem_value *ucontrol)
2413{
2414 int idx = mi2s_get_port_idx(kcontrol);
2415
2416 if (idx < 0)
2417 return idx;
2418
2419 mi2s_tx_cfg[idx].sample_rate =
2420 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2421
2422 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2423 idx, mi2s_tx_cfg[idx].sample_rate,
2424 ucontrol->value.enumerated.item[0]);
2425
2426 return 0;
2427}
2428
2429static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2430 struct snd_ctl_elem_value *ucontrol)
2431{
2432 int idx = mi2s_get_port_idx(kcontrol);
2433
2434 if (idx < 0)
2435 return idx;
2436
2437 ucontrol->value.enumerated.item[0] =
2438 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2439
2440 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2441 idx, mi2s_tx_cfg[idx].sample_rate,
2442 ucontrol->value.enumerated.item[0]);
2443
2444 return 0;
2445}
2446
2447static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2448 struct snd_ctl_elem_value *ucontrol)
2449{
2450 int idx = mi2s_get_port_idx(kcontrol);
2451
2452 if (idx < 0)
2453 return idx;
2454
2455 mi2s_tx_cfg[idx].bit_format =
2456 mi2s_get_format(ucontrol->value.enumerated.item[0]);
2457
2458 pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
2459 idx, mi2s_tx_cfg[idx].bit_format,
2460 ucontrol->value.enumerated.item[0]);
2461
2462 return 0;
2463}
2464
2465static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2466 struct snd_ctl_elem_value *ucontrol)
2467{
2468 int idx = mi2s_get_port_idx(kcontrol);
2469
2470 if (idx < 0)
2471 return idx;
2472
2473 ucontrol->value.enumerated.item[0] =
2474 mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
2475
2476 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2477 idx, mi2s_tx_cfg[idx].bit_format,
2478 ucontrol->value.enumerated.item[0]);
2479
2480 return 0;
2481}
2482
2483static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2484 struct snd_ctl_elem_value *ucontrol)
2485{
2486 int idx = mi2s_get_port_idx(kcontrol);
2487
2488 if (idx < 0)
2489 return idx;
2490
2491 mi2s_rx_cfg[idx].bit_format =
2492 mi2s_get_format(ucontrol->value.enumerated.item[0]);
2493
2494 pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
2495 idx, mi2s_rx_cfg[idx].bit_format,
2496 ucontrol->value.enumerated.item[0]);
2497
2498 return 0;
2499}
2500
2501static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2502 struct snd_ctl_elem_value *ucontrol)
2503{
2504 int idx = mi2s_get_port_idx(kcontrol);
2505
2506 if (idx < 0)
2507 return idx;
2508
2509 ucontrol->value.enumerated.item[0] =
2510 mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
2511
2512 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2513 idx, mi2s_rx_cfg[idx].bit_format,
2514 ucontrol->value.enumerated.item[0]);
2515
2516 return 0;
2517}
2518
2519static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2520 struct snd_ctl_elem_value *ucontrol)
2521{
2522 int idx = mi2s_get_port_idx(kcontrol);
2523
2524 if (idx < 0)
2525 return idx;
2526
2527 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2528 idx, mi2s_rx_cfg[idx].channels);
2529 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2530
2531 return 0;
2532}
2533
2534static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2535 struct snd_ctl_elem_value *ucontrol)
2536{
2537 int idx = mi2s_get_port_idx(kcontrol);
2538
2539 if (idx < 0)
2540 return idx;
2541
2542 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2543 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2544 idx, mi2s_rx_cfg[idx].channels);
2545
2546 return 1;
2547}
2548
2549static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2550 struct snd_ctl_elem_value *ucontrol)
2551{
2552 int idx = mi2s_get_port_idx(kcontrol);
2553
2554 if (idx < 0)
2555 return idx;
2556
2557 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2558 idx, mi2s_tx_cfg[idx].channels);
2559 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2560
2561 return 0;
2562}
2563
2564static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2565 struct snd_ctl_elem_value *ucontrol)
2566{
2567 int idx = mi2s_get_port_idx(kcontrol);
2568
2569 if (idx < 0)
2570 return idx;
2571
2572 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2573 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2574 idx, mi2s_tx_cfg[idx].channels);
2575
2576 return 1;
2577}
2578
2579static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
2580 struct snd_ctl_elem_value *ucontrol)
2581{
2582 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
2583 usb_rx_cfg.channels);
2584 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
2585 return 0;
2586}
2587
2588static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
2589 struct snd_ctl_elem_value *ucontrol)
2590{
2591 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
2592
2593 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
2594 return 1;
2595}
2596
2597static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2598 struct snd_ctl_elem_value *ucontrol)
2599{
2600 int sample_rate_val;
2601
2602 switch (usb_rx_cfg.sample_rate) {
2603 case SAMPLING_RATE_384KHZ:
2604 sample_rate_val = 9;
2605 break;
2606 case SAMPLING_RATE_192KHZ:
2607 sample_rate_val = 8;
2608 break;
2609 case SAMPLING_RATE_96KHZ:
2610 sample_rate_val = 7;
2611 break;
2612 case SAMPLING_RATE_48KHZ:
2613 sample_rate_val = 6;
2614 break;
2615 case SAMPLING_RATE_44P1KHZ:
2616 sample_rate_val = 5;
2617 break;
2618 case SAMPLING_RATE_32KHZ:
2619 sample_rate_val = 4;
2620 break;
2621 case SAMPLING_RATE_22P05KHZ:
2622 sample_rate_val = 3;
2623 break;
2624 case SAMPLING_RATE_16KHZ:
2625 sample_rate_val = 2;
2626 break;
2627 case SAMPLING_RATE_11P025KHZ:
2628 sample_rate_val = 1;
2629 break;
2630 case SAMPLING_RATE_8KHZ:
2631 default:
2632 sample_rate_val = 0;
2633 break;
2634 }
2635
2636 ucontrol->value.integer.value[0] = sample_rate_val;
2637 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
2638 usb_rx_cfg.sample_rate);
2639 return 0;
2640}
2641
2642static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2643 struct snd_ctl_elem_value *ucontrol)
2644{
2645 switch (ucontrol->value.integer.value[0]) {
2646 case 9:
2647 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
2648 break;
2649 case 8:
2650 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
2651 break;
2652 case 7:
2653 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
2654 break;
2655 case 6:
2656 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2657 break;
2658 case 5:
2659 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
2660 break;
2661 case 4:
2662 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
2663 break;
2664 case 3:
2665 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
2666 break;
2667 case 2:
2668 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
2669 break;
2670 case 1:
2671 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
2672 break;
2673 case 0:
2674 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
2675 break;
2676 default:
2677 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2678 break;
2679 }
2680
2681 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
2682 __func__, ucontrol->value.integer.value[0],
2683 usb_rx_cfg.sample_rate);
2684 return 0;
2685}
2686
2687static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
2688 struct snd_ctl_elem_value *ucontrol)
2689{
2690 switch (usb_rx_cfg.bit_format) {
2691 case SNDRV_PCM_FORMAT_S32_LE:
2692 ucontrol->value.integer.value[0] = 3;
2693 break;
2694 case SNDRV_PCM_FORMAT_S24_3LE:
2695 ucontrol->value.integer.value[0] = 2;
2696 break;
2697 case SNDRV_PCM_FORMAT_S24_LE:
2698 ucontrol->value.integer.value[0] = 1;
2699 break;
2700 case SNDRV_PCM_FORMAT_S16_LE:
2701 default:
2702 ucontrol->value.integer.value[0] = 0;
2703 break;
2704 }
2705
2706 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
2707 __func__, usb_rx_cfg.bit_format,
2708 ucontrol->value.integer.value[0]);
2709 return 0;
2710}
2711
2712static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
2713 struct snd_ctl_elem_value *ucontrol)
2714{
2715 int rc = 0;
2716
2717 switch (ucontrol->value.integer.value[0]) {
2718 case 3:
2719 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
2720 break;
2721 case 2:
2722 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2723 break;
2724 case 1:
2725 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
2726 break;
2727 case 0:
2728 default:
2729 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2730 break;
2731 }
2732 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
2733 __func__, usb_rx_cfg.bit_format,
2734 ucontrol->value.integer.value[0]);
2735
2736 return rc;
2737}
2738
2739static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
2740 struct snd_ctl_elem_value *ucontrol)
2741{
2742 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
2743 usb_tx_cfg.channels);
2744 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
2745 return 0;
2746}
2747
2748static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
2749 struct snd_ctl_elem_value *ucontrol)
2750{
2751 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
2752
2753 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
2754 return 1;
2755}
2756
2757static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2758 struct snd_ctl_elem_value *ucontrol)
2759{
2760 int sample_rate_val;
2761
2762 switch (usb_tx_cfg.sample_rate) {
2763 case SAMPLING_RATE_384KHZ:
2764 sample_rate_val = 9;
2765 break;
2766 case SAMPLING_RATE_192KHZ:
2767 sample_rate_val = 8;
2768 break;
2769 case SAMPLING_RATE_96KHZ:
2770 sample_rate_val = 7;
2771 break;
2772 case SAMPLING_RATE_48KHZ:
2773 sample_rate_val = 6;
2774 break;
2775 case SAMPLING_RATE_44P1KHZ:
2776 sample_rate_val = 5;
2777 break;
2778 case SAMPLING_RATE_32KHZ:
2779 sample_rate_val = 4;
2780 break;
2781 case SAMPLING_RATE_22P05KHZ:
2782 sample_rate_val = 3;
2783 break;
2784 case SAMPLING_RATE_16KHZ:
2785 sample_rate_val = 2;
2786 break;
2787 case SAMPLING_RATE_11P025KHZ:
2788 sample_rate_val = 1;
2789 break;
2790 case SAMPLING_RATE_8KHZ:
2791 sample_rate_val = 0;
2792 break;
2793 default:
2794 sample_rate_val = 6;
2795 break;
2796 }
2797
2798 ucontrol->value.integer.value[0] = sample_rate_val;
2799 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
2800 usb_tx_cfg.sample_rate);
2801 return 0;
2802}
2803
2804static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2805 struct snd_ctl_elem_value *ucontrol)
2806{
2807 switch (ucontrol->value.integer.value[0]) {
2808 case 9:
2809 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
2810 break;
2811 case 8:
2812 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
2813 break;
2814 case 7:
2815 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
2816 break;
2817 case 6:
2818 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2819 break;
2820 case 5:
2821 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
2822 break;
2823 case 4:
2824 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
2825 break;
2826 case 3:
2827 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
2828 break;
2829 case 2:
2830 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
2831 break;
2832 case 1:
2833 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
2834 break;
2835 case 0:
2836 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
2837 break;
2838 default:
2839 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2840 break;
2841 }
2842
2843 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
2844 __func__, ucontrol->value.integer.value[0],
2845 usb_tx_cfg.sample_rate);
2846 return 0;
2847}
2848
2849static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
2850 struct snd_ctl_elem_value *ucontrol)
2851{
2852 switch (usb_tx_cfg.bit_format) {
2853 case SNDRV_PCM_FORMAT_S32_LE:
2854 ucontrol->value.integer.value[0] = 3;
2855 break;
2856 case SNDRV_PCM_FORMAT_S24_3LE:
2857 ucontrol->value.integer.value[0] = 2;
2858 break;
2859 case SNDRV_PCM_FORMAT_S24_LE:
2860 ucontrol->value.integer.value[0] = 1;
2861 break;
2862 case SNDRV_PCM_FORMAT_S16_LE:
2863 default:
2864 ucontrol->value.integer.value[0] = 0;
2865 break;
2866 }
2867
2868 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2869 __func__, usb_tx_cfg.bit_format,
2870 ucontrol->value.integer.value[0]);
2871 return 0;
2872}
2873
2874static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
2875 struct snd_ctl_elem_value *ucontrol)
2876{
2877 int rc = 0;
2878
2879 switch (ucontrol->value.integer.value[0]) {
2880 case 3:
2881 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
2882 break;
2883 case 2:
2884 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2885 break;
2886 case 1:
2887 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
2888 break;
2889 case 0:
2890 default:
2891 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2892 break;
2893 }
2894 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2895 __func__, usb_tx_cfg.bit_format,
2896 ucontrol->value.integer.value[0]);
2897
2898 return rc;
2899}
2900
2901static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
2902{
2903 int idx;
2904
2905 if (strnstr(kcontrol->id.name, "Display Port RX",
2906 sizeof("Display Port RX")))
2907 idx = DP_RX_IDX;
2908 else {
2909 pr_err("%s: unsupported BE: %s",
2910 __func__, kcontrol->id.name);
2911 idx = -EINVAL;
2912 }
2913
2914 return idx;
2915}
2916
2917static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
2918 struct snd_ctl_elem_value *ucontrol)
2919{
2920 int idx = ext_disp_get_port_idx(kcontrol);
2921
2922 if (idx < 0)
2923 return idx;
2924
2925 switch (ext_disp_rx_cfg[idx].bit_format) {
2926 case SNDRV_PCM_FORMAT_S24_LE:
2927 ucontrol->value.integer.value[0] = 1;
2928 break;
2929
2930 case SNDRV_PCM_FORMAT_S16_LE:
2931 default:
2932 ucontrol->value.integer.value[0] = 0;
2933 break;
2934 }
2935
2936 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2937 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2938 ucontrol->value.integer.value[0]);
2939 return 0;
2940}
2941
2942static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
2943 struct snd_ctl_elem_value *ucontrol)
2944{
2945 int idx = ext_disp_get_port_idx(kcontrol);
2946
2947 if (idx < 0)
2948 return idx;
2949
2950 switch (ucontrol->value.integer.value[0]) {
2951 case 1:
2952 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
2953 break;
2954 case 0:
2955 default:
2956 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
2957 break;
2958 }
2959 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2960 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2961 ucontrol->value.integer.value[0]);
2962
2963 return 0;
2964}
2965
2966static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
2967 struct snd_ctl_elem_value *ucontrol)
2968{
2969 int idx = ext_disp_get_port_idx(kcontrol);
2970
2971 if (idx < 0)
2972 return idx;
2973
2974 ucontrol->value.integer.value[0] =
2975 ext_disp_rx_cfg[idx].channels - 2;
2976
2977 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2978 idx, ext_disp_rx_cfg[idx].channels);
2979
2980 return 0;
2981}
2982
2983static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
2984 struct snd_ctl_elem_value *ucontrol)
2985{
2986 int idx = ext_disp_get_port_idx(kcontrol);
2987
2988 if (idx < 0)
2989 return idx;
2990
2991 ext_disp_rx_cfg[idx].channels =
2992 ucontrol->value.integer.value[0] + 2;
2993
2994 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2995 idx, ext_disp_rx_cfg[idx].channels);
2996 return 1;
2997}
2998
2999static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
3000 struct snd_ctl_elem_value *ucontrol)
3001{
3002 int sample_rate_val;
3003 int idx = ext_disp_get_port_idx(kcontrol);
3004
3005 if (idx < 0)
3006 return idx;
3007
3008 switch (ext_disp_rx_cfg[idx].sample_rate) {
3009 case SAMPLING_RATE_192KHZ:
3010 sample_rate_val = 2;
3011 break;
3012
3013 case SAMPLING_RATE_96KHZ:
3014 sample_rate_val = 1;
3015 break;
3016
3017 case SAMPLING_RATE_48KHZ:
3018 default:
3019 sample_rate_val = 0;
3020 break;
3021 }
3022
3023 ucontrol->value.integer.value[0] = sample_rate_val;
3024 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
3025 idx, ext_disp_rx_cfg[idx].sample_rate);
3026
3027 return 0;
3028}
3029
3030static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
3031 struct snd_ctl_elem_value *ucontrol)
3032{
3033 int idx = ext_disp_get_port_idx(kcontrol);
3034
3035 if (idx < 0)
3036 return idx;
3037
3038 switch (ucontrol->value.integer.value[0]) {
3039 case 2:
3040 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
3041 break;
3042 case 1:
3043 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
3044 break;
3045 case 0:
3046 default:
3047 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
3048 break;
3049 }
3050
3051 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
3052 __func__, ucontrol->value.integer.value[0], idx,
3053 ext_disp_rx_cfg[idx].sample_rate);
3054 return 0;
3055}
3056
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]3057static int msm_qos_ctl_get(struct snd_kcontrol *kcontrol,
3058 struct snd_ctl_elem_value *ucontrol)
3059{
3060 ucontrol->value.enumerated.item[0] = qos_vote_status;
3061
3062 return 0;
3063}
3064
3065static int msm_qos_ctl_put(struct snd_kcontrol *kcontrol,
3066 struct snd_ctl_elem_value *ucontrol)
3067{
3068 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
3069 struct snd_soc_card *card = codec->component.card;
3070 const char *fe_name = MSM_DAILINK_NAME(LowLatency);
3071 struct snd_soc_pcm_runtime *rtd;
3072 struct snd_pcm_substream *substream;
3073 s32 usecs;
3074
3075 rtd = snd_soc_get_pcm_runtime(card, fe_name);
3076 if (!rtd) {
3077 pr_err("%s: fail to get pcm runtime for %s\n",
3078 __func__, fe_name);
3079 return -EINVAL;
3080 }
3081
3082 substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
3083 if (!substream) {
3084 pr_err("%s: substream is null\n", __func__);
3085 return -EINVAL;
3086 }
3087
3088 qos_vote_status = ucontrol->value.enumerated.item[0];
3089 if (qos_vote_status) {
3090 if (pm_qos_request_active(&substream->latency_pm_qos_req))
3091 pm_qos_remove_request(&substream->latency_pm_qos_req);
3092 if (!substream->runtime) {
3093 pr_err("%s: runtime is null\n", __func__);
3094 return -EINVAL;
3095 }
3096 usecs = MSM_LL_QOS_VALUE;
3097 if (usecs >= 0)
3098 pm_qos_add_request(&substream->latency_pm_qos_req,
3099 PM_QOS_CPU_DMA_LATENCY, usecs);
3100 } else {
3101 if (pm_qos_request_active(&substream->latency_pm_qos_req))
3102 pm_qos_remove_request(&substream->latency_pm_qos_req);
3103 }
3104
3105 return 0;
3106}
3107
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3108const struct snd_kcontrol_new msm_common_snd_controls[] = {
3109 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
3110 proxy_rx_ch_get, proxy_rx_ch_put),
3111 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3112 aux_pcm_rx_sample_rate_get,
3113 aux_pcm_rx_sample_rate_put),
3114 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3115 aux_pcm_rx_sample_rate_get,
3116 aux_pcm_rx_sample_rate_put),
3117 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3118 aux_pcm_rx_sample_rate_get,
3119 aux_pcm_rx_sample_rate_put),
3120 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3121 aux_pcm_rx_sample_rate_get,
3122 aux_pcm_rx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3123 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3124 aux_pcm_rx_sample_rate_get,
3125 aux_pcm_rx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3126 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3127 aux_pcm_tx_sample_rate_get,
3128 aux_pcm_tx_sample_rate_put),
3129 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3130 aux_pcm_tx_sample_rate_get,
3131 aux_pcm_tx_sample_rate_put),
3132 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3133 aux_pcm_tx_sample_rate_get,
3134 aux_pcm_tx_sample_rate_put),
3135 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3136 aux_pcm_tx_sample_rate_get,
3137 aux_pcm_tx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3138 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3139 aux_pcm_tx_sample_rate_get,
3140 aux_pcm_tx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3141 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3142 mi2s_rx_sample_rate_get,
3143 mi2s_rx_sample_rate_put),
3144 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3145 mi2s_rx_sample_rate_get,
3146 mi2s_rx_sample_rate_put),
3147 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3148 mi2s_rx_sample_rate_get,
3149 mi2s_rx_sample_rate_put),
3150 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3151 mi2s_rx_sample_rate_get,
3152 mi2s_rx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3153 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3154 mi2s_rx_sample_rate_get,
3155 mi2s_rx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3156 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3157 mi2s_tx_sample_rate_get,
3158 mi2s_tx_sample_rate_put),
3159 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3160 mi2s_tx_sample_rate_get,
3161 mi2s_tx_sample_rate_put),
3162 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3163 mi2s_tx_sample_rate_get,
3164 mi2s_tx_sample_rate_put),
3165 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3166 mi2s_tx_sample_rate_get,
3167 mi2s_tx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3168 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3169 mi2s_tx_sample_rate_get,
3170 mi2s_tx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3171 SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
3172 mi2s_rx_format_get,
3173 mi2s_rx_format_put),
3174 SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
3175 mi2s_rx_format_get,
3176 mi2s_rx_format_put),
3177 SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
3178 mi2s_rx_format_get,
3179 mi2s_rx_format_put),
3180 SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
3181 mi2s_rx_format_get,
3182 mi2s_rx_format_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3183 SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
3184 mi2s_rx_format_get,
3185 mi2s_rx_format_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3186 SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
3187 mi2s_tx_format_get,
3188 mi2s_tx_format_put),
3189 SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
3190 mi2s_tx_format_get,
3191 mi2s_tx_format_put),
3192 SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
3193 mi2s_tx_format_get,
3194 mi2s_tx_format_put),
3195 SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
3196 mi2s_tx_format_get,
3197 mi2s_tx_format_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3198 SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
3199 mi2s_tx_format_get,
3200 mi2s_tx_format_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3201 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3202 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3203 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3204 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3205 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3206 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3207 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3208 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3209 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3210 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3211 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3212 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3213 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3214 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3215 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3216 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3217 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3218 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3219 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3220 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3221 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
3222 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
3223 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
3224 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
3225 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
3226 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
3227 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
3228 usb_audio_rx_format_get, usb_audio_rx_format_put),
3229 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
3230 usb_audio_tx_format_get, usb_audio_tx_format_put),
3231 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
3232 ext_disp_rx_format_get, ext_disp_rx_format_put),
3233 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
3234 usb_audio_rx_sample_rate_get,
3235 usb_audio_rx_sample_rate_put),
3236 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
3237 usb_audio_tx_sample_rate_get,
3238 usb_audio_tx_sample_rate_put),
3239 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
3240 ext_disp_rx_sample_rate_get,
3241 ext_disp_rx_sample_rate_put),
3242 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3243 tdm_rx_sample_rate_get,
3244 tdm_rx_sample_rate_put),
3245 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3246 tdm_tx_sample_rate_get,
3247 tdm_tx_sample_rate_put),
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]3248 SOC_ENUM_EXT("PRI_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
3249 tdm_tx_sample_rate_get,
3250 tdm_tx_sample_rate_put),
3251 SOC_ENUM_EXT("PRI_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
3252 tdm_tx_sample_rate_get,
3253 tdm_tx_sample_rate_put),
3254 SOC_ENUM_EXT("PRI_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
3255 tdm_tx_sample_rate_get,
3256 tdm_tx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3257 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
3258 tdm_rx_format_get,
3259 tdm_rx_format_put),
3260 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
3261 tdm_tx_format_get,
3262 tdm_tx_format_put),
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]3263 SOC_ENUM_EXT("PRI_TDM_TX_1 Format", tdm_tx_format,
3264 tdm_tx_format_get,
3265 tdm_tx_format_put),
3266 SOC_ENUM_EXT("PRI_TDM_TX_2 Format", tdm_tx_format,
3267 tdm_tx_format_get,
3268 tdm_tx_format_put),
3269 SOC_ENUM_EXT("PRI_TDM_TX_3 Format", tdm_tx_format,
3270 tdm_tx_format_get,
3271 tdm_tx_format_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3272 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
3273 tdm_rx_ch_get,
3274 tdm_rx_ch_put),
3275 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
3276 tdm_tx_ch_get,
3277 tdm_tx_ch_put),
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]3278 SOC_ENUM_EXT("PRI_TDM_TX_1 Channels", tdm_tx_chs,
3279 tdm_tx_ch_get,
3280 tdm_tx_ch_put),
3281 SOC_ENUM_EXT("PRI_TDM_TX_2 Channels", tdm_tx_chs,
3282 tdm_tx_ch_get,
3283 tdm_tx_ch_put),
3284 SOC_ENUM_EXT("PRI_TDM_TX_3 Channels", tdm_tx_chs,
3285 tdm_tx_ch_get,
3286 tdm_tx_ch_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3287 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3288 tdm_rx_sample_rate_get,
3289 tdm_rx_sample_rate_put),
3290 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3291 tdm_tx_sample_rate_get,
3292 tdm_tx_sample_rate_put),
3293 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
3294 tdm_rx_format_get,
3295 tdm_rx_format_put),
3296 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
3297 tdm_tx_format_get,
3298 tdm_tx_format_put),
3299 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
3300 tdm_rx_ch_get,
3301 tdm_rx_ch_put),
3302 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
3303 tdm_tx_ch_get,
3304 tdm_tx_ch_put),
3305 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3306 tdm_rx_sample_rate_get,
3307 tdm_rx_sample_rate_put),
3308 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3309 tdm_tx_sample_rate_get,
3310 tdm_tx_sample_rate_put),
3311 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
3312 tdm_rx_format_get,
3313 tdm_rx_format_put),
3314 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
3315 tdm_tx_format_get,
3316 tdm_tx_format_put),
3317 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
3318 tdm_rx_ch_get,
3319 tdm_rx_ch_put),
3320 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
3321 tdm_tx_ch_get,
3322 tdm_tx_ch_put),
3323 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3324 tdm_rx_sample_rate_get,
3325 tdm_rx_sample_rate_put),
3326 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3327 tdm_tx_sample_rate_get,
3328 tdm_tx_sample_rate_put),
3329 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
3330 tdm_rx_format_get,
3331 tdm_rx_format_put),
3332 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
3333 tdm_tx_format_get,
3334 tdm_tx_format_put),
3335 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
3336 tdm_rx_ch_get,
3337 tdm_rx_ch_put),
3338 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
3339 tdm_tx_ch_get,
3340 tdm_tx_ch_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3341 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3342 tdm_rx_sample_rate_get,
3343 tdm_rx_sample_rate_put),
3344 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3345 tdm_tx_sample_rate_get,
3346 tdm_tx_sample_rate_put),
3347 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
3348 tdm_rx_format_get,
3349 tdm_rx_format_put),
3350 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
3351 tdm_tx_format_get,
3352 tdm_tx_format_put),
3353 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
3354 tdm_rx_ch_get,
3355 tdm_rx_ch_put),
3356 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
3357 tdm_tx_ch_get,
3358 tdm_tx_ch_put),
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]3359 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3360 tdm_slot_num_get, tdm_slot_num_put),
3361 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3362 tdm_slot_width_get, tdm_slot_width_put),
3363 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3364 tdm_slot_num_get, tdm_slot_num_put),
3365 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3366 tdm_slot_width_get, tdm_slot_width_put),
3367 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3368 tdm_slot_num_get, tdm_slot_num_put),
3369 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3370 tdm_slot_width_get, tdm_slot_width_put),
3371 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3372 tdm_slot_num_get, tdm_slot_num_put),
3373 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3374 tdm_slot_width_get, tdm_slot_width_put),
3375 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3376 tdm_slot_num_get, tdm_slot_num_put),
3377 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3378 tdm_slot_width_get, tdm_slot_width_put),
3379 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3380 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3381 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3382 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3383 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3384 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3385 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3386 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3387 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3388 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3389 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3390 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3391 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_4 SlotMapping",
3392 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3393 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3394 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_5 SlotMapping",
3395 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3396 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3397 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_6 SlotMapping",
3398 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3399 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3400 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_7 SlotMapping",
3401 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3402 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3403 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3404 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3405 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3406 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3407 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3408 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3409 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3410 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3411 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3412 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3413 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3414 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3415 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_4 SlotMapping",
3416 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3417 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3418 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_5 SlotMapping",
3419 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3420 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3421 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_6 SlotMapping",
3422 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3423 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3424 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_7 SlotMapping",
3425 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3426 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3427 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3428 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3429 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3430 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3431 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3432 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3433 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3434 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3435 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3436 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3437 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3438 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3439 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_4 SlotMapping",
3440 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3441 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3442 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_5 SlotMapping",
3443 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3444 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3445 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_6 SlotMapping",
3446 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3447 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3448 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_7 SlotMapping",
3449 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3450 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3451 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3452 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3453 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3454 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3455 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3456 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3457 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3458 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3459 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3460 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3461 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3462 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3463 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_4 SlotMapping",
3464 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3465 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3466 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_5 SlotMapping",
3467 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3468 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3469 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_6 SlotMapping",
3470 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3471 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3472 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_7 SlotMapping",
3473 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3474 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3475 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3476 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3477 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3478 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3479 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3480 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3481 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3482 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3483 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3484 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3485 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3486 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3487 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3488 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3489 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3490 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_5 SlotMapping",
3491 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3492 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3493 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_6 SlotMapping",
3494 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3495 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3496 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_7 SlotMapping",
3497 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3498 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3499 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3500 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3501 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3502 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3503 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3504 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3505 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3506 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3507 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3508 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3509 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3510 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3511 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_4 SlotMapping",
3512 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3513 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3514 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_5 SlotMapping",
3515 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3516 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3517 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_6 SlotMapping",
3518 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3519 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3520 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_7 SlotMapping",
3521 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3522 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3523 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3524 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3525 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3526 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3527 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3528 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3529 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3530 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3531 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3532 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3533 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3534 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3535 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_4 SlotMapping",
3536 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3537 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3538 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_5 SlotMapping",
3539 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3540 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3541 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_6 SlotMapping",
3542 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3543 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3544 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_7 SlotMapping",
3545 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3546 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3547 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3548 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3549 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3550 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3551 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3552 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3553 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3554 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3555 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3556 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3557 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3558 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3559 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_4 SlotMapping",
3560 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3561 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3562 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_5 SlotMapping",
3563 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3564 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3565 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_6 SlotMapping",
3566 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3567 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3568 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_7 SlotMapping",
3569 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3570 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3571 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3572 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3573 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3574 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3575 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3576 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3577 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3578 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3579 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3580 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3581 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3582 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3583 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_4 SlotMapping",
3584 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3585 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3586 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_5 SlotMapping",
3587 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3588 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3589 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_6 SlotMapping",
3590 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3591 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3592 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_7 SlotMapping",
3593 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3594 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3595 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3596 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3597 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3598 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3599 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3600 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3601 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3602 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3603 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3604 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3605 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3606 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3607 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_4 SlotMapping",
3608 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3609 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3610 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_5 SlotMapping",
3611 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3612 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3613 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_6 SlotMapping",
3614 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3615 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3616 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_7 SlotMapping",
3617 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3618 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]3619 SOC_ENUM_EXT("MultiMedia5_RX QOS Vote", qos_vote, msm_qos_ctl_get,
3620 msm_qos_ctl_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3621};
3622
3623/**
3624 * msm_common_snd_controls_size - to return controls size
3625 *
3626 * Return: returns size of common controls array
3627 */
3628int msm_common_snd_controls_size(void)
3629{
3630 return ARRAY_SIZE(msm_common_snd_controls);
3631}
3632EXPORT_SYMBOL(msm_common_snd_controls_size);
3633
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]3634void msm_set_codec_reg_done(bool done)
3635{
3636 codec_reg_done = done;
3637}
3638EXPORT_SYMBOL(msm_set_codec_reg_done);
3639
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3640static inline int param_is_mask(int p)
3641{
3642 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3643 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3644}
3645
3646static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3647 int n)
3648{
3649 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3650}
3651
3652static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
3653{
3654 if (bit >= SNDRV_MASK_MAX)
3655 return;
3656 if (param_is_mask(n)) {
3657 struct snd_mask *m = param_to_mask(p, n);
3658
3659 m->bits[0] = 0;
3660 m->bits[1] = 0;
3661 m->bits[bit >> 5] |= (1 << (bit & 31));
3662 }
3663}
3664
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]3665int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3666 struct snd_pcm_hw_params *params)
3667{
3668 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3669 struct snd_interval *rate = hw_param_interval(params,
3670 SNDRV_PCM_HW_PARAM_RATE);
3671 struct snd_interval *channels = hw_param_interval(params,
3672 SNDRV_PCM_HW_PARAM_CHANNELS);
3673 switch (cpu_dai->id) {
3674 case AFE_PORT_ID_PRIMARY_TDM_RX:
3675 channels->min = channels->max =
3676 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3677 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3678 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3679 rate->min = rate->max =
3680 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3681 break;
3682 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3683 channels->min = channels->max =
3684 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
3685 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3686 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
3687 rate->min = rate->max =
3688 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
3689 break;
3690 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3691 channels->min = channels->max =
3692 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
3693 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3694 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
3695 rate->min = rate->max =
3696 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
3697 break;
3698 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3699 channels->min = channels->max =
3700 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
3701 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3702 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
3703 rate->min = rate->max =
3704 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
3705 break;
3706 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
3707 channels->min = channels->max =
3708 tdm_rx_cfg[TDM_PRI][TDM_4].channels;
3709 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3710 tdm_rx_cfg[TDM_PRI][TDM_4].bit_format);
3711 rate->min = rate->max =
3712 tdm_rx_cfg[TDM_PRI][TDM_4].sample_rate;
3713 break;
3714 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
3715 channels->min = channels->max =
3716 tdm_rx_cfg[TDM_PRI][TDM_5].channels;
3717 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3718 tdm_rx_cfg[TDM_PRI][TDM_5].bit_format);
3719 rate->min = rate->max =
3720 tdm_rx_cfg[TDM_PRI][TDM_5].sample_rate;
3721 break;
3722 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
3723 channels->min = channels->max =
3724 tdm_rx_cfg[TDM_PRI][TDM_6].channels;
3725 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3726 tdm_rx_cfg[TDM_PRI][TDM_6].bit_format);
3727 rate->min = rate->max =
3728 tdm_rx_cfg[TDM_PRI][TDM_6].sample_rate;
3729 break;
3730 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
3731 channels->min = channels->max =
3732 tdm_rx_cfg[TDM_PRI][TDM_7].channels;
3733 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3734 tdm_rx_cfg[TDM_PRI][TDM_7].bit_format);
3735 rate->min = rate->max =
3736 tdm_rx_cfg[TDM_PRI][TDM_7].sample_rate;
3737 break;
3738 case AFE_PORT_ID_PRIMARY_TDM_TX:
3739 channels->min = channels->max =
3740 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3741 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3742 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3743 rate->min = rate->max =
3744 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3745 break;
3746 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3747 channels->min = channels->max =
3748 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
3749 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3750 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
3751 rate->min = rate->max =
3752 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
3753 break;
3754 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3755 channels->min = channels->max =
3756 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
3757 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3758 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
3759 rate->min = rate->max =
3760 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
3761 break;
3762 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3763 channels->min = channels->max =
3764 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
3765 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3766 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
3767 rate->min = rate->max =
3768 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
3769 break;
3770 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
3771 channels->min = channels->max =
3772 tdm_tx_cfg[TDM_PRI][TDM_4].channels;
3773 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3774 tdm_tx_cfg[TDM_PRI][TDM_4].bit_format);
3775 rate->min = rate->max =
3776 tdm_tx_cfg[TDM_PRI][TDM_4].sample_rate;
3777 break;
3778 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
3779 channels->min = channels->max =
3780 tdm_tx_cfg[TDM_PRI][TDM_5].channels;
3781 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3782 tdm_tx_cfg[TDM_PRI][TDM_5].bit_format);
3783 rate->min = rate->max =
3784 tdm_tx_cfg[TDM_PRI][TDM_5].sample_rate;
3785 break;
3786 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
3787 channels->min = channels->max =
3788 tdm_tx_cfg[TDM_PRI][TDM_6].channels;
3789 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3790 tdm_tx_cfg[TDM_PRI][TDM_6].bit_format);
3791 rate->min = rate->max =
3792 tdm_tx_cfg[TDM_PRI][TDM_6].sample_rate;
3793 break;
3794 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
3795 channels->min = channels->max =
3796 tdm_tx_cfg[TDM_PRI][TDM_7].channels;
3797 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3798 tdm_tx_cfg[TDM_PRI][TDM_7].bit_format);
3799 rate->min = rate->max =
3800 tdm_tx_cfg[TDM_PRI][TDM_7].sample_rate;
3801 break;
3802 case AFE_PORT_ID_SECONDARY_TDM_RX:
3803 channels->min = channels->max =
3804 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3805 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3806 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3807 rate->min = rate->max =
3808 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3809 break;
3810 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3811 channels->min = channels->max =
3812 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
3813 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3814 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
3815 rate->min = rate->max =
3816 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
3817 break;
3818 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
3819 channels->min = channels->max =
3820 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
3821 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3822 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
3823 rate->min = rate->max =
3824 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
3825 break;
3826 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
3827 channels->min = channels->max =
3828 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
3829 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3830 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
3831 rate->min = rate->max =
3832 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
3833 break;
3834 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
3835 channels->min = channels->max =
3836 tdm_rx_cfg[TDM_SEC][TDM_4].channels;
3837 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3838 tdm_rx_cfg[TDM_SEC][TDM_4].bit_format);
3839 rate->min = rate->max =
3840 tdm_rx_cfg[TDM_SEC][TDM_4].sample_rate;
3841 break;
3842 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
3843 channels->min = channels->max =
3844 tdm_rx_cfg[TDM_SEC][TDM_5].channels;
3845 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3846 tdm_rx_cfg[TDM_SEC][TDM_5].bit_format);
3847 rate->min = rate->max =
3848 tdm_rx_cfg[TDM_SEC][TDM_5].sample_rate;
3849 break;
3850 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
3851 channels->min = channels->max =
3852 tdm_rx_cfg[TDM_SEC][TDM_6].channels;
3853 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3854 tdm_rx_cfg[TDM_SEC][TDM_6].bit_format);
3855 rate->min = rate->max =
3856 tdm_rx_cfg[TDM_SEC][TDM_6].sample_rate;
3857 break;
3858 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
3859 channels->min = channels->max =
3860 tdm_rx_cfg[TDM_SEC][TDM_7].channels;
3861 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3862 tdm_rx_cfg[TDM_SEC][TDM_7].bit_format);
3863 rate->min = rate->max =
3864 tdm_rx_cfg[TDM_SEC][TDM_7].sample_rate;
3865 break;
3866 case AFE_PORT_ID_SECONDARY_TDM_TX:
3867 channels->min = channels->max =
3868 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3869 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3870 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3871 rate->min = rate->max =
3872 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3873 break;
3874 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
3875 channels->min = channels->max =
3876 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
3877 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3878 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
3879 rate->min = rate->max =
3880 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
3881 break;
3882 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
3883 channels->min = channels->max =
3884 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
3885 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3886 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
3887 rate->min = rate->max =
3888 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
3889 break;
3890 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
3891 channels->min = channels->max =
3892 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
3893 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3894 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
3895 rate->min = rate->max =
3896 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
3897 break;
3898 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
3899 channels->min = channels->max =
3900 tdm_tx_cfg[TDM_SEC][TDM_4].channels;
3901 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3902 tdm_tx_cfg[TDM_SEC][TDM_4].bit_format);
3903 rate->min = rate->max =
3904 tdm_tx_cfg[TDM_SEC][TDM_4].sample_rate;
3905 break;
3906 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
3907 channels->min = channels->max =
3908 tdm_tx_cfg[TDM_SEC][TDM_5].channels;
3909 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3910 tdm_tx_cfg[TDM_SEC][TDM_5].bit_format);
3911 rate->min = rate->max =
3912 tdm_tx_cfg[TDM_SEC][TDM_5].sample_rate;
3913 break;
3914 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
3915 channels->min = channels->max =
3916 tdm_tx_cfg[TDM_SEC][TDM_6].channels;
3917 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3918 tdm_tx_cfg[TDM_SEC][TDM_6].bit_format);
3919 rate->min = rate->max =
3920 tdm_tx_cfg[TDM_SEC][TDM_6].sample_rate;
3921 break;
3922 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
3923 channels->min = channels->max =
3924 tdm_tx_cfg[TDM_SEC][TDM_7].channels;
3925 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3926 tdm_tx_cfg[TDM_SEC][TDM_7].bit_format);
3927 rate->min = rate->max =
3928 tdm_tx_cfg[TDM_SEC][TDM_7].sample_rate;
3929 break;
3930 case AFE_PORT_ID_TERTIARY_TDM_RX:
3931 channels->min = channels->max =
3932 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3933 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3934 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3935 rate->min = rate->max =
3936 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3937 break;
3938 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
3939 channels->min = channels->max =
3940 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
3941 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3942 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
3943 rate->min = rate->max =
3944 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
3945 break;
3946 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
3947 channels->min = channels->max =
3948 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
3949 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3950 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
3951 rate->min = rate->max =
3952 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
3953 break;
3954 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
3955 channels->min = channels->max =
3956 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
3957 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3958 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
3959 rate->min = rate->max =
3960 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
3961 break;
3962 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
3963 channels->min = channels->max =
3964 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
3965 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3966 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
3967 rate->min = rate->max =
3968 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
3969 break;
3970 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
3971 channels->min = channels->max =
3972 tdm_rx_cfg[TDM_TERT][TDM_5].channels;
3973 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3974 tdm_rx_cfg[TDM_TERT][TDM_5].bit_format);
3975 rate->min = rate->max =
3976 tdm_rx_cfg[TDM_TERT][TDM_5].sample_rate;
3977 break;
3978 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
3979 channels->min = channels->max =
3980 tdm_rx_cfg[TDM_TERT][TDM_6].channels;
3981 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3982 tdm_rx_cfg[TDM_TERT][TDM_6].bit_format);
3983 rate->min = rate->max =
3984 tdm_rx_cfg[TDM_TERT][TDM_6].sample_rate;
3985 break;
3986 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
3987 channels->min = channels->max =
3988 tdm_rx_cfg[TDM_TERT][TDM_7].channels;
3989 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3990 tdm_rx_cfg[TDM_TERT][TDM_7].bit_format);
3991 rate->min = rate->max =
3992 tdm_rx_cfg[TDM_TERT][TDM_7].sample_rate;
3993 break;
3994 case AFE_PORT_ID_TERTIARY_TDM_TX:
3995 channels->min = channels->max =
3996 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3997 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3998 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3999 rate->min = rate->max =
4000 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4001 break;
4002 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4003 channels->min = channels->max =
4004 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
4005 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4006 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
4007 rate->min = rate->max =
4008 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
4009 break;
4010 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4011 channels->min = channels->max =
4012 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
4013 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4014 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
4015 rate->min = rate->max =
4016 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
4017 break;
4018 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4019 channels->min = channels->max =
4020 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
4021 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4022 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
4023 rate->min = rate->max =
4024 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
4025 break;
4026 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
4027 channels->min = channels->max =
4028 tdm_tx_cfg[TDM_TERT][TDM_4].channels;
4029 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4030 tdm_tx_cfg[TDM_TERT][TDM_4].bit_format);
4031 rate->min = rate->max =
4032 tdm_tx_cfg[TDM_TERT][TDM_4].sample_rate;
4033 break;
4034 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
4035 channels->min = channels->max =
4036 tdm_tx_cfg[TDM_TERT][TDM_5].channels;
4037 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4038 tdm_tx_cfg[TDM_TERT][TDM_5].bit_format);
4039 rate->min = rate->max =
4040 tdm_tx_cfg[TDM_TERT][TDM_5].sample_rate;
4041 break;
4042 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
4043 channels->min = channels->max =
4044 tdm_tx_cfg[TDM_TERT][TDM_6].channels;
4045 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4046 tdm_tx_cfg[TDM_TERT][TDM_6].bit_format);
4047 rate->min = rate->max =
4048 tdm_tx_cfg[TDM_TERT][TDM_6].sample_rate;
4049 break;
4050 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
4051 channels->min = channels->max =
4052 tdm_tx_cfg[TDM_TERT][TDM_7].channels;
4053 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4054 tdm_tx_cfg[TDM_TERT][TDM_7].bit_format);
4055 rate->min = rate->max =
4056 tdm_tx_cfg[TDM_TERT][TDM_7].sample_rate;
4057 break;
4058 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4059 channels->min = channels->max =
4060 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4061 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4062 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4063 rate->min = rate->max =
4064 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4065 break;
4066 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4067 channels->min = channels->max =
4068 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
4069 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4070 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
4071 rate->min = rate->max =
4072 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
4073 break;
4074 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4075 channels->min = channels->max =
4076 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
4077 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4078 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
4079 rate->min = rate->max =
4080 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
4081 break;
4082 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4083 channels->min = channels->max =
4084 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
4085 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4086 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
4087 rate->min = rate->max =
4088 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
4089 break;
4090 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
4091 channels->min = channels->max =
4092 tdm_rx_cfg[TDM_QUAT][TDM_4].channels;
4093 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4094 tdm_rx_cfg[TDM_QUAT][TDM_4].bit_format);
4095 rate->min = rate->max =
4096 tdm_rx_cfg[TDM_QUAT][TDM_4].sample_rate;
4097 break;
4098 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
4099 channels->min = channels->max =
4100 tdm_rx_cfg[TDM_QUAT][TDM_5].channels;
4101 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4102 tdm_rx_cfg[TDM_QUAT][TDM_5].bit_format);
4103 rate->min = rate->max =
4104 tdm_rx_cfg[TDM_QUAT][TDM_5].sample_rate;
4105 break;
4106 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
4107 channels->min = channels->max =
4108 tdm_rx_cfg[TDM_QUAT][TDM_6].channels;
4109 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4110 tdm_rx_cfg[TDM_QUAT][TDM_6].bit_format);
4111 rate->min = rate->max =
4112 tdm_rx_cfg[TDM_QUAT][TDM_6].sample_rate;
4113 break;
4114 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
4115 channels->min = channels->max =
4116 tdm_rx_cfg[TDM_QUAT][TDM_7].channels;
4117 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4118 tdm_rx_cfg[TDM_QUAT][TDM_7].bit_format);
4119 rate->min = rate->max =
4120 tdm_rx_cfg[TDM_QUAT][TDM_7].sample_rate;
4121 break;
4122 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4123 channels->min = channels->max =
4124 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4125 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4126 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4127 rate->min = rate->max =
4128 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4129 break;
4130 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4131 channels->min = channels->max =
4132 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
4133 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4134 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
4135 rate->min = rate->max =
4136 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
4137 break;
4138 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4139 channels->min = channels->max =
4140 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
4141 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4142 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
4143 rate->min = rate->max =
4144 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
4145 break;
4146 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4147 channels->min = channels->max =
4148 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
4149 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4150 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
4151 rate->min = rate->max =
4152 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
4153 break;
4154 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
4155 channels->min = channels->max =
4156 tdm_tx_cfg[TDM_QUAT][TDM_4].channels;
4157 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4158 tdm_tx_cfg[TDM_QUAT][TDM_4].bit_format);
4159 rate->min = rate->max =
4160 tdm_tx_cfg[TDM_QUAT][TDM_4].sample_rate;
4161 break;
4162 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
4163 channels->min = channels->max =
4164 tdm_tx_cfg[TDM_QUAT][TDM_5].channels;
4165 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4166 tdm_tx_cfg[TDM_QUAT][TDM_5].bit_format);
4167 rate->min = rate->max =
4168 tdm_tx_cfg[TDM_QUAT][TDM_5].sample_rate;
4169 break;
4170 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
4171 channels->min = channels->max =
4172 tdm_tx_cfg[TDM_QUAT][TDM_6].channels;
4173 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4174 tdm_tx_cfg[TDM_QUAT][TDM_6].bit_format);
4175 rate->min = rate->max =
4176 tdm_tx_cfg[TDM_QUAT][TDM_6].sample_rate;
4177 break;
4178 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4179 channels->min = channels->max =
4180 tdm_tx_cfg[TDM_QUAT][TDM_7].channels;
4181 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4182 tdm_tx_cfg[TDM_QUAT][TDM_7].bit_format);
4183 rate->min = rate->max =
4184 tdm_tx_cfg[TDM_QUAT][TDM_7].sample_rate;
4185 break;
4186 case AFE_PORT_ID_QUINARY_TDM_RX:
4187 channels->min = channels->max =
4188 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4189 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4190 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4191 rate->min = rate->max =
4192 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4193 break;
4194 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4195 channels->min = channels->max =
4196 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4197 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4198 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4199 rate->min = rate->max =
4200 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4201 break;
4202 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4203 channels->min = channels->max =
4204 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4205 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4206 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4207 rate->min = rate->max =
4208 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4209 break;
4210 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4211 channels->min = channels->max =
4212 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4213 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4214 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4215 rate->min = rate->max =
4216 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4217 break;
4218 case AFE_PORT_ID_QUINARY_TDM_RX_4:
4219 channels->min = channels->max =
4220 tdm_rx_cfg[TDM_QUIN][TDM_4].channels;
4221 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4222 tdm_rx_cfg[TDM_QUIN][TDM_4].bit_format);
4223 rate->min = rate->max =
4224 tdm_rx_cfg[TDM_QUIN][TDM_4].sample_rate;
4225 break;
4226 case AFE_PORT_ID_QUINARY_TDM_RX_5:
4227 channels->min = channels->max =
4228 tdm_rx_cfg[TDM_QUIN][TDM_5].channels;
4229 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4230 tdm_rx_cfg[TDM_QUIN][TDM_5].bit_format);
4231 rate->min = rate->max =
4232 tdm_rx_cfg[TDM_QUIN][TDM_5].sample_rate;
4233 break;
4234 case AFE_PORT_ID_QUINARY_TDM_RX_6:
4235 channels->min = channels->max =
4236 tdm_rx_cfg[TDM_QUIN][TDM_6].channels;
4237 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4238 tdm_rx_cfg[TDM_QUIN][TDM_6].bit_format);
4239 rate->min = rate->max =
4240 tdm_rx_cfg[TDM_QUIN][TDM_6].sample_rate;
4241 break;
4242 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4243 channels->min = channels->max =
4244 tdm_rx_cfg[TDM_QUIN][TDM_7].channels;
4245 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4246 tdm_rx_cfg[TDM_QUIN][TDM_7].bit_format);
4247 rate->min = rate->max =
4248 tdm_rx_cfg[TDM_QUIN][TDM_7].sample_rate;
4249 break;
4250 case AFE_PORT_ID_QUINARY_TDM_TX:
4251 channels->min = channels->max =
4252 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4253 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4254 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4255 rate->min = rate->max =
4256 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4257 break;
4258 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4259 channels->min = channels->max =
4260 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4261 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4262 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4263 rate->min = rate->max =
4264 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4265 break;
4266 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4267 channels->min = channels->max =
4268 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4269 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4270 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4271 rate->min = rate->max =
4272 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4273 break;
4274 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4275 channels->min = channels->max =
4276 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4277 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4278 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4279 rate->min = rate->max =
4280 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4281 break;
4282 case AFE_PORT_ID_QUINARY_TDM_TX_4:
4283 channels->min = channels->max =
4284 tdm_tx_cfg[TDM_QUIN][TDM_4].channels;
4285 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4286 tdm_tx_cfg[TDM_QUIN][TDM_4].bit_format);
4287 rate->min = rate->max =
4288 tdm_tx_cfg[TDM_QUIN][TDM_4].sample_rate;
4289 break;
4290 case AFE_PORT_ID_QUINARY_TDM_TX_5:
4291 channels->min = channels->max =
4292 tdm_tx_cfg[TDM_QUIN][TDM_5].channels;
4293 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4294 tdm_tx_cfg[TDM_QUIN][TDM_5].bit_format);
4295 rate->min = rate->max =
4296 tdm_tx_cfg[TDM_QUIN][TDM_5].sample_rate;
4297 break;
4298 case AFE_PORT_ID_QUINARY_TDM_TX_6:
4299 channels->min = channels->max =
4300 tdm_tx_cfg[TDM_QUIN][TDM_6].channels;
4301 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4302 tdm_tx_cfg[TDM_QUIN][TDM_6].bit_format);
4303 rate->min = rate->max =
4304 tdm_tx_cfg[TDM_QUIN][TDM_6].sample_rate;
4305 break;
4306 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4307 channels->min = channels->max =
4308 tdm_tx_cfg[TDM_QUIN][TDM_7].channels;
4309 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4310 tdm_tx_cfg[TDM_QUIN][TDM_7].bit_format);
4311 rate->min = rate->max =
4312 tdm_tx_cfg[TDM_QUIN][TDM_7].sample_rate;
4313 break;
4314
4315 default:
4316 pr_err("%s: dai id 0x%x not supported\n",
4317 __func__, cpu_dai->id);
4318 return -EINVAL;
4319 }
4320
4321 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4322 __func__, cpu_dai->id, channels->max, rate->max,
4323 params_format(params));
4324
4325 return 0;
4326}
4327EXPORT_SYMBOL(msm_tdm_be_hw_params_fixup);
4328
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4329static int msm_ext_disp_get_idx_from_beid(int32_t id)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4330{
4331 int idx;
4332
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4333 switch (id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4334 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
4335 idx = DP_RX_IDX;
4336 break;
4337 default:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4338 pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4339 idx = -EINVAL;
4340 break;
4341 }
4342
4343 return idx;
4344}
4345
4346/**
4347 * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
4348 *
4349 * @rtd: runtime dailink instance
4350 * @params: HW params of associated backend dailink.
4351 *
4352 * Returns 0.
4353 */
4354int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
4355 struct snd_pcm_hw_params *params)
4356{
4357 struct snd_soc_dai_link *dai_link = rtd->dai_link;
4358 struct snd_interval *rate = hw_param_interval(params,
4359 SNDRV_PCM_HW_PARAM_RATE);
4360 struct snd_interval *channels = hw_param_interval(params,
4361 SNDRV_PCM_HW_PARAM_CHANNELS);
4362 int rc = 0;
4363 int idx;
4364
4365 pr_debug("%s: format = %d, rate = %d\n",
4366 __func__, params_format(params), params_rate(params));
4367
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4368 switch (dai_link->id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4369 case MSM_BACKEND_DAI_USB_RX:
4370 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4371 usb_rx_cfg.bit_format);
4372 rate->min = rate->max = usb_rx_cfg.sample_rate;
4373 channels->min = channels->max = usb_rx_cfg.channels;
4374 break;
4375
4376 case MSM_BACKEND_DAI_USB_TX:
4377 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4378 usb_tx_cfg.bit_format);
4379 rate->min = rate->max = usb_tx_cfg.sample_rate;
4380 channels->min = channels->max = usb_tx_cfg.channels;
4381 break;
4382
4383 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4384 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
4385 if (idx < 0) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4386 pr_err("%s: Incorrect ext disp idx %d\n",
4387 __func__, idx);
4388 rc = idx;
4389 break;
4390 }
4391
4392 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4393 ext_disp_rx_cfg[idx].bit_format);
4394 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
4395 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
4396 break;
4397
4398 case MSM_BACKEND_DAI_AFE_PCM_RX:
4399 channels->min = channels->max = proxy_rx_cfg.channels;
4400 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4401 break;
4402
4403 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
4404 channels->min = channels->max =
4405 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
4406 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4407 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
4408 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
4409 break;
4410
4411 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
4412 channels->min = channels->max =
4413 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
4414 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4415 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
4416 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
4417 break;
4418
4419 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
4420 channels->min = channels->max =
4421 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
4422 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4423 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
4424 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
4425 break;
4426
4427 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
4428 channels->min = channels->max =
4429 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4430 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4431 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4432 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4433 break;
4434
4435 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
4436 channels->min = channels->max =
4437 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4438 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4439 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4440 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4441 break;
4442
4443 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
4444 channels->min = channels->max =
4445 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4446 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4447 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4448 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4449 break;
4450
4451 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
4452 channels->min = channels->max =
4453 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4454 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4455 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4456 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4457 break;
4458
4459 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
4460 channels->min = channels->max =
4461 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4462 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4463 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4464 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4465 break;
4466
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4467 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
4468 channels->min = channels->max =
4469 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4470 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4471 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4472 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4473 break;
4474
4475 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
4476 channels->min = channels->max =
4477 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4478 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4479 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4480 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4481 break;
4482
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4483 case MSM_BACKEND_DAI_AUXPCM_RX:
4484 rate->min = rate->max =
4485 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
4486 channels->min = channels->max =
4487 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
4488 break;
4489
4490 case MSM_BACKEND_DAI_AUXPCM_TX:
4491 rate->min = rate->max =
4492 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
4493 channels->min = channels->max =
4494 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
4495 break;
4496
4497 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
4498 rate->min = rate->max =
4499 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
4500 channels->min = channels->max =
4501 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
4502 break;
4503
4504 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
4505 rate->min = rate->max =
4506 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
4507 channels->min = channels->max =
4508 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
4509 break;
4510
4511 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
4512 rate->min = rate->max =
4513 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
4514 channels->min = channels->max =
4515 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
4516 break;
4517
4518 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
4519 rate->min = rate->max =
4520 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
4521 channels->min = channels->max =
4522 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
4523 break;
4524
4525 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
4526 rate->min = rate->max =
4527 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
4528 channels->min = channels->max =
4529 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
4530 break;
4531
4532 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
4533 rate->min = rate->max =
4534 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
4535 channels->min = channels->max =
4536 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
4537 break;
4538
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4539 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
4540 rate->min = rate->max =
4541 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
4542 channels->min = channels->max =
4543 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
4544 break;
4545
4546 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
4547 rate->min = rate->max =
4548 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
4549 channels->min = channels->max =
4550 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
4551 break;
4552
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4553 case MSM_BACKEND_DAI_PRI_MI2S_RX:
4554 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
4555 channels->min = channels->max =
4556 mi2s_rx_cfg[PRIM_MI2S].channels;
4557 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4558 mi2s_rx_cfg[PRIM_MI2S].bit_format);
4559 break;
4560
4561 case MSM_BACKEND_DAI_PRI_MI2S_TX:
4562 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
4563 channels->min = channels->max =
4564 mi2s_tx_cfg[PRIM_MI2S].channels;
4565 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4566 mi2s_tx_cfg[PRIM_MI2S].bit_format);
4567 break;
4568
4569 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
4570 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
4571 channels->min = channels->max =
4572 mi2s_rx_cfg[SEC_MI2S].channels;
4573 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4574 mi2s_rx_cfg[SEC_MI2S].bit_format);
4575 break;
4576
4577 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
4578 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
4579 channels->min = channels->max =
4580 mi2s_tx_cfg[SEC_MI2S].channels;
4581 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4582 mi2s_tx_cfg[SEC_MI2S].bit_format);
4583 break;
4584
4585 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
4586 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
4587 channels->min = channels->max =
4588 mi2s_rx_cfg[TERT_MI2S].channels;
4589 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4590 mi2s_rx_cfg[TERT_MI2S].bit_format);
4591 break;
4592
4593 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
4594 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
4595 channels->min = channels->max =
4596 mi2s_tx_cfg[TERT_MI2S].channels;
4597 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4598 mi2s_tx_cfg[TERT_MI2S].bit_format);
4599 break;
4600
4601 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
4602 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
4603 channels->min = channels->max =
4604 mi2s_rx_cfg[QUAT_MI2S].channels;
4605 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4606 mi2s_rx_cfg[QUAT_MI2S].bit_format);
4607 break;
4608
4609 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
4610 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
4611 channels->min = channels->max =
4612 mi2s_tx_cfg[QUAT_MI2S].channels;
4613 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4614 mi2s_tx_cfg[QUAT_MI2S].bit_format);
4615 break;
4616
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4617 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
4618 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
4619 channels->min = channels->max =
4620 mi2s_rx_cfg[QUIN_MI2S].channels;
4621 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4622 mi2s_rx_cfg[QUIN_MI2S].bit_format);
4623 break;
4624
4625 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
4626 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
4627 channels->min = channels->max =
4628 mi2s_tx_cfg[QUIN_MI2S].channels;
4629 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4630 mi2s_tx_cfg[QUIN_MI2S].bit_format);
4631 break;
4632
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4633 default:
4634 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4635 break;
4636 }
4637 return rc;
4638}
4639EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
4640
4641/**
4642 * msm_aux_pcm_snd_startup - startup ops of auxpcm.
4643 *
4644 * @substream: PCM stream pointer of associated backend dailink
4645 *
4646 * Returns 0 on success or -EINVAL on error.
4647 */
4648int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
4649{
4650 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4651
4652 dev_dbg(rtd->card->dev,
4653 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4654 __func__, substream->name, substream->stream,
4655 rtd->cpu_dai->name, rtd->cpu_dai->id);
4656
4657 return 0;
4658}
4659EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
4660
4661/**
4662 * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
4663 *
4664 * @substream: PCM stream pointer of associated backend dailink
4665 */
4666void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
4667{
4668 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4669
4670 dev_dbg(rtd->card->dev,
4671 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4672 __func__,
4673 substream->name, substream->stream,
4674 rtd->cpu_dai->name, rtd->cpu_dai->id);
4675}
4676EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
4677
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4678static int msm_get_port_id(int id)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4679{
4680 int afe_port_id;
4681
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4682 switch (id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4683 case MSM_BACKEND_DAI_PRI_MI2S_RX:
4684 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
4685 break;
4686 case MSM_BACKEND_DAI_PRI_MI2S_TX:
4687 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
4688 break;
4689 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
4690 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
4691 break;
4692 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
4693 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
4694 break;
4695 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
4696 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
4697 break;
4698 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
4699 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
4700 break;
4701 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
4702 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
4703 break;
4704 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
4705 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
4706 break;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4707 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
4708 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
4709 break;
4710 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
4711 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
4712 break;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4713 default:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4714 pr_err("%s: Invalid id: %d\n", __func__, id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4715 afe_port_id = -EINVAL;
4716 }
4717
4718 return afe_port_id;
4719}
4720
4721static u32 get_mi2s_bits_per_sample(u32 bit_format)
4722{
4723 u32 bit_per_sample;
4724
4725 switch (bit_format) {
4726 case SNDRV_PCM_FORMAT_S32_LE:
4727 case SNDRV_PCM_FORMAT_S24_3LE:
4728 case SNDRV_PCM_FORMAT_S24_LE:
4729 bit_per_sample = 32;
4730 break;
4731 case SNDRV_PCM_FORMAT_S16_LE:
4732 default:
4733 bit_per_sample = 16;
4734 break;
4735 }
4736
4737 return bit_per_sample;
4738}
4739
4740static void update_mi2s_clk_val(int dai_id, int stream)
4741{
4742 u32 bit_per_sample;
4743
4744 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
4745 bit_per_sample =
4746 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
4747 mi2s_clk[dai_id].clk_freq_in_hz =
4748 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
4749 } else {
4750 bit_per_sample =
4751 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
4752 mi2s_clk[dai_id].clk_freq_in_hz =
4753 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
4754 }
4755}
4756
4757static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
4758{
4759 int ret = 0;
4760 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4761 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4762 int port_id = 0;
4763 int index = cpu_dai->id;
4764
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4765 port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4766 if (port_id < 0) {
4767 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
4768 ret = port_id;
4769 goto done;
4770 }
4771
4772 if (enable) {
4773 update_mi2s_clk_val(index, substream->stream);
4774 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
4775 mi2s_clk[index].clk_freq_in_hz);
4776 }
4777
4778 mi2s_clk[index].enable = enable;
4779 ret = afe_set_lpass_clock_v2(port_id,
4780 &mi2s_clk[index]);
4781 if (ret < 0) {
4782 dev_err(rtd->card->dev,
4783 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
4784 __func__, port_id, ret);
4785 goto done;
4786 }
4787
4788done:
4789 return ret;
4790}
4791
4792/**
4793 * msm_mi2s_snd_startup - startup ops of mi2s.
4794 *
4795 * @substream: PCM stream pointer of associated backend dailink
4796 *
4797 * Returns 0 on success or -EINVAL on error.
4798 */
4799int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4800{
4801 int ret = 0;
4802 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4803 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4804 int port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4805 int index = cpu_dai->id;
4806 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4807 struct msm_asoc_mach_data *pdata =
4808 snd_soc_card_get_drvdata(rtd->card);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4809
4810 dev_dbg(rtd->card->dev,
4811 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4812 __func__, substream->name, substream->stream,
4813 cpu_dai->name, cpu_dai->id);
4814
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4815 if (index < PRIM_MI2S || index >= MI2S_MAX) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4816 ret = -EINVAL;
4817 dev_err(rtd->card->dev,
4818 "%s: CPU DAI id (%d) out of range\n",
4819 __func__, cpu_dai->id);
4820 goto done;
4821 }
4822 /*
4823 * Muxtex protection in case the same MI2S
4824 * interface using for both TX and RX so
4825 * that the same clock won't be enable twice.
4826 */
4827 mutex_lock(&mi2s_intf_conf[index].lock);
4828 if (++mi2s_intf_conf[index].ref_cnt == 1) {
4829 /* Check if msm needs to provide the clock to the interface */
4830 if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
4831 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4832 fmt = SND_SOC_DAIFMT_CBM_CFM;
4833 }
4834 ret = msm_mi2s_set_sclk(substream, true);
4835 if (ret < 0) {
4836 dev_err(rtd->card->dev,
4837 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4838 __func__, ret);
4839 goto clean_up;
4840 }
4841 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4842 if (ret < 0) {
4843 dev_err(rtd->card->dev,
4844 "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4845 __func__, index, ret);
4846 goto clk_off;
4847 }
4848 if (mi2s_intf_conf[index].msm_is_ext_mclk) {
4849 mi2s_mclk[index].enable = 1;
4850 pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
4851 __func__, mi2s_mclk[index].clk_freq_in_hz);
4852 ret = afe_set_lpass_clock_v2(port_id,
4853 &mi2s_mclk[index]);
4854 if (ret < 0) {
4855 pr_err("%s: afe lpass mclk failed, err:%d\n",
4856 __func__, ret);
4857 goto clk_off;
4858 }
4859 }
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4860 if (pdata->mi2s_gpio_p[index])
4861 msm_cdc_pinctrl_select_active_state(
4862 pdata->mi2s_gpio_p[index]);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4863 }
4864 mutex_unlock(&mi2s_intf_conf[index].lock);
4865 return 0;
4866clk_off:
4867 if (ret < 0)
4868 msm_mi2s_set_sclk(substream, false);
4869clean_up:
4870 if (ret < 0)
4871 mi2s_intf_conf[index].ref_cnt--;
4872 mutex_unlock(&mi2s_intf_conf[index].lock);
4873done:
4874 return ret;
4875}
4876EXPORT_SYMBOL(msm_mi2s_snd_startup);
4877
4878/**
4879 * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
4880 *
4881 * @substream: PCM stream pointer of associated backend dailink
4882 */
4883void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4884{
4885 int ret;
4886 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4887 int port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4888 int index = rtd->cpu_dai->id;
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4889 struct msm_asoc_mach_data *pdata =
4890 snd_soc_card_get_drvdata(rtd->card);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4891
4892 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4893 substream->name, substream->stream);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4894 if (index < PRIM_MI2S || index >= MI2S_MAX) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4895 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4896 return;
4897 }
4898
4899 mutex_lock(&mi2s_intf_conf[index].lock);
4900 if (--mi2s_intf_conf[index].ref_cnt == 0) {
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4901 if (pdata->mi2s_gpio_p[index])
4902 msm_cdc_pinctrl_select_sleep_state(
4903 pdata->mi2s_gpio_p[index]);
4904
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4905 ret = msm_mi2s_set_sclk(substream, false);
Aditya Bavanarib68d1022018-01-08 19:14:41 +0530[diff] [blame]4906 if (ret < 0)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4907 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4908 __func__, index, ret);
Aditya Bavanarib68d1022018-01-08 19:14:41 +0530[diff] [blame]4909
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4910 if (mi2s_intf_conf[index].msm_is_ext_mclk) {
4911 mi2s_mclk[index].enable = 0;
4912 pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
4913 __func__, mi2s_mclk[index].clk_freq_in_hz);
4914 ret = afe_set_lpass_clock_v2(port_id,
4915 &mi2s_mclk[index]);
4916 if (ret < 0) {
4917 pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
4918 __func__, index, ret);
4919 }
4920 }
4921 }
4922 mutex_unlock(&mi2s_intf_conf[index].lock);
4923}
4924EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
4925
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4926static int msm_get_tdm_mode(u32 port_id)
4927{
4928 int tdm_mode;
4929
4930 switch (port_id) {
4931 case AFE_PORT_ID_PRIMARY_TDM_RX:
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]4932 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4933 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4934 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4935 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
4936 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
4937 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
4938 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4939 case AFE_PORT_ID_PRIMARY_TDM_TX:
Gangadhar Sc1a5a502020-03-03 13:23:43 +0530[diff] [blame^]4940 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4941 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4942 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4943 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
4944 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
4945 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
4946 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4947 tdm_mode = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4948 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4949 case AFE_PORT_ID_SECONDARY_TDM_RX:
4950 case AFE_PORT_ID_SECONDARY_TDM_TX:
4951 tdm_mode = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4952 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4953 case AFE_PORT_ID_TERTIARY_TDM_RX:
4954 case AFE_PORT_ID_TERTIARY_TDM_TX:
4955 tdm_mode = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4956 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4957 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4958 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4959 tdm_mode = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4960 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4961 case AFE_PORT_ID_QUINARY_TDM_RX:
4962 case AFE_PORT_ID_QUINARY_TDM_TX:
4963 tdm_mode = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4964 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4965 default:
4966 pr_err("%s: Invalid port id: %d\n", __func__, port_id);
4967 tdm_mode = -EINVAL;
4968 }
4969 return tdm_mode;
4970}
4971
4972int msm_tdm_snd_startup(struct snd_pcm_substream *substream)
4973{
4974 int ret = 0;
4975 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4976 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4977 struct snd_soc_card *card = rtd->card;
4978 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4979 struct tdm_dai_data *dai_data = dev_get_drvdata(cpu_dai->dev);
4980 int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
4981
4982 if (tdm_mode < 0) {
4983 dev_err(rtd->card->dev, "%s: Invalid tdm_mode\n", __func__);
4984 return tdm_mode;
4985 }
4986 dai_data->clk_set.enable = true;
4987 ret = afe_set_lpass_clock_v2(cpu_dai->id, &dai_data->clk_set);
4988 if (ret < 0)
4989 pr_err("%s: afe lpass clock failed, err:%d\n",
4990 __func__, ret);
4991 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4992 if (pdata->mi2s_gpio_p[tdm_mode])
4993 ret = msm_cdc_pinctrl_select_active_state(
4994 pdata->mi2s_gpio_p[tdm_mode]);
4995 return ret;
4996}
4997EXPORT_SYMBOL(msm_tdm_snd_startup);
4998
4999void msm_tdm_snd_shutdown(struct snd_pcm_substream *substream)
5000{
5001 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5002 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5003 struct snd_soc_card *card = rtd->card;
5004 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5005 struct tdm_dai_data *dai_data = dev_get_drvdata(cpu_dai->dev);
5006 int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
5007 int ret;
5008
5009 if (tdm_mode < 0) {
5010 dev_err(rtd->card->dev, "%s: Invalid tdm_mode\n", __func__);
5011 return;
5012 }
5013 dai_data->clk_set.enable = false;
5014 ret = afe_set_lpass_clock_v2(cpu_dai->id, &dai_data->clk_set);
5015 if (ret < 0)
5016 pr_err("%s: afe lpass clock failed, err:%d\n", __func__, ret);
5017
5018 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
5019 if (pdata->mi2s_gpio_p[tdm_mode])
5020 msm_cdc_pinctrl_select_sleep_state(
5021 pdata->mi2s_gpio_p[tdm_mode]);
5022}
5023EXPORT_SYMBOL(msm_tdm_snd_shutdown);
5024
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5025/* Validate whether US EU switch is present or not */
5026static int msm_prepare_us_euro(struct snd_soc_card *card)
5027{
5028 struct msm_asoc_mach_data *pdata =
5029 snd_soc_card_get_drvdata(card);
5030 int ret = 0;
5031
5032 if (pdata->us_euro_gpio >= 0) {
5033 dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
5034 pdata->us_euro_gpio);
5035 ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
5036 if (ret) {
5037 dev_err(card->dev,
5038 "%s: Failed to request codec US/EURO gpio %d error %d\n",
5039 __func__, pdata->us_euro_gpio, ret);
5040 }
5041 }
5042
5043 return ret;
5044}
5045
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5046
5047static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
5048{
5049 int value = 0;
5050 bool ret = false;
5051 struct snd_soc_card *card = codec->component.card;
5052 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5053 struct pinctrl_state *en2_pinctrl_active;
5054 struct pinctrl_state *en2_pinctrl_sleep;
5055
5056 if (!pdata->usbc_en2_gpio_p) {
5057 if (active) {
5058 /* if active and usbc_en2_gpio undefined, get pin */
5059 pdata->usbc_en2_gpio_p = devm_pinctrl_get(card->dev);
5060 if (IS_ERR_OR_NULL(pdata->usbc_en2_gpio_p)) {
5061 dev_err(card->dev,
5062 "%s: Can't get EN2 gpio pinctrl:%ld\n",
5063 __func__,
5064 PTR_ERR(pdata->usbc_en2_gpio_p));
5065 pdata->usbc_en2_gpio_p = NULL;
5066 return false;
5067 }
5068 } else {
5069 /* if not active and usbc_en2_gpio undefined, return */
5070 return false;
5071 }
5072 }
5073
5074 pdata->usbc_en2_gpio = of_get_named_gpio(card->dev->of_node,
5075 "qcom,usbc-analog-en2-gpio", 0);
5076 if (!gpio_is_valid(pdata->usbc_en2_gpio)) {
5077 dev_err(card->dev, "%s, property %s not in node %s\n",
5078 __func__, "qcom,usbc-analog-en2-gpio",
5079 card->dev->of_node->full_name);
5080 return false;
5081 }
5082
5083 en2_pinctrl_active = pinctrl_lookup_state(
5084 pdata->usbc_en2_gpio_p, "aud_active");
5085 if (IS_ERR_OR_NULL(en2_pinctrl_active)) {
5086 dev_err(card->dev,
5087 "%s: Cannot get aud_active pinctrl state:%ld\n",
5088 __func__, PTR_ERR(en2_pinctrl_active));
5089 ret = false;
5090 goto err_lookup_state;
5091 }
5092
5093 en2_pinctrl_sleep = pinctrl_lookup_state(
5094 pdata->usbc_en2_gpio_p, "aud_sleep");
5095 if (IS_ERR_OR_NULL(en2_pinctrl_sleep)) {
5096 dev_err(card->dev,
5097 "%s: Cannot get aud_sleep pinctrl state:%ld\n",
5098 __func__, PTR_ERR(en2_pinctrl_sleep));
5099 ret = false;
5100 goto err_lookup_state;
5101 }
5102
5103 /* if active and usbc_en2_gpio_p defined, swap using usbc_en2_gpio_p */
5104 if (active) {
5105 dev_dbg(codec->dev, "%s: enter\n", __func__);
5106 if (pdata->usbc_en2_gpio_p) {
5107 value = gpio_get_value_cansleep(pdata->usbc_en2_gpio);
5108 if (value)
5109 pinctrl_select_state(pdata->usbc_en2_gpio_p,
5110 en2_pinctrl_sleep);
5111 else
5112 pinctrl_select_state(pdata->usbc_en2_gpio_p,
5113 en2_pinctrl_active);
5114 } else if (pdata->usbc_en2_gpio >= 0) {
5115 value = gpio_get_value_cansleep(pdata->usbc_en2_gpio);
5116 gpio_set_value_cansleep(pdata->usbc_en2_gpio, !value);
5117 }
5118 pr_debug("%s: swap select switch %d to %d\n", __func__,
5119 value, !value);
5120 ret = true;
5121 } else {
5122 /* if not active, release usbc_en2_gpio_p pin */
5123 pinctrl_select_state(pdata->usbc_en2_gpio_p,
5124 en2_pinctrl_sleep);
5125 }
5126
5127err_lookup_state:
5128 devm_pinctrl_put(pdata->usbc_en2_gpio_p);
5129 pdata->usbc_en2_gpio_p = NULL;
5130 return ret;
5131}
5132
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5133static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5134{
5135 struct snd_soc_card *card = codec->component.card;
5136 struct msm_asoc_mach_data *pdata =
5137 snd_soc_card_get_drvdata(card);
5138 int value = 0;
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5139 bool ret = 0;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5140
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5141 if (!mbhc_cfg.enable_usbc_analog) {
5142 if (pdata->us_euro_gpio_p) {
5143 value = msm_cdc_pinctrl_get_state(
5144 pdata->us_euro_gpio_p);
5145 if (value)
5146 msm_cdc_pinctrl_select_sleep_state(
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5147 pdata->us_euro_gpio_p);
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5148 else
5149 msm_cdc_pinctrl_select_active_state(
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5150 pdata->us_euro_gpio_p);
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5151 } else if (pdata->us_euro_gpio >= 0) {
5152 value = gpio_get_value_cansleep(pdata->us_euro_gpio);
5153 gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
5154 }
5155 pr_debug("%s: swap select switch %d to %d\n",
5156 __func__, value, !value);
5157 ret = true;
5158 } else {
5159 /* if usbc is defined, swap using usbc_en2 */
5160 ret = msm_usbc_swap_gnd_mic(codec, active);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5161 }
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5162 return ret;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5163}
5164
5165static int msm_populate_dai_link_component_of_node(
5166 struct msm_asoc_mach_data *pdata,
5167 struct snd_soc_card *card)
5168{
5169 int i, index, ret = 0;
5170 struct device *cdev = card->dev;
5171 struct snd_soc_dai_link *dai_link = card->dai_link;
5172 struct device_node *phandle;
5173
5174 if (!cdev) {
5175 pr_err("%s: Sound card device memory NULL\n", __func__);
5176 return -ENODEV;
5177 }
5178
5179 for (i = 0; i < card->num_links; i++) {
5180 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
5181 continue;
5182
5183 /* populate platform_of_node for snd card dai links */
5184 if (dai_link[i].platform_name &&
5185 !dai_link[i].platform_of_node) {
5186 index = of_property_match_string(cdev->of_node,
5187 "asoc-platform-names",
5188 dai_link[i].platform_name);
5189 if (index < 0) {
5190 pr_err("%s: No match found for platform name: %s\n",
5191 __func__, dai_link[i].platform_name);
5192 ret = index;
5193 goto cpu_dai;
5194 }
5195 phandle = of_parse_phandle(cdev->of_node,
5196 "asoc-platform",
5197 index);
5198 if (!phandle) {
5199 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
5200 __func__, dai_link[i].platform_name,
5201 index);
5202 ret = -ENODEV;
5203 goto err;
5204 }
5205 dai_link[i].platform_of_node = phandle;
5206 dai_link[i].platform_name = NULL;
5207 }
5208cpu_dai:
5209 /* populate cpu_of_node for snd card dai links */
5210 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
5211 index = of_property_match_string(cdev->of_node,
5212 "asoc-cpu-names",
5213 dai_link[i].cpu_dai_name);
5214 if (index < 0)
5215 goto codec_dai;
5216 phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
5217 index);
5218 if (!phandle) {
5219 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
5220 __func__, dai_link[i].cpu_dai_name);
5221 ret = -ENODEV;
5222 goto err;
5223 }
5224 dai_link[i].cpu_of_node = phandle;
5225 dai_link[i].cpu_dai_name = NULL;
5226 }
5227codec_dai:
5228 /* populate codec_of_node for snd card dai links */
5229 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
5230 index = of_property_match_string(cdev->of_node,
5231 "asoc-codec-names",
5232 dai_link[i].codec_name);
5233 if (index < 0)
5234 continue;
5235 phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
5236 index);
5237 if (!phandle) {
5238 pr_err("%s: retrieving phandle for codec dai %s failed\n",
5239 __func__, dai_link[i].codec_name);
5240 ret = -ENODEV;
5241 goto err;
5242 }
5243 dai_link[i].codec_of_node = phandle;
5244 dai_link[i].codec_name = NULL;
5245 }
5246 if (pdata->snd_card_val == INT_SND_CARD) {
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5247 if ((dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5248 MSM_BACKEND_DAI_INT0_MI2S_RX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5249 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5250 MSM_BACKEND_DAI_INT1_MI2S_RX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5251 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5252 MSM_BACKEND_DAI_INT2_MI2S_TX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5253 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5254 MSM_BACKEND_DAI_INT3_MI2S_TX)) {
5255 index = of_property_match_string(cdev->of_node,
5256 "asoc-codec-names",
5257 MSM_INT_DIGITAL_CODEC);
5258 phandle = of_parse_phandle(cdev->of_node,
5259 "asoc-codec",
5260 index);
5261 dai_link[i].codecs[DIG_CDC].of_node = phandle;
5262 index = of_property_match_string(cdev->of_node,
5263 "asoc-codec-names",
5264 PMIC_INT_ANALOG_CODEC);
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5265 phandle = of_parse_phandle(
5266 cdev->of_node,
5267 "asoc-codec",
5268 index);
5269 dai_link[i].codecs[ANA_CDC].of_node =
5270 phandle;
5271 }
5272 }
5273 if (pdata->snd_card_val == INT_DIG_SND_CARD) {
5274 if ((dai_link[i].id ==
5275 MSM_BACKEND_DAI_INT0_MI2S_RX) ||
5276 (dai_link[i].id ==
5277 MSM_BACKEND_DAI_INT1_MI2S_RX) ||
5278 (dai_link[i].id ==
5279 MSM_BACKEND_DAI_INT2_MI2S_TX) ||
5280 (dai_link[i].id ==
5281 MSM_BACKEND_DAI_INT3_MI2S_TX)) {
5282 index = of_property_match_string(cdev->of_node,
5283 "asoc-codec-names",
5284 MSM_INT_DIGITAL_CODEC);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5285 phandle = of_parse_phandle(cdev->of_node,
5286 "asoc-codec",
5287 index);
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5288 dai_link[i].codec_of_node = phandle;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5289 }
5290 }
5291 }
5292err:
5293 return ret;
5294}
5295
5296static int msm_wsa881x_init(struct snd_soc_component *component)
5297{
5298 u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
5299 u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
5300 unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
5301 unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
5302 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
5303 struct msm_asoc_mach_data *pdata;
5304 struct snd_soc_dapm_context *dapm =
5305 snd_soc_codec_get_dapm(codec);
5306
5307 if (!codec) {
5308 pr_err("%s codec is NULL\n", __func__);
5309 return -EINVAL;
5310 }
5311
5312 if (!strcmp(component->name_prefix, "SpkrLeft")) {
5313 dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
5314 __func__, codec->component.name);
5315 wsa881x_set_channel_map(codec, &spkleft_ports[0],
5316 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
5317 &ch_rate[0]);
5318 if (dapm->component) {
5319 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
5320 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
5321 }
5322 } else if (!strcmp(component->name_prefix, "SpkrRight")) {
5323 dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
5324 __func__, codec->component.name);
5325 wsa881x_set_channel_map(codec, &spkright_ports[0],
5326 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
5327 &ch_rate[0]);
5328 if (dapm->component) {
5329 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
5330 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
5331 }
5332 } else {
5333 dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
5334 codec->component.name);
5335 return -EINVAL;
5336 }
5337
5338
5339 pdata = snd_soc_card_get_drvdata(component->card);
5340 if (pdata && pdata->codec_root)
5341 wsa881x_codec_info_create_codec_entry(pdata->codec_root,
5342 codec);
5343 return 0;
5344}
5345
5346
5347static int msm_init_wsa_dev(struct platform_device *pdev,
5348 struct snd_soc_card *card)
5349{
5350 struct device_node *wsa_of_node;
5351 u32 wsa_max_devs;
5352 u32 wsa_dev_cnt;
5353 char *dev_name_str = NULL;
5354 struct msm_wsa881x_dev_info *wsa881x_dev_info;
5355 const char *wsa_auxdev_name_prefix[1];
5356 int found = 0;
5357 int i;
5358 int ret;
5359
5360 /* Get maximum WSA device count for this platform */
5361 ret = of_property_read_u32(pdev->dev.of_node,
5362 "qcom,wsa-max-devs", &wsa_max_devs);
5363 if (ret) {
5364 dev_dbg(&pdev->dev,
5365 "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
5366 __func__, pdev->dev.of_node->full_name, ret);
5367 goto err_dt;
5368 }
5369 if (wsa_max_devs == 0) {
5370 dev_warn(&pdev->dev,
5371 "%s: Max WSA devices is 0 for this target?\n",
5372 __func__);
5373 goto err_dt;
5374 }
5375
5376 /* Get count of WSA device phandles for this platform */
5377 wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
5378 "qcom,wsa-devs", NULL);
5379 if (wsa_dev_cnt == -ENOENT) {
5380 dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
5381 __func__);
5382 goto err_dt;
5383 } else if (wsa_dev_cnt <= 0) {
5384 dev_err(&pdev->dev,
5385 "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
5386 __func__, wsa_dev_cnt);
5387 ret = -EINVAL;
5388 goto err_dt;
5389 }
5390
5391 /*
5392 * Expect total phandles count to be NOT less than maximum possible
5393 * WSA count. However, if it is less, then assign same value to
5394 * max count as well.
5395 */
5396 if (wsa_dev_cnt < wsa_max_devs) {
5397 dev_dbg(&pdev->dev,
5398 "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
5399 __func__, wsa_max_devs, wsa_dev_cnt);
5400 wsa_max_devs = wsa_dev_cnt;
5401 }
5402
5403 /* Make sure prefix string passed for each WSA device */
5404 ret = of_property_count_strings(pdev->dev.of_node,
5405 "qcom,wsa-aux-dev-prefix");
5406 if (ret != wsa_dev_cnt) {
5407 dev_err(&pdev->dev,
5408 "%s: expecting %d wsa prefix. Defined only %d in DT\n",
5409 __func__, wsa_dev_cnt, ret);
5410 ret = -EINVAL;
5411 goto err_dt;
5412 }
5413
5414 /*
5415 * Alloc mem to store phandle and index info of WSA device, if already
5416 * registered with ALSA core
5417 */
5418 wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
5419 sizeof(struct msm_wsa881x_dev_info),
5420 GFP_KERNEL);
5421 if (!wsa881x_dev_info) {
5422 ret = -ENOMEM;
5423 goto err_mem;
5424 }
5425
5426 /*
5427 * search and check whether all WSA devices are already
5428 * registered with ALSA core or not. If found a node, store
5429 * the node and the index in a local array of struct for later
5430 * use.
5431 */
5432 for (i = 0; i < wsa_dev_cnt; i++) {
5433 wsa_of_node = of_parse_phandle(pdev->dev.of_node,
5434 "qcom,wsa-devs", i);
5435 if (unlikely(!wsa_of_node)) {
5436 /* we should not be here */
5437 dev_err(&pdev->dev,
5438 "%s: wsa dev node is not present\n",
5439 __func__);
5440 ret = -EINVAL;
5441 goto err_dev_node;
5442 }
5443 if (soc_find_component(wsa_of_node, NULL)) {
5444 /* WSA device registered with ALSA core */
5445 wsa881x_dev_info[found].of_node = wsa_of_node;
5446 wsa881x_dev_info[found].index = i;
5447 found++;
5448 if (found == wsa_max_devs)
5449 break;
5450 }
5451 }
5452
5453 if (found < wsa_max_devs) {
5454 dev_dbg(&pdev->dev,
5455 "%s: failed to find %d components. Found only %d\n",
5456 __func__, wsa_max_devs, found);
5457 return -EPROBE_DEFER;
5458 }
5459 dev_info(&pdev->dev,
5460 "%s: found %d wsa881x devices registered with ALSA core\n",
5461 __func__, found);
5462
5463 card->num_aux_devs = wsa_max_devs;
5464 card->num_configs = wsa_max_devs;
5465
5466 /* Alloc array of AUX devs struct */
5467 msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
5468 sizeof(struct snd_soc_aux_dev),
5469 GFP_KERNEL);
5470 if (!msm_aux_dev) {
5471 ret = -ENOMEM;
5472 goto err_auxdev_mem;
5473 }
5474
5475 /* Alloc array of codec conf struct */
5476 msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
5477 sizeof(struct snd_soc_codec_conf),
5478 GFP_KERNEL);
5479 if (!msm_codec_conf) {
5480 ret = -ENOMEM;
5481 goto err_codec_conf;
5482 }
5483
5484 for (i = 0; i < card->num_aux_devs; i++) {
5485 dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
5486 GFP_KERNEL);
5487 if (!dev_name_str) {
5488 ret = -ENOMEM;
5489 goto err_dev_str;
5490 }
5491
5492 ret = of_property_read_string_index(pdev->dev.of_node,
5493 "qcom,wsa-aux-dev-prefix",
5494 wsa881x_dev_info[i].index,
5495 wsa_auxdev_name_prefix);
5496 if (ret) {
5497 dev_err(&pdev->dev,
5498 "%s: failed to read wsa aux dev prefix, ret = %d\n",
5499 __func__, ret);
5500 ret = -EINVAL;
5501 goto err_dt_prop;
5502 }
5503
5504 snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
5505 msm_aux_dev[i].name = dev_name_str;
5506 msm_aux_dev[i].codec_name = NULL;
5507 msm_aux_dev[i].codec_of_node =
5508 wsa881x_dev_info[i].of_node;
5509 msm_aux_dev[i].init = msm_wsa881x_init;
5510 msm_codec_conf[i].dev_name = NULL;
5511 msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
5512 msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
5513 }
5514 card->codec_conf = msm_codec_conf;
5515 card->aux_dev = msm_aux_dev;
5516
5517 return 0;
5518
5519err_dt_prop:
5520 devm_kfree(&pdev->dev, dev_name_str);
5521err_dev_str:
5522 devm_kfree(&pdev->dev, msm_codec_conf);
5523err_codec_conf:
5524 devm_kfree(&pdev->dev, msm_aux_dev);
5525err_auxdev_mem:
5526err_dev_node:
5527 devm_kfree(&pdev->dev, wsa881x_dev_info);
5528err_mem:
5529err_dt:
5530 return ret;
5531}
5532
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5533static void i2s_auxpcm_init(struct platform_device *pdev)
5534{
5535 int count;
5536 u32 mi2s_master_slave[MI2S_MAX];
5537 u32 mi2s_ext_mclk[MI2S_MAX];
5538 int ret;
5539
5540 for (count = 0; count < MI2S_MAX; count++) {
5541 mutex_init(&mi2s_intf_conf[count].lock);
5542 mi2s_intf_conf[count].ref_cnt = 0;
5543 }
5544
5545 ret = of_property_read_u32_array(pdev->dev.of_node,
5546 "qcom,msm-mi2s-master",
5547 mi2s_master_slave, MI2S_MAX);
5548 if (ret) {
5549 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
5550 __func__);
5551 } else {
5552 for (count = 0; count < MI2S_MAX; count++) {
5553 mi2s_intf_conf[count].msm_is_mi2s_master =
5554 mi2s_master_slave[count];
5555 }
5556 }
5557
5558 ret = of_property_read_u32_array(pdev->dev.of_node,
5559 "qcom,msm-mi2s-ext-mclk",
5560 mi2s_ext_mclk, MI2S_MAX);
5561 if (ret) {
5562 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
5563 __func__);
5564 } else {
5565 for (count = 0; count < MI2S_MAX; count++)
5566 mi2s_intf_conf[count].msm_is_ext_mclk =
5567 mi2s_ext_mclk[count];
5568 }
5569}
5570
5571static const struct of_device_id sdm660_asoc_machine_of_match[] = {
5572 { .compatible = "qcom,sdm660-asoc-snd",
5573 .data = "internal_codec"},
5574 { .compatible = "qcom,sdm660-asoc-snd-tasha",
5575 .data = "tasha_codec"},
5576 { .compatible = "qcom,sdm660-asoc-snd-tavil",
5577 .data = "tavil_codec"},
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]5578 { .compatible = "qcom,sdm670-asoc-snd",
5579 .data = "internal_codec"},
5580 { .compatible = "qcom,sdm670-asoc-snd-tasha",
5581 .data = "tasha_codec"},
5582 { .compatible = "qcom,sdm670-asoc-snd-tavil",
5583 .data = "tavil_codec"},
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5584 { .compatible = "qcom,qcs605-dig-asoc-snd",
5585 .data = "digital_codec"},
Meng Wangce5655b2018-07-06 10:47:38 +0800[diff] [blame]5586 { .compatible = "qcom,qcs605-asoc-snd-tavil",
5587 .data = "tavil_codec"},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5588 {},
5589};
5590
5591static int msm_asoc_machine_probe(struct platform_device *pdev)
5592{
5593 struct snd_soc_card *card = NULL;
5594 struct msm_asoc_mach_data *pdata = NULL;
5595 const char *mclk = "qcom,msm-mclk-freq";
5596 int ret = -EINVAL, id;
5597 const struct of_device_id *match;
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5598 const char *usb_c_dt = "qcom,msm-mbhc-usbc-audio-supported";
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5599
5600 pdata = devm_kzalloc(&pdev->dev,
5601 sizeof(struct msm_asoc_mach_data),
5602 GFP_KERNEL);
5603 if (!pdata)
5604 return -ENOMEM;
5605
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]5606 msm_set_codec_reg_done(false);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5607 match = of_match_node(sdm660_asoc_machine_of_match,
5608 pdev->dev.of_node);
5609 if (!match)
5610 goto err;
5611
5612 ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
5613 if (ret) {
5614 dev_err(&pdev->dev,
5615 "%s: missing %s in dt node\n", __func__, mclk);
5616 id = DEFAULT_MCLK_RATE;
5617 }
5618 pdata->mclk_freq = id;
5619
5620 if (!strcmp(match->data, "tasha_codec") ||
5621 !strcmp(match->data, "tavil_codec")) {
5622 if (!strcmp(match->data, "tasha_codec"))
5623 pdata->snd_card_val = EXT_SND_CARD_TASHA;
5624 else
5625 pdata->snd_card_val = EXT_SND_CARD_TAVIL;
5626 ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
5627 if (ret)
5628 goto err;
5629 } else if (!strcmp(match->data, "internal_codec")) {
5630 pdata->snd_card_val = INT_SND_CARD;
5631 ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
5632 if (ret)
5633 goto err;
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5634 } else if (!strcmp(match->data, "digital_codec")) {
5635 pdata->snd_card_val = INT_DIG_SND_CARD;
5636 ret = msm_int_cdc_init(pdev, pdata, &card, NULL);
5637 if (ret)
5638 goto err;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5639 } else {
5640 dev_err(&pdev->dev,
5641 "%s: Not a matching DT sound node\n", __func__);
5642 goto err;
5643 }
5644 if (!card)
5645 goto err;
5646
5647 if (pdata->snd_card_val == INT_SND_CARD) {
5648 /*reading the gpio configurations from dtsi file*/
5649 pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
5650 "qcom,cdc-pdm-gpios", 0);
5651 pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
5652 "qcom,cdc-comp-gpios", 0);
5653 pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
5654 "qcom,cdc-dmic-gpios", 0);
5655 pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
5656 "qcom,cdc-ext-spk-gpios", 0);
5657 }
5658
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5659 if (pdata->snd_card_val == INT_DIG_SND_CARD) {
5660 /*reading the gpio configurations from dtsi file*/
5661 pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
5662 "qcom,cdc-dmic-gpios", 0);
5663 }
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]5664 pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
5665 "qcom,pri-mi2s-gpios", 0);
5666 pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
5667 "qcom,sec-mi2s-gpios", 0);
5668 pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
5669 "qcom,tert-mi2s-gpios", 0);
5670 pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
5671 "qcom,quat-mi2s-gpios", 0);
5672 pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
5673 "qcom,quin-mi2s-gpios", 0);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5674 /*
5675 * Parse US-Euro gpio info from DT. Report no error if us-euro
5676 * entry is not found in DT file as some targets do not support
5677 * US-Euro detection
5678 */
5679 pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
5680 "qcom,us-euro-gpios", 0);
5681 if (!gpio_is_valid(pdata->us_euro_gpio))
5682 pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
5683 "qcom,us-euro-gpios", 0);
5684 if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
5685 dev_dbg(&pdev->dev, "property %s not detected in node %s",
5686 "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
5687 } else {
5688 dev_dbg(&pdev->dev, "%s detected",
5689 "qcom,us-euro-gpios");
5690 mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
5691 }
5692
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5693 if (of_find_property(pdev->dev.of_node, usb_c_dt, NULL))
5694 mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
5695
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5696 ret = msm_prepare_us_euro(card);
5697 if (ret)
5698 dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
5699 ret);
5700
5701 i2s_auxpcm_init(pdev);
5702
5703 ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
5704 if (ret)
5705 goto err;
5706
5707 ret = msm_populate_dai_link_component_of_node(pdata, card);
5708 if (ret) {
5709 ret = -EPROBE_DEFER;
5710 goto err;
5711 }
5712
5713 if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
5714 ret = msm_init_wsa_dev(pdev, card);
5715 if (ret)
5716 goto err;
5717 }
5718
5719 ret = devm_snd_soc_register_card(&pdev->dev, card);
5720 if (ret == -EPROBE_DEFER) {
5721 if (codec_reg_done) {
5722 /*
5723 * return failure as EINVAL since other codec
5724 * registered sound card successfully.
5725 * This avoids any further probe calls.
5726 */
5727 ret = -EINVAL;
5728 }
5729 goto err;
5730 } else if (ret) {
5731 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
5732 ret);
5733 goto err;
5734 }
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5735 if (pdata->snd_card_val > INT_MAX_SND_CARD)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5736 msm_ext_register_audio_notifier(pdev);
5737
5738 return 0;
5739err:
5740 if (pdata->us_euro_gpio > 0) {
5741 dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
5742 __func__, pdata->us_euro_gpio);
5743 pdata->us_euro_gpio = 0;
5744 }
5745 if (pdata->hph_en1_gpio > 0) {
5746 dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
5747 __func__, pdata->hph_en1_gpio);
5748 gpio_free(pdata->hph_en1_gpio);
5749 pdata->hph_en1_gpio = 0;
5750 }
5751 if (pdata->hph_en0_gpio > 0) {
5752 dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
5753 __func__, pdata->hph_en0_gpio);
5754 gpio_free(pdata->hph_en0_gpio);
5755 pdata->hph_en0_gpio = 0;
5756 }
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5757 devm_kfree(&pdev->dev, pdata);
5758 return ret;
5759}
5760
5761static int msm_asoc_machine_remove(struct platform_device *pdev)
5762{
5763 struct snd_soc_card *card = platform_get_drvdata(pdev);
5764 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5765
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5766 if (pdata->snd_card_val <= INT_MAX_SND_CARD)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5767 mutex_destroy(&pdata->cdc_int_mclk0_mutex);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5768
Meng Wangc4ef3b52017-10-18 10:57:15 +0800[diff] [blame]5769 if (gpio_is_valid(pdata->us_euro_gpio)) {
5770 gpio_free(pdata->us_euro_gpio);
5771 pdata->us_euro_gpio = 0;
5772 }
5773 if (gpio_is_valid(pdata->hph_en1_gpio)) {
5774 gpio_free(pdata->hph_en1_gpio);
5775 pdata->hph_en1_gpio = 0;
5776 }
5777 if (gpio_is_valid(pdata->hph_en0_gpio)) {
5778 gpio_free(pdata->hph_en0_gpio);
5779 pdata->hph_en0_gpio = 0;
5780 }
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]5781
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5782 if (pdata->snd_card_val > INT_MAX_SND_CARD)
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]5783 audio_notifier_deregister("sdm660");
5784
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5785 snd_soc_unregister_card(card);
5786 return 0;
5787}
5788
5789static struct platform_driver sdm660_asoc_machine_driver = {
5790 .driver = {
5791 .name = DRV_NAME,
5792 .owner = THIS_MODULE,
5793 .pm = &snd_soc_pm_ops,
5794 .of_match_table = sdm660_asoc_machine_of_match,
5795 },
5796 .probe = msm_asoc_machine_probe,
5797 .remove = msm_asoc_machine_remove,
5798};
5799module_platform_driver(sdm660_asoc_machine_driver);
5800
5801MODULE_DESCRIPTION("ALSA SoC msm");
5802MODULE_LICENSE("GPL v2");
5803MODULE_ALIAS("platform:" DRV_NAME);
5804MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);