Laxminath Kasam | 468ece3 | 2017-11-28 12:40:22 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/platform_device.h> |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/kthread.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/pm_runtime.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/debugfs.h> |
| 26 | #include <linux/uaccess.h> |
Laxminath Kasam | 605b42f | 2017-08-01 22:02:15 +0530 | [diff] [blame] | 27 | #include <soc/soundwire.h> |
| 28 | #include <soc/swr-wcd.h> |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 29 | #include "swrm_registers.h" |
| 30 | #include "swr-wcd-ctrl.h" |
| 31 | |
| 32 | #define SWR_BROADCAST_CMD_ID 0x0F |
| 33 | #define SWR_AUTO_SUSPEND_DELAY 3 /* delay in sec */ |
| 34 | #define SWR_DEV_ID_MASK 0xFFFFFFFF |
| 35 | #define SWR_REG_VAL_PACK(data, dev, id, reg) \ |
| 36 | ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) |
| 37 | |
| 38 | /* pm runtime auto suspend timer in msecs */ |
| 39 | static int auto_suspend_timer = SWR_AUTO_SUSPEND_DELAY * 1000; |
| 40 | module_param(auto_suspend_timer, int, 0664); |
| 41 | MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend"); |
| 42 | |
| 43 | static u8 mstr_ports[] = {100, 101, 102, 103, 104, 105, 106, 107}; |
| 44 | static u8 mstr_port_type[] = {SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT, |
| 45 | SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT, |
| 46 | SWR_VISENSE_PORT, SWR_VISENSE_PORT}; |
| 47 | |
| 48 | struct usecase uc[] = { |
| 49 | {0, 0, 0}, /* UC0: no ports */ |
| 50 | {1, 1, 2400}, /* UC1: Spkr */ |
| 51 | {1, 4, 600}, /* UC2: Compander */ |
| 52 | {1, 2, 300}, /* UC3: Smart Boost */ |
| 53 | {1, 2, 1200}, /* UC4: VI Sense */ |
| 54 | {4, 9, 4500}, /* UC5: Spkr + Comp + SB + VI */ |
| 55 | {8, 18, 9000}, /* UC6: 2*(Spkr + Comp + SB + VI) */ |
| 56 | {2, 2, 4800}, /* UC7: 2*Spkr */ |
| 57 | {2, 5, 3000}, /* UC8: Spkr + Comp */ |
| 58 | {4, 10, 6000}, /* UC9: 2*(Spkr + Comp) */ |
| 59 | {3, 7, 3300}, /* UC10: Spkr + Comp + SB */ |
| 60 | {6, 14, 6600}, /* UC11: 2*(Spkr + Comp + SB) */ |
| 61 | {2, 3, 2700}, /* UC12: Spkr + SB */ |
| 62 | {4, 6, 5400}, /* UC13: 2*(Spkr + SB) */ |
| 63 | {3, 5, 3900}, /* UC14: Spkr + SB + VI */ |
| 64 | {6, 10, 7800}, /* UC15: 2*(Spkr + SB + VI) */ |
| 65 | {2, 3, 3600}, /* UC16: Spkr + VI */ |
| 66 | {4, 6, 7200}, /* UC17: 2*(Spkr + VI) */ |
| 67 | {3, 7, 4200}, /* UC18: Spkr + Comp + VI */ |
| 68 | {6, 14, 8400}, /* UC19: 2*(Spkr + Comp + VI) */ |
| 69 | }; |
| 70 | #define MAX_USECASE ARRAY_SIZE(uc) |
| 71 | |
| 72 | struct port_params pp[MAX_USECASE][SWR_MSTR_PORT_LEN] = { |
| 73 | /* UC 0 */ |
| 74 | { |
| 75 | {0, 0, 0}, |
| 76 | }, |
| 77 | /* UC 1 */ |
| 78 | { |
| 79 | {7, 1, 0}, |
| 80 | }, |
| 81 | /* UC 2 */ |
| 82 | { |
| 83 | {31, 2, 0}, |
| 84 | }, |
| 85 | /* UC 3 */ |
| 86 | { |
| 87 | {63, 12, 31}, |
| 88 | }, |
| 89 | /* UC 4 */ |
| 90 | { |
| 91 | {15, 7, 0}, |
| 92 | }, |
| 93 | /* UC 5 */ |
| 94 | { |
| 95 | {7, 1, 0}, |
| 96 | {31, 2, 0}, |
| 97 | {63, 12, 31}, |
| 98 | {15, 7, 0}, |
| 99 | }, |
| 100 | /* UC 6 */ |
| 101 | { |
| 102 | {7, 1, 0}, |
| 103 | {31, 2, 0}, |
| 104 | {63, 12, 31}, |
| 105 | {15, 7, 0}, |
| 106 | {7, 6, 0}, |
| 107 | {31, 18, 0}, |
| 108 | {63, 13, 31}, |
| 109 | {15, 10, 0}, |
| 110 | }, |
| 111 | /* UC 7 */ |
| 112 | { |
| 113 | {7, 1, 0}, |
| 114 | {7, 6, 0}, |
| 115 | |
| 116 | }, |
| 117 | /* UC 8 */ |
| 118 | { |
| 119 | {7, 1, 0}, |
| 120 | {31, 2, 0}, |
| 121 | }, |
| 122 | /* UC 9 */ |
| 123 | { |
| 124 | {7, 1, 0}, |
| 125 | {31, 2, 0}, |
| 126 | {7, 6, 0}, |
| 127 | {31, 18, 0}, |
| 128 | }, |
| 129 | /* UC 10 */ |
| 130 | { |
| 131 | {7, 1, 0}, |
| 132 | {31, 2, 0}, |
| 133 | {63, 12, 31}, |
| 134 | }, |
| 135 | /* UC 11 */ |
| 136 | { |
| 137 | {7, 1, 0}, |
| 138 | {31, 2, 0}, |
| 139 | {63, 12, 31}, |
| 140 | {7, 6, 0}, |
| 141 | {31, 18, 0}, |
| 142 | {63, 13, 31}, |
| 143 | }, |
| 144 | /* UC 12 */ |
| 145 | { |
| 146 | {7, 1, 0}, |
| 147 | {63, 12, 31}, |
| 148 | }, |
| 149 | /* UC 13 */ |
| 150 | { |
| 151 | {7, 1, 0}, |
| 152 | {63, 12, 31}, |
| 153 | {7, 6, 0}, |
| 154 | {63, 13, 31}, |
| 155 | }, |
| 156 | /* UC 14 */ |
| 157 | { |
| 158 | {7, 1, 0}, |
| 159 | {63, 12, 31}, |
| 160 | {15, 7, 0}, |
| 161 | }, |
| 162 | /* UC 15 */ |
| 163 | { |
| 164 | {7, 1, 0}, |
| 165 | {63, 12, 31}, |
| 166 | {15, 7, 0}, |
| 167 | {7, 6, 0}, |
| 168 | {63, 13, 31}, |
| 169 | {15, 10, 0}, |
| 170 | }, |
| 171 | /* UC 16 */ |
| 172 | { |
| 173 | {7, 1, 0}, |
| 174 | {15, 7, 0}, |
| 175 | }, |
| 176 | /* UC 17 */ |
| 177 | { |
| 178 | {7, 1, 0}, |
| 179 | {15, 7, 0}, |
| 180 | {7, 6, 0}, |
| 181 | {15, 10, 0}, |
| 182 | }, |
| 183 | /* UC 18 */ |
| 184 | { |
| 185 | {7, 1, 0}, |
| 186 | {31, 2, 0}, |
| 187 | {15, 7, 0}, |
| 188 | }, |
| 189 | /* UC 19 */ |
| 190 | { |
| 191 | {7, 1, 0}, |
| 192 | {31, 2, 0}, |
| 193 | {15, 7, 0}, |
| 194 | {7, 6, 0}, |
| 195 | {31, 18, 0}, |
| 196 | {15, 10, 0}, |
| 197 | }, |
| 198 | }; |
| 199 | |
| 200 | enum { |
| 201 | SWR_NOT_PRESENT, /* Device is detached/not present on the bus */ |
| 202 | SWR_ATTACHED_OK, /* Device is attached */ |
| 203 | SWR_ALERT, /* Device alters master for any interrupts */ |
| 204 | SWR_RESERVED, /* Reserved */ |
| 205 | }; |
| 206 | |
| 207 | #define SWRM_MAX_PORT_REG 40 |
| 208 | #define SWRM_MAX_INIT_REG 8 |
| 209 | |
| 210 | #define SWR_MSTR_MAX_REG_ADDR 0x1740 |
| 211 | #define SWR_MSTR_START_REG_ADDR 0x00 |
| 212 | #define SWR_MSTR_MAX_BUF_LEN 32 |
| 213 | #define BYTES_PER_LINE 12 |
| 214 | #define SWR_MSTR_RD_BUF_LEN 8 |
| 215 | #define SWR_MSTR_WR_BUF_LEN 32 |
| 216 | |
| 217 | static void swrm_copy_data_port_config(struct swr_master *master, |
| 218 | u8 inactive_bank); |
| 219 | static struct swr_mstr_ctrl *dbgswrm; |
| 220 | static struct dentry *debugfs_swrm_dent; |
| 221 | static struct dentry *debugfs_peek; |
| 222 | static struct dentry *debugfs_poke; |
| 223 | static struct dentry *debugfs_reg_dump; |
| 224 | static unsigned int read_data; |
| 225 | |
| 226 | |
| 227 | static bool swrm_is_msm_variant(int val) |
| 228 | { |
| 229 | return (val == SWRM_VERSION_1_3); |
| 230 | } |
| 231 | |
| 232 | static int swrm_debug_open(struct inode *inode, struct file *file) |
| 233 | { |
| 234 | file->private_data = inode->i_private; |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static int get_parameters(char *buf, u32 *param1, int num_of_par) |
| 239 | { |
| 240 | char *token; |
| 241 | int base, cnt; |
| 242 | |
| 243 | token = strsep(&buf, " "); |
| 244 | for (cnt = 0; cnt < num_of_par; cnt++) { |
| 245 | if (token) { |
| 246 | if ((token[1] == 'x') || (token[1] == 'X')) |
| 247 | base = 16; |
| 248 | else |
| 249 | base = 10; |
| 250 | |
| 251 | if (kstrtou32(token, base, ¶m1[cnt]) != 0) |
| 252 | return -EINVAL; |
| 253 | |
| 254 | token = strsep(&buf, " "); |
| 255 | } else |
| 256 | return -EINVAL; |
| 257 | } |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | static ssize_t swrm_reg_show(char __user *ubuf, size_t count, |
| 262 | loff_t *ppos) |
| 263 | { |
| 264 | int i, reg_val, len; |
| 265 | ssize_t total = 0; |
| 266 | char tmp_buf[SWR_MSTR_MAX_BUF_LEN]; |
| 267 | |
| 268 | if (!ubuf || !ppos) |
| 269 | return 0; |
| 270 | |
| 271 | for (i = (((int) *ppos / BYTES_PER_LINE) + SWR_MSTR_START_REG_ADDR); |
| 272 | i <= SWR_MSTR_MAX_REG_ADDR; i += 4) { |
| 273 | reg_val = dbgswrm->read(dbgswrm->handle, i); |
| 274 | len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val); |
| 275 | if ((total + len) >= count - 1) |
| 276 | break; |
| 277 | if (copy_to_user((ubuf + total), tmp_buf, len)) { |
| 278 | pr_err("%s: fail to copy reg dump\n", __func__); |
| 279 | total = -EFAULT; |
| 280 | goto copy_err; |
| 281 | } |
| 282 | *ppos += len; |
| 283 | total += len; |
| 284 | } |
| 285 | |
| 286 | copy_err: |
| 287 | return total; |
| 288 | } |
| 289 | |
| 290 | static ssize_t swrm_debug_read(struct file *file, char __user *ubuf, |
| 291 | size_t count, loff_t *ppos) |
| 292 | { |
| 293 | char lbuf[SWR_MSTR_RD_BUF_LEN]; |
| 294 | char *access_str; |
| 295 | ssize_t ret_cnt; |
| 296 | |
| 297 | if (!count || !file || !ppos || !ubuf) |
| 298 | return -EINVAL; |
| 299 | |
| 300 | access_str = file->private_data; |
| 301 | if (*ppos < 0) |
| 302 | return -EINVAL; |
| 303 | |
| 304 | if (!strcmp(access_str, "swrm_peek")) { |
| 305 | snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data); |
| 306 | ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf, |
| 307 | strnlen(lbuf, 7)); |
| 308 | } else if (!strcmp(access_str, "swrm_reg_dump")) { |
| 309 | ret_cnt = swrm_reg_show(ubuf, count, ppos); |
| 310 | } else { |
| 311 | pr_err("%s: %s not permitted to read\n", __func__, access_str); |
| 312 | ret_cnt = -EPERM; |
| 313 | } |
| 314 | return ret_cnt; |
| 315 | } |
| 316 | |
| 317 | static ssize_t swrm_debug_write(struct file *filp, |
| 318 | const char __user *ubuf, size_t cnt, loff_t *ppos) |
| 319 | { |
| 320 | char lbuf[SWR_MSTR_WR_BUF_LEN]; |
| 321 | int rc; |
| 322 | u32 param[5]; |
| 323 | char *access_str; |
| 324 | |
| 325 | if (!filp || !ppos || !ubuf) |
| 326 | return -EINVAL; |
| 327 | |
| 328 | access_str = filp->private_data; |
| 329 | if (cnt > sizeof(lbuf) - 1) |
| 330 | return -EINVAL; |
| 331 | |
| 332 | rc = copy_from_user(lbuf, ubuf, cnt); |
| 333 | if (rc) |
| 334 | return -EFAULT; |
| 335 | |
| 336 | lbuf[cnt] = '\0'; |
| 337 | if (!strcmp(access_str, "swrm_poke")) { |
| 338 | /* write */ |
| 339 | rc = get_parameters(lbuf, param, 2); |
| 340 | if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) && |
| 341 | (param[1] <= 0xFFFFFFFF) && |
| 342 | (rc == 0)) |
| 343 | rc = dbgswrm->write(dbgswrm->handle, param[0], |
| 344 | param[1]); |
| 345 | else |
| 346 | rc = -EINVAL; |
| 347 | } else if (!strcmp(access_str, "swrm_peek")) { |
| 348 | /* read */ |
| 349 | rc = get_parameters(lbuf, param, 1); |
| 350 | if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) && (rc == 0)) |
| 351 | read_data = dbgswrm->read(dbgswrm->handle, param[0]); |
| 352 | else |
| 353 | rc = -EINVAL; |
| 354 | } |
| 355 | if (rc == 0) |
| 356 | rc = cnt; |
| 357 | else |
| 358 | pr_err("%s: rc = %d\n", __func__, rc); |
| 359 | |
| 360 | return rc; |
| 361 | } |
| 362 | |
| 363 | static const struct file_operations swrm_debug_ops = { |
| 364 | .open = swrm_debug_open, |
| 365 | .write = swrm_debug_write, |
| 366 | .read = swrm_debug_read, |
| 367 | }; |
| 368 | |
| 369 | static int swrm_set_ch_map(struct swr_mstr_ctrl *swrm, void *data) |
| 370 | { |
| 371 | struct swr_mstr_port *pinfo = (struct swr_mstr_port *)data; |
| 372 | |
| 373 | swrm->mstr_port = kzalloc(sizeof(struct swr_mstr_port), GFP_KERNEL); |
| 374 | if (swrm->mstr_port == NULL) |
| 375 | return -ENOMEM; |
| 376 | swrm->mstr_port->num_port = pinfo->num_port; |
| 377 | swrm->mstr_port->port = kzalloc((pinfo->num_port * sizeof(u8)), |
| 378 | GFP_KERNEL); |
| 379 | if (!swrm->mstr_port->port) { |
| 380 | kfree(swrm->mstr_port); |
| 381 | swrm->mstr_port = NULL; |
| 382 | return -ENOMEM; |
| 383 | } |
| 384 | memcpy(swrm->mstr_port->port, pinfo->port, pinfo->num_port); |
| 385 | return 0; |
| 386 | } |
| 387 | |
| 388 | static bool swrm_is_port_en(struct swr_master *mstr) |
| 389 | { |
| 390 | return !!(mstr->num_port); |
| 391 | } |
| 392 | |
| 393 | static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable) |
| 394 | { |
| 395 | if (!swrm->clk || !swrm->handle) |
| 396 | return -EINVAL; |
| 397 | |
| 398 | if (enable) { |
Laxminath Kasam | 8f7ccc2 | 2017-08-28 17:35:04 +0530 | [diff] [blame] | 399 | swrm->clk_ref_count++; |
| 400 | if (swrm->clk_ref_count == 1) { |
| 401 | swrm->clk(swrm->handle, true); |
| 402 | swrm->state = SWR_MSTR_UP; |
| 403 | } |
| 404 | } else if (--swrm->clk_ref_count == 0) { |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 405 | swrm->clk(swrm->handle, false); |
| 406 | swrm->state = SWR_MSTR_DOWN; |
Laxminath Kasam | 8f7ccc2 | 2017-08-28 17:35:04 +0530 | [diff] [blame] | 407 | } else if (swrm->clk_ref_count < 0) { |
| 408 | pr_err("%s: swrm clk count mismatch\n", __func__); |
| 409 | swrm->clk_ref_count = 0; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 410 | } |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static int swrm_get_port_config(struct swr_master *master) |
| 415 | { |
| 416 | u32 ch_rate = 0; |
| 417 | u32 num_ch = 0; |
| 418 | int i, uc_idx; |
| 419 | u32 portcount = 0; |
| 420 | |
| 421 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 422 | if (master->port[i].port_en) { |
| 423 | ch_rate += master->port[i].ch_rate; |
| 424 | num_ch += master->port[i].num_ch; |
| 425 | portcount++; |
| 426 | } |
| 427 | } |
| 428 | for (i = 0; i < ARRAY_SIZE(uc); i++) { |
| 429 | if ((uc[i].num_port == portcount) && |
| 430 | (uc[i].num_ch == num_ch) && |
| 431 | (uc[i].chrate == ch_rate)) { |
| 432 | uc_idx = i; |
| 433 | break; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | if (i >= ARRAY_SIZE(uc)) { |
| 438 | dev_err(&master->dev, |
| 439 | "%s: usecase port:%d, num_ch:%d, chrate:%d not found\n", |
| 440 | __func__, master->num_port, num_ch, ch_rate); |
| 441 | return -EINVAL; |
| 442 | } |
| 443 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 444 | if (master->port[i].port_en) { |
| 445 | master->port[i].sinterval = pp[uc_idx][i].si; |
| 446 | master->port[i].offset1 = pp[uc_idx][i].off1; |
| 447 | master->port[i].offset2 = pp[uc_idx][i].off2; |
| 448 | } |
| 449 | } |
| 450 | return 0; |
| 451 | } |
| 452 | |
| 453 | static int swrm_get_master_port(u8 *mstr_port_id, u8 slv_port_id) |
| 454 | { |
| 455 | int i; |
| 456 | |
| 457 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 458 | if (mstr_ports[i] == slv_port_id) { |
| 459 | *mstr_port_id = i; |
| 460 | return 0; |
| 461 | } |
| 462 | } |
| 463 | return -EINVAL; |
| 464 | } |
| 465 | |
| 466 | static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, |
| 467 | u8 dev_addr, u16 reg_addr) |
| 468 | { |
| 469 | u32 val; |
| 470 | u8 id = *cmd_id; |
| 471 | |
| 472 | if (id != SWR_BROADCAST_CMD_ID) { |
| 473 | if (id < 14) |
| 474 | id += 1; |
| 475 | else |
| 476 | id = 0; |
| 477 | *cmd_id = id; |
| 478 | } |
| 479 | val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); |
| 480 | |
| 481 | return val; |
| 482 | } |
| 483 | |
| 484 | static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data, |
| 485 | u8 dev_addr, u8 cmd_id, u16 reg_addr, |
| 486 | u32 len) |
| 487 | { |
| 488 | u32 val; |
| 489 | int ret = 0; |
| 490 | |
| 491 | val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); |
| 492 | ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_RD_CMD, val); |
| 493 | if (ret < 0) { |
| 494 | dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n", |
| 495 | __func__, val, ret); |
| 496 | goto err; |
| 497 | } |
| 498 | *cmd_data = swrm->read(swrm->handle, SWRM_CMD_FIFO_RD_FIFO_ADDR); |
| 499 | dev_dbg(swrm->dev, |
| 500 | "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n", |
| 501 | __func__, reg_addr, cmd_id, dev_addr, *cmd_data); |
| 502 | err: |
| 503 | return ret; |
| 504 | } |
| 505 | |
| 506 | static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data, |
| 507 | u8 dev_addr, u8 cmd_id, u16 reg_addr) |
| 508 | { |
| 509 | u32 val; |
| 510 | int ret = 0; |
| 511 | |
| 512 | if (!cmd_id) |
| 513 | val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, |
| 514 | dev_addr, reg_addr); |
| 515 | else |
| 516 | val = swrm_get_packed_reg_val(&cmd_id, cmd_data, |
| 517 | dev_addr, reg_addr); |
| 518 | |
| 519 | dev_dbg(swrm->dev, |
| 520 | "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n", |
| 521 | __func__, reg_addr, cmd_id, dev_addr, cmd_data); |
| 522 | ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_WR_CMD, val); |
| 523 | if (ret < 0) { |
| 524 | dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n", |
| 525 | __func__, val, ret); |
| 526 | goto err; |
| 527 | } |
| 528 | if (cmd_id == 0xF) { |
| 529 | /* |
| 530 | * sleep for 10ms for MSM soundwire variant to allow broadcast |
| 531 | * command to complete. |
| 532 | */ |
| 533 | if (swrm_is_msm_variant(swrm->version)) |
| 534 | usleep_range(10000, 10100); |
| 535 | else |
| 536 | wait_for_completion_timeout(&swrm->broadcast, |
| 537 | (2 * HZ/10)); |
| 538 | } |
| 539 | err: |
| 540 | return ret; |
| 541 | } |
| 542 | |
| 543 | static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr, |
| 544 | void *buf, u32 len) |
| 545 | { |
| 546 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 547 | int ret = 0; |
| 548 | int val; |
| 549 | u8 *reg_val = (u8 *)buf; |
| 550 | |
| 551 | if (!swrm) { |
| 552 | dev_err(&master->dev, "%s: swrm is NULL\n", __func__); |
| 553 | return -EINVAL; |
| 554 | } |
| 555 | |
| 556 | if (dev_num) |
| 557 | ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr, |
| 558 | len); |
| 559 | else |
| 560 | val = swrm->read(swrm->handle, reg_addr); |
| 561 | |
| 562 | if (!ret) |
| 563 | *reg_val = (u8)val; |
| 564 | |
| 565 | pm_runtime_mark_last_busy(&swrm->pdev->dev); |
| 566 | |
| 567 | return ret; |
| 568 | } |
| 569 | |
| 570 | static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr, |
| 571 | const void *buf) |
| 572 | { |
| 573 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 574 | int ret = 0; |
| 575 | u8 reg_val = *(u8 *)buf; |
| 576 | |
| 577 | if (!swrm) { |
| 578 | dev_err(&master->dev, "%s: swrm is NULL\n", __func__); |
| 579 | return -EINVAL; |
| 580 | } |
| 581 | |
| 582 | if (dev_num) |
| 583 | ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr); |
| 584 | else |
| 585 | ret = swrm->write(swrm->handle, reg_addr, reg_val); |
| 586 | |
| 587 | pm_runtime_mark_last_busy(&swrm->pdev->dev); |
| 588 | |
| 589 | return ret; |
| 590 | } |
| 591 | |
| 592 | static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg, |
| 593 | const void *buf, size_t len) |
| 594 | { |
| 595 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 596 | int ret = 0; |
| 597 | int i; |
| 598 | u32 *val; |
| 599 | u32 *swr_fifo_reg; |
| 600 | |
| 601 | if (!swrm || !swrm->handle) { |
| 602 | dev_err(&master->dev, "%s: swrm is NULL\n", __func__); |
| 603 | return -EINVAL; |
| 604 | } |
| 605 | if (len <= 0) |
| 606 | return -EINVAL; |
| 607 | |
| 608 | if (dev_num) { |
| 609 | swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL); |
| 610 | if (!swr_fifo_reg) { |
| 611 | ret = -ENOMEM; |
| 612 | goto err; |
| 613 | } |
| 614 | val = kcalloc(len, sizeof(u32), GFP_KERNEL); |
| 615 | if (!val) { |
| 616 | ret = -ENOMEM; |
| 617 | goto mem_fail; |
| 618 | } |
| 619 | |
| 620 | for (i = 0; i < len; i++) { |
| 621 | val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id, |
| 622 | ((u8 *)buf)[i], |
| 623 | dev_num, |
| 624 | ((u16 *)reg)[i]); |
| 625 | swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD; |
| 626 | } |
| 627 | ret = swrm->bulk_write(swrm->handle, swr_fifo_reg, val, len); |
| 628 | if (ret) { |
| 629 | dev_err(&master->dev, "%s: bulk write failed\n", |
| 630 | __func__); |
| 631 | ret = -EINVAL; |
| 632 | } |
| 633 | } else { |
| 634 | dev_err(&master->dev, |
| 635 | "%s: No support of Bulk write for master regs\n", |
| 636 | __func__); |
| 637 | ret = -EINVAL; |
| 638 | goto err; |
| 639 | } |
| 640 | kfree(val); |
| 641 | mem_fail: |
| 642 | kfree(swr_fifo_reg); |
| 643 | err: |
| 644 | pm_runtime_mark_last_busy(&swrm->pdev->dev); |
| 645 | return ret; |
| 646 | } |
| 647 | |
| 648 | static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm) |
| 649 | { |
| 650 | return (swrm->read(swrm->handle, SWRM_MCP_STATUS) & |
| 651 | SWRM_MCP_STATUS_BANK_NUM_MASK) ? 0 : 1; |
| 652 | } |
| 653 | |
| 654 | static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank, |
| 655 | u8 row, u8 col) |
| 656 | { |
Laxminath Kasam | 18e8808 | 2018-11-27 18:12:11 +0530 | [diff] [blame] | 657 | /* apply div2 setting for inactive bank before bank switch */ |
| 658 | swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00, |
| 659 | SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); |
| 660 | |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 661 | swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF, |
| 662 | SWRS_SCP_FRAME_CTRL_BANK(bank)); |
| 663 | } |
| 664 | |
| 665 | static struct swr_port_info *swrm_get_port(struct swr_master *master, |
| 666 | u8 port_id) |
| 667 | { |
| 668 | int i; |
| 669 | struct swr_port_info *port = NULL; |
| 670 | |
| 671 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 672 | port = &master->port[i]; |
| 673 | if (port->port_id == port_id) { |
| 674 | dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n", |
| 675 | __func__, port_id, i); |
| 676 | return port; |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | return NULL; |
| 681 | } |
| 682 | |
| 683 | static struct swr_port_info *swrm_get_avail_port(struct swr_master *master) |
| 684 | { |
| 685 | int i; |
| 686 | struct swr_port_info *port = NULL; |
| 687 | |
| 688 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 689 | port = &master->port[i]; |
| 690 | if (port->port_en) |
| 691 | continue; |
| 692 | |
| 693 | dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n", |
| 694 | __func__, port->port_id, i); |
| 695 | return port; |
| 696 | } |
| 697 | |
| 698 | return NULL; |
| 699 | } |
| 700 | |
| 701 | static struct swr_port_info *swrm_get_enabled_port(struct swr_master *master, |
| 702 | u8 port_id) |
| 703 | { |
| 704 | int i; |
| 705 | struct swr_port_info *port = NULL; |
| 706 | |
| 707 | for (i = 0; i < SWR_MSTR_PORT_LEN; i++) { |
| 708 | port = &master->port[i]; |
| 709 | if ((port->port_id == port_id) && (port->port_en == true)) |
| 710 | break; |
| 711 | } |
| 712 | if (i == SWR_MSTR_PORT_LEN) |
| 713 | port = NULL; |
| 714 | return port; |
| 715 | } |
| 716 | |
| 717 | static bool swrm_remove_from_group(struct swr_master *master) |
| 718 | { |
| 719 | struct swr_device *swr_dev; |
| 720 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 721 | bool is_removed = false; |
| 722 | |
| 723 | if (!swrm) |
| 724 | goto end; |
| 725 | |
| 726 | mutex_lock(&swrm->mlock); |
| 727 | if ((swrm->num_rx_chs > 1) && |
| 728 | (swrm->num_rx_chs == swrm->num_cfg_devs)) { |
| 729 | list_for_each_entry(swr_dev, &master->devices, |
| 730 | dev_list) { |
| 731 | swr_dev->group_id = SWR_GROUP_NONE; |
| 732 | master->gr_sid = 0; |
| 733 | } |
| 734 | is_removed = true; |
| 735 | } |
| 736 | mutex_unlock(&swrm->mlock); |
| 737 | |
| 738 | end: |
| 739 | return is_removed; |
| 740 | } |
| 741 | |
| 742 | static void swrm_cleanup_disabled_data_ports(struct swr_master *master, |
| 743 | u8 bank) |
| 744 | { |
| 745 | u32 value; |
| 746 | struct swr_port_info *port; |
| 747 | int i; |
| 748 | int port_type; |
| 749 | struct swrm_mports *mport, *mport_next = NULL; |
| 750 | int port_disable_cnt = 0; |
| 751 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 752 | |
| 753 | if (!swrm) { |
| 754 | pr_err("%s: swrm is null\n", __func__); |
| 755 | return; |
| 756 | } |
| 757 | |
| 758 | dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__, |
| 759 | master->num_port); |
| 760 | |
| 761 | mport = list_first_entry_or_null(&swrm->mport_list, |
| 762 | struct swrm_mports, |
| 763 | list); |
| 764 | if (!mport) { |
| 765 | dev_err(swrm->dev, "%s: list is empty\n", __func__); |
| 766 | return; |
| 767 | } |
| 768 | |
| 769 | for (i = 0; i < master->num_port; i++) { |
| 770 | port = swrm_get_port(master, mstr_ports[mport->id]); |
| 771 | if (!port || port->ch_en) |
| 772 | goto inc_loop; |
| 773 | |
| 774 | port_disable_cnt++; |
| 775 | port_type = mstr_port_type[mport->id]; |
| 776 | value = ((port->ch_en) |
| 777 | << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); |
| 778 | value |= ((port->offset2) |
| 779 | << SWRM_DP_PORT_CTRL_OFFSET2_SHFT); |
| 780 | value |= ((port->offset1) |
| 781 | << SWRM_DP_PORT_CTRL_OFFSET1_SHFT); |
| 782 | value |= port->sinterval; |
| 783 | |
| 784 | swrm->write(swrm->handle, |
| 785 | SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank), |
| 786 | value); |
| 787 | swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00, |
| 788 | SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank)); |
| 789 | |
| 790 | dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n", |
| 791 | __func__, mport->id, |
| 792 | (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value); |
| 793 | |
| 794 | inc_loop: |
| 795 | mport_next = list_next_entry(mport, list); |
| 796 | if (port && !port->ch_en) { |
| 797 | list_del(&mport->list); |
| 798 | kfree(mport); |
| 799 | } |
| 800 | if (!mport_next) { |
| 801 | dev_err(swrm->dev, "%s: end of list\n", __func__); |
| 802 | break; |
| 803 | } |
| 804 | mport = mport_next; |
| 805 | } |
| 806 | master->num_port -= port_disable_cnt; |
| 807 | |
| 808 | dev_dbg(swrm->dev, "%s:disable ports: %d, active ports (rem): %d\n", |
| 809 | __func__, port_disable_cnt, master->num_port); |
| 810 | } |
| 811 | |
| 812 | static void swrm_slvdev_datapath_control(struct swr_master *master, |
| 813 | bool enable) |
| 814 | { |
| 815 | u8 bank; |
| 816 | u32 value, n_col; |
| 817 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 818 | int mask = (SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK | |
| 819 | SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK | |
| 820 | SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK); |
| 821 | u8 inactive_bank; |
| 822 | |
| 823 | if (!swrm) { |
| 824 | pr_err("%s: swrm is null\n", __func__); |
| 825 | return; |
| 826 | } |
| 827 | |
| 828 | bank = get_inactive_bank_num(swrm); |
| 829 | |
| 830 | dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d\n", |
| 831 | __func__, enable, swrm->num_cfg_devs); |
| 832 | |
| 833 | if (enable) { |
| 834 | /* set Row = 48 and col = 16 */ |
| 835 | n_col = SWR_MAX_COL; |
| 836 | } else { |
| 837 | /* |
| 838 | * Do not change to 48x2 if number of channels configured |
| 839 | * as stereo and if disable datapath is called for the |
| 840 | * first slave device |
| 841 | */ |
| 842 | if (swrm->num_cfg_devs > 0) |
| 843 | n_col = SWR_MAX_COL; |
| 844 | else |
| 845 | n_col = SWR_MIN_COL; |
| 846 | |
| 847 | /* |
| 848 | * All ports are already disabled, no need to perform |
| 849 | * bank-switch and copy operation. This case can arise |
| 850 | * when speaker channels are enabled in stereo mode with |
| 851 | * BROADCAST and disabled in GROUP_NONE |
| 852 | */ |
| 853 | if (master->num_port == 0) |
| 854 | return; |
| 855 | } |
| 856 | |
| 857 | value = swrm->read(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank)); |
| 858 | value &= (~mask); |
| 859 | value |= ((0 << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) | |
| 860 | (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) | |
| 861 | (0 << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT)); |
| 862 | swrm->write(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value); |
| 863 | |
| 864 | dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__, |
| 865 | SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value); |
| 866 | |
| 867 | enable_bank_switch(swrm, bank, SWR_MAX_ROW, n_col); |
| 868 | |
| 869 | inactive_bank = bank ? 0 : 1; |
| 870 | if (enable) |
| 871 | swrm_copy_data_port_config(master, inactive_bank); |
| 872 | else |
| 873 | swrm_cleanup_disabled_data_ports(master, inactive_bank); |
| 874 | |
| 875 | if (!swrm_is_port_en(master)) { |
| 876 | dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n", |
| 877 | __func__); |
| 878 | pm_runtime_mark_last_busy(&swrm->pdev->dev); |
| 879 | pm_runtime_put_autosuspend(&swrm->pdev->dev); |
| 880 | } |
| 881 | } |
| 882 | |
| 883 | static void swrm_apply_port_config(struct swr_master *master) |
| 884 | { |
| 885 | u8 bank; |
| 886 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 887 | |
| 888 | if (!swrm) { |
| 889 | pr_err("%s: Invalid handle to swr controller\n", |
| 890 | __func__); |
| 891 | return; |
| 892 | } |
| 893 | |
| 894 | bank = get_inactive_bank_num(swrm); |
| 895 | dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n", |
| 896 | __func__, bank, master->num_port); |
| 897 | |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 898 | swrm_copy_data_port_config(master, bank); |
| 899 | } |
| 900 | |
| 901 | static void swrm_copy_data_port_config(struct swr_master *master, u8 bank) |
| 902 | { |
| 903 | u32 value; |
| 904 | struct swr_port_info *port; |
| 905 | int i; |
| 906 | int port_type; |
| 907 | struct swrm_mports *mport; |
| 908 | u32 reg[SWRM_MAX_PORT_REG]; |
| 909 | u32 val[SWRM_MAX_PORT_REG]; |
| 910 | int len = 0; |
| 911 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 912 | |
| 913 | if (!swrm) { |
| 914 | pr_err("%s: swrm is null\n", __func__); |
| 915 | return; |
| 916 | } |
| 917 | |
| 918 | dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__, |
| 919 | master->num_port); |
| 920 | |
| 921 | mport = list_first_entry_or_null(&swrm->mport_list, |
| 922 | struct swrm_mports, |
| 923 | list); |
| 924 | if (!mport) { |
| 925 | dev_err(swrm->dev, "%s: list is empty\n", __func__); |
| 926 | return; |
| 927 | } |
| 928 | for (i = 0; i < master->num_port; i++) { |
| 929 | |
| 930 | port = swrm_get_enabled_port(master, mstr_ports[mport->id]); |
| 931 | if (!port) |
| 932 | continue; |
| 933 | port_type = mstr_port_type[mport->id]; |
| 934 | if (!port->dev_id || (port->dev_id > master->num_dev)) { |
| 935 | dev_dbg(swrm->dev, "%s: invalid device id = %d\n", |
| 936 | __func__, port->dev_id); |
| 937 | continue; |
| 938 | } |
| 939 | value = ((port->ch_en) |
| 940 | << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); |
| 941 | value |= ((port->offset2) |
| 942 | << SWRM_DP_PORT_CTRL_OFFSET2_SHFT); |
| 943 | value |= ((port->offset1) |
| 944 | << SWRM_DP_PORT_CTRL_OFFSET1_SHFT); |
| 945 | value |= port->sinterval; |
| 946 | |
| 947 | reg[len] = SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank); |
| 948 | val[len++] = value; |
| 949 | |
| 950 | dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n", |
| 951 | __func__, mport->id, |
| 952 | (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value); |
| 953 | |
| 954 | reg[len] = SWRM_CMD_FIFO_WR_CMD; |
| 955 | val[len++] = SWR_REG_VAL_PACK(port->ch_en, port->dev_id, 0x00, |
| 956 | SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank)); |
| 957 | |
| 958 | reg[len] = SWRM_CMD_FIFO_WR_CMD; |
| 959 | val[len++] = SWR_REG_VAL_PACK(port->sinterval, |
| 960 | port->dev_id, 0x00, |
| 961 | SWRS_DP_SAMPLE_CONTROL_1_BANK(port_type, bank)); |
| 962 | |
| 963 | reg[len] = SWRM_CMD_FIFO_WR_CMD; |
| 964 | val[len++] = SWR_REG_VAL_PACK(port->offset1, |
| 965 | port->dev_id, 0x00, |
| 966 | SWRS_DP_OFFSET_CONTROL_1_BANK(port_type, bank)); |
| 967 | |
| 968 | if (port_type != 0) { |
| 969 | reg[len] = SWRM_CMD_FIFO_WR_CMD; |
| 970 | val[len++] = SWR_REG_VAL_PACK(port->offset2, |
| 971 | port->dev_id, 0x00, |
| 972 | SWRS_DP_OFFSET_CONTROL_2_BANK(port_type, |
| 973 | bank)); |
| 974 | } |
| 975 | mport = list_next_entry(mport, list); |
| 976 | if (!mport) { |
| 977 | dev_err(swrm->dev, "%s: end of list\n", __func__); |
| 978 | break; |
| 979 | } |
| 980 | } |
| 981 | swrm->bulk_write(swrm->handle, reg, val, len); |
| 982 | } |
| 983 | |
| 984 | static int swrm_connect_port(struct swr_master *master, |
| 985 | struct swr_params *portinfo) |
| 986 | { |
| 987 | int i; |
| 988 | struct swr_port_info *port; |
| 989 | int ret = 0; |
| 990 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 991 | struct swrm_mports *mport; |
| 992 | struct list_head *ptr, *next; |
| 993 | |
| 994 | dev_dbg(&master->dev, "%s: enter\n", __func__); |
| 995 | if (!portinfo) |
| 996 | return -EINVAL; |
| 997 | |
| 998 | if (!swrm) { |
| 999 | dev_err(&master->dev, |
| 1000 | "%s: Invalid handle to swr controller\n", |
| 1001 | __func__); |
| 1002 | return -EINVAL; |
| 1003 | } |
| 1004 | |
| 1005 | mutex_lock(&swrm->mlock); |
| 1006 | if (!swrm_is_port_en(master)) |
| 1007 | pm_runtime_get_sync(&swrm->pdev->dev); |
| 1008 | |
| 1009 | for (i = 0; i < portinfo->num_port; i++) { |
| 1010 | mport = kzalloc(sizeof(struct swrm_mports), GFP_KERNEL); |
| 1011 | if (!mport) { |
| 1012 | ret = -ENOMEM; |
| 1013 | goto mem_fail; |
| 1014 | } |
| 1015 | ret = swrm_get_master_port(&mport->id, |
| 1016 | portinfo->port_id[i]); |
| 1017 | if (ret < 0) { |
| 1018 | dev_err(&master->dev, |
| 1019 | "%s: mstr portid for slv port %d not found\n", |
| 1020 | __func__, portinfo->port_id[i]); |
| 1021 | goto port_fail; |
| 1022 | } |
| 1023 | port = swrm_get_avail_port(master); |
| 1024 | if (!port) { |
| 1025 | dev_err(&master->dev, |
| 1026 | "%s: avail ports not found!\n", __func__); |
| 1027 | goto port_fail; |
| 1028 | } |
| 1029 | list_add(&mport->list, &swrm->mport_list); |
| 1030 | port->dev_id = portinfo->dev_id; |
| 1031 | port->port_id = portinfo->port_id[i]; |
| 1032 | port->num_ch = portinfo->num_ch[i]; |
| 1033 | port->ch_rate = portinfo->ch_rate[i]; |
| 1034 | port->ch_en = portinfo->ch_en[i]; |
| 1035 | port->port_en = true; |
| 1036 | dev_dbg(&master->dev, |
| 1037 | "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n", |
| 1038 | __func__, mport->id, port->port_id, port->ch_rate, |
| 1039 | port->num_ch); |
| 1040 | } |
| 1041 | master->num_port += portinfo->num_port; |
| 1042 | if (master->num_port >= SWR_MSTR_PORT_LEN) |
| 1043 | master->num_port = SWR_MSTR_PORT_LEN; |
| 1044 | |
| 1045 | swrm_get_port_config(master); |
| 1046 | swr_port_response(master, portinfo->tid); |
| 1047 | swrm->num_cfg_devs += 1; |
| 1048 | dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d\n", |
| 1049 | __func__, swrm->num_cfg_devs, swrm->num_rx_chs); |
| 1050 | if (swrm->num_rx_chs > 1) { |
| 1051 | if (swrm->num_rx_chs == swrm->num_cfg_devs) |
| 1052 | swrm_apply_port_config(master); |
| 1053 | } else { |
| 1054 | swrm_apply_port_config(master); |
| 1055 | } |
| 1056 | mutex_unlock(&swrm->mlock); |
| 1057 | return 0; |
| 1058 | |
| 1059 | port_fail: |
| 1060 | kfree(mport); |
| 1061 | mem_fail: |
| 1062 | list_for_each_safe(ptr, next, &swrm->mport_list) { |
| 1063 | mport = list_entry(ptr, struct swrm_mports, list); |
| 1064 | for (i = 0; i < portinfo->num_port; i++) { |
| 1065 | if (portinfo->port_id[i] == mstr_ports[mport->id]) { |
| 1066 | port = swrm_get_port(master, |
| 1067 | portinfo->port_id[i]); |
| 1068 | if (port) |
| 1069 | port->ch_en = false; |
| 1070 | list_del(&mport->list); |
| 1071 | kfree(mport); |
| 1072 | break; |
| 1073 | } |
| 1074 | } |
| 1075 | } |
| 1076 | mutex_unlock(&swrm->mlock); |
| 1077 | return ret; |
| 1078 | } |
| 1079 | |
| 1080 | static int swrm_disconnect_port(struct swr_master *master, |
| 1081 | struct swr_params *portinfo) |
| 1082 | { |
| 1083 | int i; |
| 1084 | struct swr_port_info *port; |
| 1085 | u8 bank; |
| 1086 | u32 value; |
| 1087 | int ret = 0; |
| 1088 | u8 mport_id = 0; |
| 1089 | int port_type = 0; |
| 1090 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master); |
| 1091 | |
| 1092 | if (!swrm) { |
| 1093 | dev_err(&master->dev, |
| 1094 | "%s: Invalid handle to swr controller\n", |
| 1095 | __func__); |
| 1096 | return -EINVAL; |
| 1097 | } |
| 1098 | |
| 1099 | if (!portinfo) { |
| 1100 | dev_err(&master->dev, "%s: portinfo is NULL\n", __func__); |
| 1101 | return -EINVAL; |
| 1102 | } |
| 1103 | mutex_lock(&swrm->mlock); |
| 1104 | bank = get_inactive_bank_num(swrm); |
| 1105 | for (i = 0; i < portinfo->num_port; i++) { |
| 1106 | ret = swrm_get_master_port(&mport_id, |
| 1107 | portinfo->port_id[i]); |
| 1108 | if (ret < 0) { |
| 1109 | dev_err(&master->dev, |
| 1110 | "%s: mstr portid for slv port %d not found\n", |
| 1111 | __func__, portinfo->port_id[i]); |
| 1112 | mutex_unlock(&swrm->mlock); |
| 1113 | return -EINVAL; |
| 1114 | } |
| 1115 | port = swrm_get_enabled_port(master, portinfo->port_id[i]); |
| 1116 | if (!port) { |
| 1117 | dev_dbg(&master->dev, "%s: port %d already disabled\n", |
| 1118 | __func__, portinfo->port_id[i]); |
| 1119 | continue; |
| 1120 | } |
| 1121 | port_type = mstr_port_type[mport_id]; |
| 1122 | port->dev_id = portinfo->dev_id; |
| 1123 | port->port_en = false; |
| 1124 | port->ch_en = 0; |
| 1125 | value = port->ch_en << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT; |
| 1126 | value |= (port->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT); |
| 1127 | value |= (port->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT); |
| 1128 | value |= port->sinterval; |
| 1129 | |
| 1130 | |
| 1131 | swrm->write(swrm->handle, |
| 1132 | SWRM_DP_PORT_CTRL_BANK((mport_id+1), bank), |
| 1133 | value); |
| 1134 | swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00, |
| 1135 | SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank)); |
| 1136 | } |
| 1137 | |
| 1138 | swr_port_response(master, portinfo->tid); |
| 1139 | swrm->num_cfg_devs -= 1; |
| 1140 | dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d, active ports: %d\n", |
| 1141 | __func__, swrm->num_cfg_devs, swrm->num_rx_chs, |
| 1142 | master->num_port); |
| 1143 | mutex_unlock(&swrm->mlock); |
| 1144 | |
| 1145 | return 0; |
| 1146 | } |
| 1147 | |
| 1148 | static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm, |
| 1149 | int status, u8 *devnum) |
| 1150 | { |
| 1151 | int i; |
| 1152 | int new_sts = status; |
| 1153 | int ret = SWR_NOT_PRESENT; |
| 1154 | |
| 1155 | if (status != swrm->slave_status) { |
| 1156 | for (i = 0; i < (swrm->master.num_dev + 1); i++) { |
| 1157 | if ((status & SWRM_MCP_SLV_STATUS_MASK) != |
| 1158 | (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) { |
| 1159 | ret = (status & SWRM_MCP_SLV_STATUS_MASK); |
| 1160 | *devnum = i; |
| 1161 | break; |
| 1162 | } |
| 1163 | status >>= 2; |
| 1164 | swrm->slave_status >>= 2; |
| 1165 | } |
| 1166 | swrm->slave_status = new_sts; |
| 1167 | } |
| 1168 | return ret; |
| 1169 | } |
| 1170 | |
| 1171 | static irqreturn_t swr_mstr_interrupt(int irq, void *dev) |
| 1172 | { |
| 1173 | struct swr_mstr_ctrl *swrm = dev; |
| 1174 | u32 value, intr_sts; |
| 1175 | int status, chg_sts, i; |
| 1176 | u8 devnum = 0; |
| 1177 | int ret = IRQ_HANDLED; |
| 1178 | |
Laxminath Kasam | 8f7ccc2 | 2017-08-28 17:35:04 +0530 | [diff] [blame] | 1179 | mutex_lock(&swrm->reslock); |
| 1180 | swrm_clk_request(swrm, true); |
| 1181 | mutex_unlock(&swrm->reslock); |
| 1182 | |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1183 | intr_sts = swrm->read(swrm->handle, SWRM_INTERRUPT_STATUS); |
| 1184 | intr_sts &= SWRM_INTERRUPT_STATUS_RMSK; |
| 1185 | for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { |
| 1186 | value = intr_sts & (1 << i); |
| 1187 | if (!value) |
| 1188 | continue; |
| 1189 | |
| 1190 | swrm->write(swrm->handle, SWRM_INTERRUPT_CLEAR, value); |
| 1191 | switch (value) { |
| 1192 | case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: |
| 1193 | dev_dbg(swrm->dev, "SWR slave pend irq\n"); |
| 1194 | break; |
| 1195 | case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: |
| 1196 | dev_dbg(swrm->dev, "SWR new slave attached\n"); |
| 1197 | break; |
| 1198 | case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: |
| 1199 | status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS); |
| 1200 | if (status == swrm->slave_status) { |
| 1201 | dev_dbg(swrm->dev, |
| 1202 | "%s: No change in slave status: %d\n", |
| 1203 | __func__, status); |
| 1204 | break; |
| 1205 | } |
| 1206 | chg_sts = swrm_check_slave_change_status(swrm, status, |
| 1207 | &devnum); |
| 1208 | switch (chg_sts) { |
| 1209 | case SWR_NOT_PRESENT: |
| 1210 | dev_dbg(swrm->dev, "device %d got detached\n", |
| 1211 | devnum); |
| 1212 | break; |
| 1213 | case SWR_ATTACHED_OK: |
| 1214 | dev_dbg(swrm->dev, "device %d got attached\n", |
| 1215 | devnum); |
| 1216 | break; |
| 1217 | case SWR_ALERT: |
| 1218 | dev_dbg(swrm->dev, |
| 1219 | "device %d has pending interrupt\n", |
| 1220 | devnum); |
| 1221 | break; |
| 1222 | } |
| 1223 | break; |
| 1224 | case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: |
| 1225 | dev_err_ratelimited(swrm->dev, "SWR bus clash detected\n"); |
| 1226 | break; |
| 1227 | case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: |
| 1228 | dev_dbg(swrm->dev, "SWR read FIFO overflow\n"); |
| 1229 | break; |
| 1230 | case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: |
| 1231 | dev_dbg(swrm->dev, "SWR read FIFO underflow\n"); |
| 1232 | break; |
| 1233 | case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: |
| 1234 | dev_dbg(swrm->dev, "SWR write FIFO overflow\n"); |
| 1235 | break; |
| 1236 | case SWRM_INTERRUPT_STATUS_CMD_ERROR: |
| 1237 | value = swrm->read(swrm->handle, SWRM_CMD_FIFO_STATUS); |
| 1238 | dev_err_ratelimited(swrm->dev, |
| 1239 | "SWR CMD error, fifo status 0x%x, flushing fifo\n", |
| 1240 | value); |
| 1241 | swrm->write(swrm->handle, SWRM_CMD_FIFO_CMD, 0x1); |
| 1242 | break; |
| 1243 | case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: |
| 1244 | dev_dbg(swrm->dev, "SWR Port collision detected\n"); |
| 1245 | break; |
| 1246 | case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: |
| 1247 | dev_dbg(swrm->dev, "SWR read enable valid mismatch\n"); |
| 1248 | break; |
| 1249 | case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: |
| 1250 | complete(&swrm->broadcast); |
| 1251 | dev_dbg(swrm->dev, "SWR cmd id finished\n"); |
| 1252 | break; |
| 1253 | case SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED: |
| 1254 | break; |
| 1255 | case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED: |
| 1256 | break; |
| 1257 | case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL: |
| 1258 | break; |
| 1259 | case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED: |
| 1260 | complete(&swrm->reset); |
| 1261 | break; |
| 1262 | case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED: |
| 1263 | break; |
| 1264 | default: |
| 1265 | dev_err_ratelimited(swrm->dev, "SWR unknown interrupt\n"); |
| 1266 | ret = IRQ_NONE; |
| 1267 | break; |
| 1268 | } |
| 1269 | } |
Laxminath Kasam | 8f7ccc2 | 2017-08-28 17:35:04 +0530 | [diff] [blame] | 1270 | |
| 1271 | mutex_lock(&swrm->reslock); |
| 1272 | swrm_clk_request(swrm, false); |
| 1273 | mutex_unlock(&swrm->reslock); |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1274 | return ret; |
| 1275 | } |
| 1276 | |
| 1277 | static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum) |
| 1278 | { |
| 1279 | u32 val; |
| 1280 | |
| 1281 | swrm->slave_status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS); |
| 1282 | val = (swrm->slave_status >> (devnum * 2)); |
| 1283 | val &= SWRM_MCP_SLV_STATUS_MASK; |
| 1284 | return val; |
| 1285 | } |
| 1286 | |
| 1287 | static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id, |
| 1288 | u8 *dev_num) |
| 1289 | { |
| 1290 | int i; |
| 1291 | u64 id = 0; |
| 1292 | int ret = -EINVAL; |
| 1293 | struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr); |
Vidyakumar Athota | 462a0ec | 2018-01-22 15:44:58 -0800 | [diff] [blame] | 1294 | struct swr_device *swr_dev; |
Laxminath Kasam | f1d45c6 | 2018-02-26 20:31:02 +0530 | [diff] [blame] | 1295 | u32 num_dev = 0; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1296 | |
| 1297 | if (!swrm) { |
| 1298 | pr_err("%s: Invalid handle to swr controller\n", |
| 1299 | __func__); |
| 1300 | return ret; |
| 1301 | } |
Laxminath Kasam | f1d45c6 | 2018-02-26 20:31:02 +0530 | [diff] [blame] | 1302 | if (swrm->num_dev) |
| 1303 | num_dev = swrm->num_dev; |
| 1304 | else |
| 1305 | num_dev = mstr->num_dev; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1306 | |
| 1307 | pm_runtime_get_sync(&swrm->pdev->dev); |
Laxminath Kasam | f1d45c6 | 2018-02-26 20:31:02 +0530 | [diff] [blame] | 1308 | for (i = 1; i < (num_dev + 1); i++) { |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1309 | id = ((u64)(swrm->read(swrm->handle, |
| 1310 | SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32); |
| 1311 | id |= swrm->read(swrm->handle, |
| 1312 | SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i)); |
Vidyakumar Athota | 462a0ec | 2018-01-22 15:44:58 -0800 | [diff] [blame] | 1313 | /* |
| 1314 | * As pm_runtime_get_sync() brings all slaves out of reset |
| 1315 | * update logical device number for all slaves. |
| 1316 | */ |
| 1317 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) { |
| 1318 | if (swr_dev->addr == (id & SWR_DEV_ID_MASK)) { |
| 1319 | u32 status = swrm_get_device_status(swrm, i); |
| 1320 | |
| 1321 | if ((status == 0x01) || (status == 0x02)) { |
| 1322 | swr_dev->dev_num = i; |
| 1323 | if ((id & SWR_DEV_ID_MASK) == dev_id) { |
| 1324 | *dev_num = i; |
| 1325 | ret = 0; |
| 1326 | } |
| 1327 | dev_dbg(swrm->dev, "%s: devnum %d is assigned for dev addr %lx\n", |
| 1328 | __func__, i, swr_dev->addr); |
| 1329 | } |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1330 | } |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1331 | } |
| 1332 | } |
Vidyakumar Athota | 462a0ec | 2018-01-22 15:44:58 -0800 | [diff] [blame] | 1333 | if (ret) |
| 1334 | dev_err(swrm->dev, "%s: device 0x%llx is not ready\n", |
| 1335 | __func__, dev_id); |
| 1336 | |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1337 | pm_runtime_mark_last_busy(&swrm->pdev->dev); |
| 1338 | pm_runtime_put_autosuspend(&swrm->pdev->dev); |
| 1339 | return ret; |
| 1340 | } |
| 1341 | static int swrm_master_init(struct swr_mstr_ctrl *swrm) |
| 1342 | { |
| 1343 | int ret = 0; |
| 1344 | u32 val; |
| 1345 | u8 row_ctrl = SWR_MAX_ROW; |
| 1346 | u8 col_ctrl = SWR_MIN_COL; |
| 1347 | u8 ssp_period = 1; |
| 1348 | u8 retry_cmd_num = 3; |
| 1349 | u32 reg[SWRM_MAX_INIT_REG]; |
| 1350 | u32 value[SWRM_MAX_INIT_REG]; |
| 1351 | int len = 0; |
| 1352 | |
| 1353 | /* Clear Rows and Cols */ |
| 1354 | val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) | |
| 1355 | (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) | |
| 1356 | (ssp_period << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT)); |
| 1357 | |
| 1358 | reg[len] = SWRM_MCP_FRAME_CTRL_BANK_ADDR(0); |
| 1359 | value[len++] = val; |
| 1360 | |
| 1361 | /* Set Auto enumeration flag */ |
| 1362 | reg[len] = SWRM_ENUMERATOR_CFG_ADDR; |
| 1363 | value[len++] = 1; |
| 1364 | |
| 1365 | /* Mask soundwire interrupts */ |
| 1366 | reg[len] = SWRM_INTERRUPT_MASK_ADDR; |
| 1367 | value[len++] = 0x1FFFD; |
| 1368 | |
| 1369 | /* Configure No pings */ |
| 1370 | val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR); |
| 1371 | val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK; |
| 1372 | val |= (0x1f << SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT); |
| 1373 | reg[len] = SWRM_MCP_CFG_ADDR; |
| 1374 | value[len++] = val; |
| 1375 | |
| 1376 | /* Configure number of retries of a read/write cmd */ |
| 1377 | val = (retry_cmd_num << SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT); |
| 1378 | reg[len] = SWRM_CMD_FIFO_CFG_ADDR; |
| 1379 | value[len++] = val; |
| 1380 | |
| 1381 | /* Set IRQ to PULSE */ |
| 1382 | reg[len] = SWRM_COMP_CFG_ADDR; |
| 1383 | value[len++] = 0x02; |
| 1384 | |
| 1385 | reg[len] = SWRM_COMP_CFG_ADDR; |
| 1386 | value[len++] = 0x03; |
| 1387 | |
| 1388 | reg[len] = SWRM_INTERRUPT_CLEAR; |
| 1389 | value[len++] = 0x08; |
| 1390 | |
| 1391 | swrm->bulk_write(swrm->handle, reg, value, len); |
| 1392 | |
| 1393 | return ret; |
| 1394 | } |
| 1395 | |
| 1396 | static int swrm_probe(struct platform_device *pdev) |
| 1397 | { |
| 1398 | struct swr_mstr_ctrl *swrm; |
| 1399 | struct swr_ctrl_platform_data *pdata; |
| 1400 | int ret; |
| 1401 | |
| 1402 | /* Allocate soundwire master driver structure */ |
| 1403 | swrm = kzalloc(sizeof(struct swr_mstr_ctrl), GFP_KERNEL); |
| 1404 | if (!swrm) { |
| 1405 | ret = -ENOMEM; |
| 1406 | goto err_memory_fail; |
| 1407 | } |
| 1408 | swrm->dev = &pdev->dev; |
| 1409 | swrm->pdev = pdev; |
| 1410 | platform_set_drvdata(pdev, swrm); |
| 1411 | swr_set_ctrl_data(&swrm->master, swrm); |
| 1412 | pdata = dev_get_platdata(&pdev->dev); |
| 1413 | if (!pdata) { |
| 1414 | dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", |
| 1415 | __func__); |
| 1416 | ret = -EINVAL; |
| 1417 | goto err_pdata_fail; |
| 1418 | } |
| 1419 | swrm->handle = (void *)pdata->handle; |
| 1420 | if (!swrm->handle) { |
| 1421 | dev_err(&pdev->dev, "%s: swrm->handle is NULL\n", |
| 1422 | __func__); |
| 1423 | ret = -EINVAL; |
| 1424 | goto err_pdata_fail; |
| 1425 | } |
| 1426 | swrm->read = pdata->read; |
| 1427 | if (!swrm->read) { |
| 1428 | dev_err(&pdev->dev, "%s: swrm->read is NULL\n", |
| 1429 | __func__); |
| 1430 | ret = -EINVAL; |
| 1431 | goto err_pdata_fail; |
| 1432 | } |
| 1433 | swrm->write = pdata->write; |
| 1434 | if (!swrm->write) { |
| 1435 | dev_err(&pdev->dev, "%s: swrm->write is NULL\n", |
| 1436 | __func__); |
| 1437 | ret = -EINVAL; |
| 1438 | goto err_pdata_fail; |
| 1439 | } |
| 1440 | swrm->bulk_write = pdata->bulk_write; |
| 1441 | if (!swrm->bulk_write) { |
| 1442 | dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n", |
| 1443 | __func__); |
| 1444 | ret = -EINVAL; |
| 1445 | goto err_pdata_fail; |
| 1446 | } |
| 1447 | swrm->clk = pdata->clk; |
| 1448 | if (!swrm->clk) { |
| 1449 | dev_err(&pdev->dev, "%s: swrm->clk is NULL\n", |
| 1450 | __func__); |
| 1451 | ret = -EINVAL; |
| 1452 | goto err_pdata_fail; |
| 1453 | } |
| 1454 | swrm->reg_irq = pdata->reg_irq; |
| 1455 | if (!swrm->reg_irq) { |
| 1456 | dev_err(&pdev->dev, "%s: swrm->reg_irq is NULL\n", |
| 1457 | __func__); |
| 1458 | ret = -EINVAL; |
| 1459 | goto err_pdata_fail; |
| 1460 | } |
| 1461 | swrm->master.read = swrm_read; |
| 1462 | swrm->master.write = swrm_write; |
| 1463 | swrm->master.bulk_write = swrm_bulk_write; |
| 1464 | swrm->master.get_logical_dev_num = swrm_get_logical_dev_num; |
| 1465 | swrm->master.connect_port = swrm_connect_port; |
| 1466 | swrm->master.disconnect_port = swrm_disconnect_port; |
| 1467 | swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control; |
| 1468 | swrm->master.remove_from_group = swrm_remove_from_group; |
| 1469 | swrm->master.dev.parent = &pdev->dev; |
| 1470 | swrm->master.dev.of_node = pdev->dev.of_node; |
| 1471 | swrm->master.num_port = 0; |
| 1472 | swrm->num_enum_slaves = 0; |
| 1473 | swrm->rcmd_id = 0; |
| 1474 | swrm->wcmd_id = 0; |
| 1475 | swrm->slave_status = 0; |
| 1476 | swrm->num_rx_chs = 0; |
Laxminath Kasam | 8f7ccc2 | 2017-08-28 17:35:04 +0530 | [diff] [blame] | 1477 | swrm->clk_ref_count = 0; |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1478 | swrm->state = SWR_MSTR_RESUME; |
| 1479 | init_completion(&swrm->reset); |
| 1480 | init_completion(&swrm->broadcast); |
| 1481 | mutex_init(&swrm->mlock); |
| 1482 | INIT_LIST_HEAD(&swrm->mport_list); |
| 1483 | mutex_init(&swrm->reslock); |
| 1484 | |
Laxminath Kasam | f1d45c6 | 2018-02-26 20:31:02 +0530 | [diff] [blame] | 1485 | ret = of_property_read_u32(swrm->dev->of_node, "qcom,swr-num-dev", |
| 1486 | &swrm->num_dev); |
| 1487 | if (ret) |
| 1488 | dev_dbg(&pdev->dev, "%s: Looking up %s property failed\n", |
| 1489 | __func__, "qcom,swr-num-dev"); |
| 1490 | else { |
| 1491 | if (swrm->num_dev > SWR_MAX_SLAVE_DEVICES) { |
| 1492 | dev_err(&pdev->dev, "%s: num_dev %d > max limit %d\n", |
| 1493 | __func__, swrm->num_dev, SWR_MAX_SLAVE_DEVICES); |
| 1494 | ret = -EINVAL; |
| 1495 | goto err_pdata_fail; |
| 1496 | } |
| 1497 | } |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1498 | ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm, |
| 1499 | SWR_IRQ_REGISTER); |
| 1500 | if (ret) { |
| 1501 | dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n", |
| 1502 | __func__, ret); |
| 1503 | goto err_irq_fail; |
| 1504 | } |
| 1505 | |
| 1506 | ret = swr_register_master(&swrm->master); |
| 1507 | if (ret) { |
| 1508 | dev_err(&pdev->dev, "%s: error adding swr master\n", __func__); |
| 1509 | goto err_mstr_fail; |
| 1510 | } |
| 1511 | |
| 1512 | /* Add devices registered with board-info as the |
| 1513 | * controller will be up now |
| 1514 | */ |
| 1515 | swr_master_add_boarddevices(&swrm->master); |
| 1516 | mutex_lock(&swrm->mlock); |
| 1517 | swrm_clk_request(swrm, true); |
| 1518 | ret = swrm_master_init(swrm); |
| 1519 | if (ret < 0) { |
| 1520 | dev_err(&pdev->dev, |
| 1521 | "%s: Error in master Initializaiton, err %d\n", |
| 1522 | __func__, ret); |
| 1523 | mutex_unlock(&swrm->mlock); |
| 1524 | goto err_mstr_fail; |
| 1525 | } |
| 1526 | swrm->version = swrm->read(swrm->handle, SWRM_COMP_HW_VERSION); |
| 1527 | |
| 1528 | mutex_unlock(&swrm->mlock); |
| 1529 | |
| 1530 | if (pdev->dev.of_node) |
| 1531 | of_register_swr_devices(&swrm->master); |
| 1532 | |
| 1533 | dbgswrm = swrm; |
| 1534 | debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0); |
| 1535 | if (!IS_ERR(debugfs_swrm_dent)) { |
| 1536 | debugfs_peek = debugfs_create_file("swrm_peek", |
| 1537 | S_IFREG | 0444, debugfs_swrm_dent, |
| 1538 | (void *) "swrm_peek", &swrm_debug_ops); |
| 1539 | |
| 1540 | debugfs_poke = debugfs_create_file("swrm_poke", |
| 1541 | S_IFREG | 0444, debugfs_swrm_dent, |
| 1542 | (void *) "swrm_poke", &swrm_debug_ops); |
| 1543 | |
| 1544 | debugfs_reg_dump = debugfs_create_file("swrm_reg_dump", |
| 1545 | S_IFREG | 0444, debugfs_swrm_dent, |
| 1546 | (void *) "swrm_reg_dump", |
| 1547 | &swrm_debug_ops); |
| 1548 | } |
| 1549 | pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer); |
| 1550 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1551 | pm_runtime_set_active(&pdev->dev); |
| 1552 | pm_runtime_enable(&pdev->dev); |
| 1553 | pm_runtime_mark_last_busy(&pdev->dev); |
| 1554 | |
| 1555 | return 0; |
| 1556 | err_mstr_fail: |
| 1557 | swrm->reg_irq(swrm->handle, swr_mstr_interrupt, |
| 1558 | swrm, SWR_IRQ_FREE); |
| 1559 | err_irq_fail: |
| 1560 | err_pdata_fail: |
| 1561 | kfree(swrm); |
| 1562 | err_memory_fail: |
| 1563 | return ret; |
| 1564 | } |
| 1565 | |
| 1566 | static int swrm_remove(struct platform_device *pdev) |
| 1567 | { |
| 1568 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1569 | |
Laxminath Kasam | 468ece3 | 2017-11-28 12:40:22 +0530 | [diff] [blame] | 1570 | if (swrm->reg_irq) |
| 1571 | swrm->reg_irq(swrm->handle, swr_mstr_interrupt, |
| 1572 | swrm, SWR_IRQ_FREE); |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1573 | if (swrm->mstr_port) { |
| 1574 | kfree(swrm->mstr_port->port); |
| 1575 | swrm->mstr_port->port = NULL; |
| 1576 | kfree(swrm->mstr_port); |
| 1577 | swrm->mstr_port = NULL; |
| 1578 | } |
| 1579 | pm_runtime_disable(&pdev->dev); |
| 1580 | pm_runtime_set_suspended(&pdev->dev); |
| 1581 | swr_unregister_master(&swrm->master); |
| 1582 | mutex_destroy(&swrm->mlock); |
| 1583 | mutex_destroy(&swrm->reslock); |
| 1584 | kfree(swrm); |
| 1585 | return 0; |
| 1586 | } |
| 1587 | |
| 1588 | static int swrm_clk_pause(struct swr_mstr_ctrl *swrm) |
| 1589 | { |
| 1590 | u32 val; |
| 1591 | |
| 1592 | dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state); |
| 1593 | swrm->write(swrm->handle, SWRM_INTERRUPT_MASK_ADDR, 0x1FDFD); |
| 1594 | val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR); |
| 1595 | val |= SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK; |
| 1596 | swrm->write(swrm->handle, SWRM_MCP_CFG_ADDR, val); |
| 1597 | swrm->state = SWR_MSTR_PAUSE; |
| 1598 | |
| 1599 | return 0; |
| 1600 | } |
| 1601 | |
| 1602 | #ifdef CONFIG_PM |
| 1603 | static int swrm_runtime_resume(struct device *dev) |
| 1604 | { |
| 1605 | struct platform_device *pdev = to_platform_device(dev); |
| 1606 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1607 | int ret = 0; |
| 1608 | struct swr_master *mstr = &swrm->master; |
| 1609 | struct swr_device *swr_dev; |
| 1610 | |
| 1611 | dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n", |
| 1612 | __func__, swrm->state); |
| 1613 | mutex_lock(&swrm->reslock); |
| 1614 | if ((swrm->state == SWR_MSTR_PAUSE) || |
| 1615 | (swrm->state == SWR_MSTR_DOWN)) { |
| 1616 | if (swrm->state == SWR_MSTR_DOWN) { |
| 1617 | if (swrm_clk_request(swrm, true)) |
| 1618 | goto exit; |
| 1619 | } |
| 1620 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) { |
| 1621 | ret = swr_device_up(swr_dev); |
| 1622 | if (ret) { |
| 1623 | dev_err(dev, |
| 1624 | "%s: failed to wakeup swr dev %d\n", |
| 1625 | __func__, swr_dev->dev_num); |
| 1626 | swrm_clk_request(swrm, false); |
| 1627 | goto exit; |
| 1628 | } |
| 1629 | } |
| 1630 | swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01); |
| 1631 | swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01); |
| 1632 | swrm_master_init(swrm); |
| 1633 | } |
| 1634 | exit: |
| 1635 | pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer); |
| 1636 | mutex_unlock(&swrm->reslock); |
| 1637 | return ret; |
| 1638 | } |
| 1639 | |
| 1640 | static int swrm_runtime_suspend(struct device *dev) |
| 1641 | { |
| 1642 | struct platform_device *pdev = to_platform_device(dev); |
| 1643 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1644 | int ret = 0; |
| 1645 | struct swr_master *mstr = &swrm->master; |
| 1646 | struct swr_device *swr_dev; |
| 1647 | |
| 1648 | dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n", |
| 1649 | __func__, swrm->state); |
| 1650 | mutex_lock(&swrm->reslock); |
| 1651 | if ((swrm->state == SWR_MSTR_RESUME) || |
| 1652 | (swrm->state == SWR_MSTR_UP)) { |
| 1653 | if (swrm_is_port_en(&swrm->master)) { |
| 1654 | dev_dbg(dev, "%s ports are enabled\n", __func__); |
| 1655 | ret = -EBUSY; |
| 1656 | goto exit; |
| 1657 | } |
| 1658 | swrm_clk_pause(swrm); |
| 1659 | swrm->write(swrm->handle, SWRM_COMP_CFG_ADDR, 0x00); |
| 1660 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) { |
| 1661 | ret = swr_device_down(swr_dev); |
| 1662 | if (ret) { |
| 1663 | dev_err(dev, |
| 1664 | "%s: failed to shutdown swr dev %d\n", |
| 1665 | __func__, swr_dev->dev_num); |
| 1666 | goto exit; |
| 1667 | } |
| 1668 | } |
| 1669 | swrm_clk_request(swrm, false); |
| 1670 | } |
| 1671 | exit: |
| 1672 | mutex_unlock(&swrm->reslock); |
| 1673 | return ret; |
| 1674 | } |
| 1675 | #endif /* CONFIG_PM */ |
| 1676 | |
| 1677 | static int swrm_device_down(struct device *dev) |
| 1678 | { |
| 1679 | struct platform_device *pdev = to_platform_device(dev); |
| 1680 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1681 | int ret = 0; |
| 1682 | struct swr_master *mstr = &swrm->master; |
| 1683 | struct swr_device *swr_dev; |
| 1684 | |
| 1685 | dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state); |
| 1686 | mutex_lock(&swrm->reslock); |
| 1687 | if ((swrm->state == SWR_MSTR_RESUME) || |
| 1688 | (swrm->state == SWR_MSTR_UP)) { |
| 1689 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) { |
| 1690 | ret = swr_device_down(swr_dev); |
| 1691 | if (ret) |
| 1692 | dev_err(dev, |
| 1693 | "%s: failed to shutdown swr dev %d\n", |
| 1694 | __func__, swr_dev->dev_num); |
| 1695 | } |
| 1696 | dev_dbg(dev, "%s: Shutting down SWRM\n", __func__); |
| 1697 | pm_runtime_disable(dev); |
| 1698 | pm_runtime_set_suspended(dev); |
| 1699 | pm_runtime_enable(dev); |
| 1700 | swrm_clk_request(swrm, false); |
| 1701 | } |
| 1702 | mutex_unlock(&swrm->reslock); |
| 1703 | return ret; |
| 1704 | } |
| 1705 | |
| 1706 | /** |
| 1707 | * swrm_wcd_notify - parent device can notify to soundwire master through |
| 1708 | * this function |
| 1709 | * @pdev: pointer to platform device structure |
| 1710 | * @id: command id from parent to the soundwire master |
| 1711 | * @data: data from parent device to soundwire master |
| 1712 | */ |
| 1713 | int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data) |
| 1714 | { |
| 1715 | struct swr_mstr_ctrl *swrm; |
| 1716 | int ret = 0; |
| 1717 | struct swr_master *mstr; |
| 1718 | struct swr_device *swr_dev; |
| 1719 | |
| 1720 | if (!pdev) { |
| 1721 | pr_err("%s: pdev is NULL\n", __func__); |
| 1722 | return -EINVAL; |
| 1723 | } |
| 1724 | swrm = platform_get_drvdata(pdev); |
| 1725 | if (!swrm) { |
| 1726 | dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__); |
| 1727 | return -EINVAL; |
| 1728 | } |
| 1729 | mstr = &swrm->master; |
| 1730 | |
| 1731 | switch (id) { |
| 1732 | case SWR_CH_MAP: |
| 1733 | if (!data) { |
| 1734 | dev_err(swrm->dev, "%s: data is NULL\n", __func__); |
| 1735 | ret = -EINVAL; |
| 1736 | } else { |
| 1737 | ret = swrm_set_ch_map(swrm, data); |
| 1738 | } |
| 1739 | break; |
| 1740 | case SWR_DEVICE_DOWN: |
| 1741 | dev_dbg(swrm->dev, "%s: swr master down called\n", __func__); |
| 1742 | mutex_lock(&swrm->mlock); |
| 1743 | if ((swrm->state == SWR_MSTR_PAUSE) || |
| 1744 | (swrm->state == SWR_MSTR_DOWN)) |
| 1745 | dev_dbg(swrm->dev, "%s: SWR master is already Down: %d\n", |
| 1746 | __func__, swrm->state); |
| 1747 | else |
| 1748 | swrm_device_down(&pdev->dev); |
| 1749 | mutex_unlock(&swrm->mlock); |
| 1750 | break; |
| 1751 | case SWR_DEVICE_UP: |
| 1752 | dev_dbg(swrm->dev, "%s: swr master up called\n", __func__); |
| 1753 | mutex_lock(&swrm->mlock); |
| 1754 | mutex_lock(&swrm->reslock); |
| 1755 | if ((swrm->state == SWR_MSTR_RESUME) || |
| 1756 | (swrm->state == SWR_MSTR_UP)) { |
| 1757 | dev_dbg(swrm->dev, "%s: SWR master is already UP: %d\n", |
| 1758 | __func__, swrm->state); |
Laxminath Kasam | ac594bd | 2018-07-31 19:27:44 +0530 | [diff] [blame] | 1759 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) |
| 1760 | swr_reset_device(swr_dev); |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1761 | } else { |
| 1762 | pm_runtime_mark_last_busy(&pdev->dev); |
| 1763 | mutex_unlock(&swrm->reslock); |
| 1764 | pm_runtime_get_sync(&pdev->dev); |
| 1765 | mutex_lock(&swrm->reslock); |
| 1766 | list_for_each_entry(swr_dev, &mstr->devices, dev_list) { |
| 1767 | ret = swr_reset_device(swr_dev); |
| 1768 | if (ret) { |
| 1769 | dev_err(swrm->dev, |
| 1770 | "%s: failed to reset swr device %d\n", |
| 1771 | __func__, swr_dev->dev_num); |
| 1772 | swrm_clk_request(swrm, false); |
| 1773 | } |
| 1774 | } |
| 1775 | pm_runtime_mark_last_busy(&pdev->dev); |
| 1776 | pm_runtime_put_autosuspend(&pdev->dev); |
| 1777 | } |
| 1778 | mutex_unlock(&swrm->reslock); |
| 1779 | mutex_unlock(&swrm->mlock); |
| 1780 | break; |
| 1781 | case SWR_SET_NUM_RX_CH: |
| 1782 | if (!data) { |
| 1783 | dev_err(swrm->dev, "%s: data is NULL\n", __func__); |
| 1784 | ret = -EINVAL; |
| 1785 | } else { |
| 1786 | mutex_lock(&swrm->mlock); |
| 1787 | swrm->num_rx_chs = *(int *)data; |
| 1788 | if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) { |
| 1789 | list_for_each_entry(swr_dev, &mstr->devices, |
| 1790 | dev_list) { |
| 1791 | ret = swr_set_device_group(swr_dev, |
| 1792 | SWR_BROADCAST); |
| 1793 | if (ret) |
| 1794 | dev_err(swrm->dev, |
| 1795 | "%s: set num ch failed\n", |
| 1796 | __func__); |
| 1797 | } |
| 1798 | } else { |
| 1799 | list_for_each_entry(swr_dev, &mstr->devices, |
| 1800 | dev_list) { |
| 1801 | ret = swr_set_device_group(swr_dev, |
| 1802 | SWR_GROUP_NONE); |
| 1803 | if (ret) |
| 1804 | dev_err(swrm->dev, |
| 1805 | "%s: set num ch failed\n", |
| 1806 | __func__); |
| 1807 | } |
| 1808 | } |
| 1809 | mutex_unlock(&swrm->mlock); |
| 1810 | } |
| 1811 | break; |
| 1812 | default: |
| 1813 | dev_err(swrm->dev, "%s: swr master unknown id %d\n", |
| 1814 | __func__, id); |
| 1815 | break; |
| 1816 | } |
| 1817 | return ret; |
| 1818 | } |
| 1819 | EXPORT_SYMBOL(swrm_wcd_notify); |
| 1820 | |
| 1821 | #ifdef CONFIG_PM_SLEEP |
| 1822 | static int swrm_suspend(struct device *dev) |
| 1823 | { |
| 1824 | int ret = -EBUSY; |
| 1825 | struct platform_device *pdev = to_platform_device(dev); |
| 1826 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1827 | |
| 1828 | dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state); |
| 1829 | if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { |
| 1830 | ret = swrm_runtime_suspend(dev); |
| 1831 | if (!ret) { |
| 1832 | /* |
| 1833 | * Synchronize runtime-pm and system-pm states: |
| 1834 | * At this point, we are already suspended. If |
| 1835 | * runtime-pm still thinks its active, then |
| 1836 | * make sure its status is in sync with HW |
| 1837 | * status. The three below calls let the |
| 1838 | * runtime-pm know that we are suspended |
| 1839 | * already without re-invoking the suspend |
| 1840 | * callback |
| 1841 | */ |
| 1842 | pm_runtime_disable(dev); |
| 1843 | pm_runtime_set_suspended(dev); |
| 1844 | pm_runtime_enable(dev); |
| 1845 | } |
| 1846 | } |
| 1847 | if (ret == -EBUSY) { |
| 1848 | /* |
| 1849 | * There is a possibility that some audio stream is active |
| 1850 | * during suspend. We dont want to return suspend failure in |
| 1851 | * that case so that display and relevant components can still |
| 1852 | * go to suspend. |
| 1853 | * If there is some other error, then it should be passed-on |
| 1854 | * to system level suspend |
| 1855 | */ |
| 1856 | ret = 0; |
| 1857 | } |
| 1858 | return ret; |
| 1859 | } |
| 1860 | |
| 1861 | static int swrm_resume(struct device *dev) |
| 1862 | { |
| 1863 | int ret = 0; |
| 1864 | struct platform_device *pdev = to_platform_device(dev); |
| 1865 | struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev); |
| 1866 | |
| 1867 | dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state); |
| 1868 | if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) { |
| 1869 | ret = swrm_runtime_resume(dev); |
| 1870 | if (!ret) { |
| 1871 | pm_runtime_mark_last_busy(dev); |
| 1872 | pm_request_autosuspend(dev); |
| 1873 | } |
| 1874 | } |
| 1875 | return ret; |
| 1876 | } |
| 1877 | #endif /* CONFIG_PM_SLEEP */ |
| 1878 | |
| 1879 | static const struct dev_pm_ops swrm_dev_pm_ops = { |
| 1880 | SET_SYSTEM_SLEEP_PM_OPS( |
| 1881 | swrm_suspend, |
| 1882 | swrm_resume |
| 1883 | ) |
| 1884 | SET_RUNTIME_PM_OPS( |
| 1885 | swrm_runtime_suspend, |
| 1886 | swrm_runtime_resume, |
| 1887 | NULL |
| 1888 | ) |
| 1889 | }; |
| 1890 | |
| 1891 | static const struct of_device_id swrm_dt_match[] = { |
| 1892 | { |
| 1893 | .compatible = "qcom,swr-wcd", |
| 1894 | }, |
| 1895 | {} |
| 1896 | }; |
| 1897 | |
| 1898 | static struct platform_driver swr_mstr_driver = { |
| 1899 | .probe = swrm_probe, |
| 1900 | .remove = swrm_remove, |
| 1901 | .driver = { |
| 1902 | .name = SWR_WCD_NAME, |
| 1903 | .owner = THIS_MODULE, |
| 1904 | .pm = &swrm_dev_pm_ops, |
| 1905 | .of_match_table = swrm_dt_match, |
| 1906 | }, |
| 1907 | }; |
| 1908 | |
| 1909 | static int __init swrm_init(void) |
| 1910 | { |
| 1911 | return platform_driver_register(&swr_mstr_driver); |
| 1912 | } |
Laxminath Kasam | 8b1366a | 2017-10-05 01:44:16 +0530 | [diff] [blame] | 1913 | module_init(swrm_init); |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1914 | |
| 1915 | static void __exit swrm_exit(void) |
| 1916 | { |
| 1917 | platform_driver_unregister(&swr_mstr_driver); |
| 1918 | } |
| 1919 | module_exit(swrm_exit); |
| 1920 | |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1921 | MODULE_LICENSE("GPL v2"); |
| 1922 | MODULE_DESCRIPTION("WCD SoundWire Controller"); |
| 1923 | MODULE_ALIAS("platform:swr-wcd"); |