wlan: False SSR and RIVA crash fix
If RX interrupt happens with host RX low buffer condition,
it's same with DXE RX channel disabled condition,
processed RX frame count set as '0'.
When RX buffer available signal schedule, if RX interrupt happen,
RX buffer avaliable process will be intercepted by interrupt.
And RX DXE will be enabled right before RX interrupt schedule by
RX buffer available process. In this case, previous frame count '0'
will be handled as empty interrupt and SSR will be issued.
To avoid this, RX DXE disabled interrupt should be marked as
non-empty interrupt.
Change-Id: I209797e0def40938dbcb764dec42c7274d2865db
CRs-fixed: 506731
diff --git a/CORE/DXE/src/wlan_qct_dxe.c b/CORE/DXE/src/wlan_qct_dxe.c
index a9ef977..983c3e7 100644
--- a/CORE/DXE/src/wlan_qct_dxe.c
+++ b/CORE/DXE/src/wlan_qct_dxe.c
@@ -2221,7 +2221,10 @@
HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_ERROR,
"dxeRXFrameReady %s RING Wrapped, RX Free Low 0x%x",
channelType[channelEntry->channelType], chStat);
- channelEntry->numFragmentCurrentChain = 0;
+ /* This is not empty interrupt case
+ * If handle this as empty interrupt, false SSR might be issued
+ * Frame count '1' is dummy frame count to avoid SSR */
+ channelEntry->numFragmentCurrentChain = 1;
return eWLAN_PAL_STATUS_SUCCESS;
}