wlan: Enable DXE Channel 7 for H2H transfer
DXE Channel 7 will be used by Firmware to send
logs to the host via H2H transfer. Apart from
sending the logs this channel will also be
used to send mailbox messages which will help
synchronizing the host and firmware operations
when transfering the logs.
CRs-Fixed: 848291
Change-Id: Ia6e2d789a4ccec9b993813dbef401e0fbe2aca8e
diff --git a/CORE/DXE/src/wlan_qct_dxe.c b/CORE/DXE/src/wlan_qct_dxe.c
index 1bcfaf5..90a259f 100644
--- a/CORE/DXE/src/wlan_qct_dxe.c
+++ b/CORE/DXE/src/wlan_qct_dxe.c
@@ -108,6 +108,7 @@
"TX_HIGH_PRI",
"RX_LOW_PRI",
"RX_HIGH_PRI",
+ "RX_LOGS",
"RX_FW_LOGS",
};
static wpt_packet *rx_reaped_buf[WLANDXE_MAX_REAPED_RX_FRAMES];
@@ -944,7 +945,7 @@
}
else
{
- /* Just in case. H2H Test RX channel, do nothing
+ /* Just in case. H2H RX channel, do nothing
* By Definition this must not happen */
}
@@ -1222,15 +1223,6 @@
else
{
/* H2H test channel, not use work Q */
- /* Program pre allocated destination Address */
- status = wpalWriteRegister(channelEntry->channelRegister.chDXEDadrlRegAddr,
- WLANDXE_U32_SWAP_ENDIAN(channelEntry->DescBottomLoc->dxedesc.dxe_short_desc.phyNextL));
- if(eWLAN_PAL_STATUS_SUCCESS != status)
- {
- HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_ERROR,
- "dxeChannelInitProgram Write RX DAddress register fail");
- return status;
- }
}
HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_INFO_LOW,
@@ -4045,19 +4037,21 @@
unsigned int idx;
WLANDXE_ChannelCBType *currentChannel = NULL;
int smsmInitState;
+ wpt_uint8 chanMask = WDTS_TRANSPORT_CHANNELS_MASK;
HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_INFO_LOW,
"%s Enter", __func__);
if (wpalIsFwLoggingEnabled())
{
- dxeSetEnabledChannels(WDTS_TRANSPORT_CHANNELS_MASK |
- WDTS_RX_LOG_CHANNEL_MASK);
+ chanMask |= WDTS_RX_LOG_CHANNEL_MASK;
}
- else
+
+ if (wpalIsFwEvLoggingEnabled())
{
- dxeSetEnabledChannels(WDTS_TRANSPORT_CHANNELS_MASK);
+ chanMask |= WDTS_RX_FW_LOG_CHANNEL_MASK;
}
+ dxeSetEnabledChannels(chanMask);
/* This is temporary allocation */
tempDxeCtrlBlk = (WLANDXE_CtrlBlkType *)wpalMemoryAllocate(sizeof(WLANDXE_CtrlBlkType));
@@ -4083,26 +4077,7 @@
HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_WARN,
"WLANDXE_Open Channel %s Open Start", channelType[idx]);
currentChannel = &tempDxeCtrlBlk->dxeChannel[idx];
- if(idx == WDTS_CHANNEL_TX_LOW_PRI)
- {
- currentChannel->channelType = WDTS_CHANNEL_TX_LOW_PRI;
- }
- else if(idx == WDTS_CHANNEL_TX_HIGH_PRI)
- {
- currentChannel->channelType = WDTS_CHANNEL_TX_HIGH_PRI;
- }
- else if(idx == WDTS_CHANNEL_RX_LOW_PRI)
- {
- currentChannel->channelType = WDTS_CHANNEL_RX_LOW_PRI;
- }
- else if(idx == WDTS_CHANNEL_RX_HIGH_PRI)
- {
- currentChannel->channelType = WDTS_CHANNEL_RX_HIGH_PRI;
- }
- else if(idx == WDTS_CHANNEL_RX_LOG)
- {
- currentChannel->channelType = WDTS_CHANNEL_RX_LOG;
- }
+ currentChannel->channelType = idx;
/* Config individual channels from channel default setup table */
status = dxeChannelDefaultConfig(tempDxeCtrlBlk,
diff --git a/CORE/DXE/src/wlan_qct_dxe_cfg_i.c b/CORE/DXE/src/wlan_qct_dxe_cfg_i.c
index 4a9ec3e..29317e8 100644
--- a/CORE/DXE/src/wlan_qct_dxe_cfg_i.c
+++ b/CORE/DXE/src/wlan_qct_dxe_cfg_i.c
@@ -81,7 +81,8 @@
WLANDXE_DMA_CHAN3_BASE_ADDRESS,
WLANDXE_DMA_CHAN4_BASE_ADDRESS,
WLANDXE_DMA_CHAN5_BASE_ADDRESS,
- WLANDXE_DMA_CHAN6_BASE_ADDRESS
+ WLANDXE_DMA_CHAN6_BASE_ADDRESS,
+ WLANDXE_DMA_CHAN7_BASE_ADDRESS
};
wpt_uint32 channelInterruptMask[WLANDXE_DMA_CHANNEL_MAX] =
@@ -92,7 +93,8 @@
WLANDXE_INT_MASK_CHAN_3,
WLANDXE_INT_MASK_CHAN_4,
WLANDXE_INT_MASK_CHAN_5,
- WLANDXE_INT_MASK_CHAN_6
+ WLANDXE_INT_MASK_CHAN_6,
+ WLANDXE_INT_MASK_CHAN_7
};
WLANDXE_ChannelConfigType chanTXLowPriConfig =
@@ -273,6 +275,45 @@
WLANDXE_DESC_CTRL_XTYPE_B2H,
/* Channel Priority 7(Highest) - 0(Lowest)*/
+ 1,
+
+ /* BD attached to frames for this pipe */
+ eWLAN_PAL_TRUE,
+
+ /* chk_size*/
+ 0,
+
+ /* bmuThdSel*/
+ 8,
+
+ /* Added in Gen5 for Prefetch*/
+ eWLAN_PAL_TRUE,
+
+ /* Use short Descriptor */
+ eWLAN_PAL_TRUE
+};
+
+WLANDXE_ChannelConfigType chanRXFWLogConfig =
+{
+ /* Q handle type, Circular */
+ WLANDXE_CHANNEL_HANDLE_CIRCULA,
+
+ /* Number of Descriptors*/
+ 32,
+
+ /* MAX num RX Buffer*/
+ 1,
+
+ /* Reference WQ - NA as channel used for H2H */
+ 0,
+
+ /* USB Only, End point info */
+ 0,
+
+ /* Transfer Type */
+ WLANDXE_DESC_CTRL_XTYPE_H2H,
+
+ /* Channel Priority 7(Highest) - 0(Lowest)*/
0,
/* BD attached to frames for this pipe */
@@ -298,6 +339,7 @@
{WDTS_CHANNEL_RX_LOW_PRI, WLANDXE_DMA_CHANNEL_1, &chanRXLowPriConfig},
{WDTS_CHANNEL_RX_HIGH_PRI, WLANDXE_DMA_CHANNEL_3, &chanRXHighPriConfig},
{WDTS_CHANNEL_RX_LOG, WLANDXE_DMA_CHANNEL_5, &chanRXLogConfig},
+ {WDTS_CHANNEL_RX_FW_LOG, WLANDXE_DMA_CHANNEL_7, &chanRXFWLogConfig},
};
WLANDXE_TxCompIntConfigType txCompInt =
@@ -518,11 +560,15 @@
}
else
{
- /* This is test H2H channel, TX, RX not use work Q
+ /* This is H2H channel, TX, RX not use work Q
* Do Nothing */
}
- /* Frame Contents Swap */
- channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_SWAP_MASK;
+
+ if (WDTS_CHANNEL_RX_FW_LOG != channelEntry->channelType)
+ {
+ /* Frame Contents Swap */
+ channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_SWAP_MASK;
+ }
/* Host System Using Little Endian */
channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_ENDIAN_MASK;
/* BMU Threshold select */
@@ -545,9 +591,14 @@
* DXE engine will reference this value before DMA transfer */
dxeControlRead = 0;
/* Source is a Queue ID, not flat memory address */
- dxeControlRead |= WLANDXE_DESC_CTRL_SIQ;
+ if (WDTS_CHANNEL_RX_FW_LOG != channelEntry->channelType)
+ dxeControlRead |= WLANDXE_DESC_CTRL_SIQ;
/* Transfer direction is BMU 2 Host */
- dxeControlRead |= WLANDXE_DESC_CTRL_XTYPE_B2H;
+ if (WDTS_CHANNEL_RX_FW_LOG != channelEntry->channelType)
+ dxeControlRead |= WLANDXE_DESC_CTRL_XTYPE_B2H;
+ else
+ dxeControlRead |= WLANDXE_DESC_CTRL_XTYPE_H2H;
+
/* End of Packet, RX is single fragment */
dxeControlRead |= WLANDXE_DESC_CTRL_EOP;
/* BD Present, default YES, B2H case it must be 0 to insert BD */
@@ -574,7 +625,8 @@
dxeControlRead |= WLANDXE_DESC_CTRL_BDT_SWAP;
/* Host Little Endian */
if((WDTS_CHANNEL_TX_LOW_PRI == channelEntry->channelType) ||
- (WDTS_CHANNEL_TX_HIGH_PRI == channelEntry->channelType))
+ (WDTS_CHANNEL_TX_HIGH_PRI == channelEntry->channelType) ||
+ (WDTS_CHANNEL_RX_FW_LOG == channelEntry->channelType))
{
dxeControlRead |= WLANDXE_DESC_CTRL_ENDIANNESS;
}
@@ -658,6 +710,10 @@
{
channelEntry->numDesc = mappedChannel->channelConfig->nDescs;
}
+ else if(WDTS_CHANNEL_RX_FW_LOG == channelEntry->channelType)
+ {
+ channelEntry->numDesc = mappedChannel->channelConfig->nDescs;
+ }
else
{
channelEntry->numDesc = rxResourceCount / 4;
diff --git a/CORE/DXE/src/wlan_qct_dxe_i.h b/CORE/DXE/src/wlan_qct_dxe_i.h
index dacc1e1..e6aa8b0 100644
--- a/CORE/DXE/src/wlan_qct_dxe_i.h
+++ b/CORE/DXE/src/wlan_qct_dxe_i.h
@@ -149,6 +149,7 @@
#define WLANDXE_DMA_CHAN4_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x500)
#define WLANDXE_DMA_CHAN5_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x540)
#define WLANDXE_DMA_CHAN6_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x580)
+#define WLANDXE_DMA_CHAN7_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x5c0)
/* Channel specific register offset */
#define WLANDXE_DMA_CH_CTRL_REG 0x0000
@@ -416,6 +417,7 @@
#define WLANDXE_INT_MASK_CHAN_4 0x00000010
#define WLANDXE_INT_MASK_CHAN_5 0x00000020
#define WLANDXE_INT_MASK_CHAN_6 0x00000040
+#define WLANDXE_INT_MASK_CHAN_7 0x00000080
#define WLANDXE_TX_LOW_RES_THRESHOLD (5)
@@ -499,6 +501,7 @@
WLANDXE_DMA_CHANNEL_4,
WLANDXE_DMA_CHANNEL_5,
WLANDXE_DMA_CHANNEL_6,
+ WLANDXE_DMA_CHANNEL_7,
WLANDXE_DMA_CHANNEL_MAX
} WLANDXE_DMAChannelType;
diff --git a/CORE/HDD/inc/wlan_hdd_main.h b/CORE/HDD/inc/wlan_hdd_main.h
index 8d18a9d..b6a8777 100644
--- a/CORE/HDD/inc/wlan_hdd_main.h
+++ b/CORE/HDD/inc/wlan_hdd_main.h
@@ -1638,4 +1638,5 @@
tANI_U8 dfsScanMode);
v_U8_t hdd_is_fw_logging_enabled(void);
+v_U8_t hdd_is_fw_ev_logging_enabled(void);
#endif // end #if !defined( WLAN_HDD_MAIN_H )
diff --git a/CORE/HDD/src/wlan_hdd_main.c b/CORE/HDD/src/wlan_hdd_main.c
index 187507e..0cb4e33 100755
--- a/CORE/HDD/src/wlan_hdd_main.c
+++ b/CORE/HDD/src/wlan_hdd_main.c
@@ -11272,6 +11272,18 @@
}
/*
+ * API to find if the firmware will send trace logs using DXE channel
+ */
+v_U8_t hdd_is_fw_ev_logging_enabled(void)
+{
+ hdd_context_t *pHddCtx;
+
+ pHddCtx = vos_get_context(VOS_MODULE_ID_HDD,
+ vos_get_global_context(VOS_MODULE_ID_HDD, NULL));
+
+ return (pHddCtx && pHddCtx->cfg_ini->enableFWLogging);
+}
+/*
* API to find if there is any session connected
*/
VOS_STATUS hdd_is_any_session_connected(hdd_context_t *pHddCtx)
diff --git a/CORE/VOSS/inc/vos_api.h b/CORE/VOSS/inc/vos_api.h
index 17f16e7..f0bf3d5 100644
--- a/CORE/VOSS/inc/vos_api.h
+++ b/CORE/VOSS/inc/vos_api.h
@@ -341,6 +341,7 @@
v_BOOL_t vos_get_dxeSSREnable(void);
v_U8_t vos_is_fw_logging_enabled(void);
+v_U8_t vos_is_fw_ev_logging_enabled(void);
v_U8_t vos_is_fw_logging_supported(void);
void vos_set_multicast_logging(uint8_t value);
diff --git a/CORE/VOSS/src/vos_api.c b/CORE/VOSS/src/vos_api.c
index 0b6fa85..c6f616d 100644
--- a/CORE/VOSS/src/vos_api.c
+++ b/CORE/VOSS/src/vos_api.c
@@ -2475,6 +2475,24 @@
/**---------------------------------------------------------------------------
+ \brief vos_is_fw_ev_logging_enabled() -
+
+ API to check if firmware is configured to send live logs using DXE channel
+
+ \param - None
+
+ \return - 0: firmware logging is not enabled (it may or may not
+ be supported)
+ 1: firmware logging is enabled
+
+ --------------------------------------------------------------------------*/
+v_U8_t vos_is_fw_ev_logging_enabled(void)
+{
+ return hdd_is_fw_ev_logging_enabled();
+}
+
+/**---------------------------------------------------------------------------
+
\brief vos_is_fw_logging_supported() -
API to check if firmware supports to send logs using DXE channel
diff --git a/CORE/WDI/TRP/DTS/inc/wlan_qct_wdi_dts.h b/CORE/WDI/TRP/DTS/inc/wlan_qct_wdi_dts.h
index 2f78ed1..0d1dfaf 100644
--- a/CORE/WDI/TRP/DTS/inc/wlan_qct_wdi_dts.h
+++ b/CORE/WDI/TRP/DTS/inc/wlan_qct_wdi_dts.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -73,6 +73,7 @@
WDTS_CHANNEL_RX_LOW_PRI,
WDTS_CHANNEL_RX_HIGH_PRI,
WDTS_CHANNEL_RX_LOG,
+ WDTS_CHANNEL_RX_FW_LOG,
WDTS_CHANNEL_MAX
} WDTS_ChannelType;
@@ -81,6 +82,7 @@
| 1<<WDTS_CHANNEL_RX_LOW_PRI | 1<<WDTS_CHANNEL_RX_HIGH_PRI)
#define WDTS_RX_LOG_CHANNEL_MASK (1<<WDTS_CHANNEL_RX_LOG)
+#define WDTS_RX_FW_LOG_CHANNEL_MASK (1<<WDTS_CHANNEL_RX_FW_LOG)
typedef enum
{
diff --git a/CORE/WDI/WPAL/inc/wlan_qct_pal_api.h b/CORE/WDI/WPAL/inc/wlan_qct_pal_api.h
index 6b3a24e..c1a8d18 100644
--- a/CORE/WDI/WPAL/inc/wlan_qct_pal_api.h
+++ b/CORE/WDI/WPAL/inc/wlan_qct_pal_api.h
@@ -388,4 +388,5 @@
wpt_uint8 wpalIsFwLoggingEnabled(void);
wpt_uint8 wpalIsFwLoggingSupported(void);
+wpt_uint8 wpalIsFwEvLoggingEnabled(void);
#endif // __WLAN_QCT_PAL_API_H
diff --git a/CORE/WDI/WPAL/src/wlan_qct_pal_api.c b/CORE/WDI/WPAL/src/wlan_qct_pal_api.c
index 361b0fb..9e0f047 100644
--- a/CORE/WDI/WPAL/src/wlan_qct_pal_api.c
+++ b/CORE/WDI/WPAL/src/wlan_qct_pal_api.c
@@ -443,6 +443,19 @@
}
/*---------------------------------------------------------------------------
+ wpalIsFwLoggingEnabled - Check if Firmware will send running
+ logs using DXE
+
+ Param:
+ None
+ Return:
+ Check the documentation of vos_is_fw_logging_enabled
+---------------------------------------------------------------------------*/
+wpt_uint8 wpalIsFwEvLoggingEnabled(void)
+{
+ return vos_is_fw_ev_logging_enabled();
+}
+/*---------------------------------------------------------------------------
wpalIsFwLoggingSupported - Check if Firmware supports the fw->host
logging infrastructure
This API can only be called after fw caps