qcacmn: regtable population of QCA8074
Added qca8074def.c that holds the register
table entries for qca8074.
Change-Id: I40b170722c2177cf5f53b5728cfae3730eeb8500
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1042915
diff --git a/hif/inc/hostdef.h b/hif/inc/hostdef.h
index b291bbf..da330ba 100644
--- a/hif/inc/hostdef.h
+++ b/hif/inc/hostdef.h
@@ -35,6 +35,7 @@
extern struct hostdef_s *QCA9888_HOSTdef;
#ifdef ATH_AHB
extern struct hostdef_s *IPQ4019_HOSTdef;
+extern struct hostdef_s *QCA8074_HOSTdef;
#endif
#endif
diff --git a/hif/inc/reg_struct.h b/hif/inc/reg_struct.h
index d1f8c79..e87e396 100644
--- a/hif/inc/reg_struct.h
+++ b/hif/inc/reg_struct.h
@@ -609,6 +609,7 @@
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
uint32_t d_HOST_IE_ADDRESS;
+ uint32_t d_HOST_IE_ADDRESS_2;
uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
uint32_t d_SR_BA_ADDRESS;
uint32_t d_SR_BA_ADDRESS_HIGH;
diff --git a/hif/inc/target_reg_init.h b/hif/inc/target_reg_init.h
index 4948785..e6146a4 100644
--- a/hif/inc/target_reg_init.h
+++ b/hif/inc/target_reg_init.h
@@ -355,6 +355,9 @@
#if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS)
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET
#endif
+#if !defined(HOST_IE_ADDRESS_2)
+#define HOST_IE_ADDRESS_2 ATH_UNSUPPORTED_REG_OFFSET
+#endif
static struct ce_reg_def my_ce_reg_def = {
/* copy_engine.c */
@@ -383,6 +386,7 @@
.d_CE_DDR_ADDRESS_FOR_RRI_LOW = CE_DDR_ADDRESS_FOR_RRI_LOW,
.d_CE_DDR_ADDRESS_FOR_RRI_HIGH = CE_DDR_ADDRESS_FOR_RRI_HIGH,
.d_HOST_IE_ADDRESS = HOST_IE_ADDRESS,
+ .d_HOST_IE_ADDRESS_2 = HOST_IE_ADDRESS_2,
.d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK,
.d_SR_BA_ADDRESS = SR_BA_ADDRESS,
.d_SR_BA_ADDRESS_HIGH = SR_BA_ADDRESS_HIGH,
diff --git a/hif/inc/targetdef.h b/hif/inc/targetdef.h
index 0c99e0f..7c16d04 100644
--- a/hif/inc/targetdef.h
+++ b/hif/inc/targetdef.h
@@ -35,6 +35,7 @@
extern struct targetdef_s *QCA9888_TARGETdef;
#ifdef ATH_AHB
extern struct targetdef_s *IPQ4019_TARGETdef;
+extern struct targetdef_s *QCA8074_TARGETdef;
#endif
extern struct ce_reg_def *AR6002_CE_TARGETdef;
@@ -48,6 +49,7 @@
extern struct ce_reg_def *QCA9888_CE_TARGETdef;
#ifdef ATH_AHB
extern struct ce_reg_def *IPQ4019_CE_TARGETdef;
+extern struct ce_reg_def *QCA8074_CE_TARGETdef;
#endif
diff --git a/hif/src/ce/ce_reg.h b/hif/src/ce/ce_reg.h
index 297e88f..5d3ac7f 100644
--- a/hif/src/ce/ce_reg.h
+++ b/hif/src/ce/ce_reg.h
@@ -193,6 +193,7 @@
#define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
#define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
#define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
+#define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2)
#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
#define SRC_WATERMARK_LOW_SET(x) \
diff --git a/hif/src/qca8074def.c b/hif/src/qca8074def.c
new file mode 100644
index 0000000..3a99f92
--- /dev/null
+++ b/hif/src/qca8074def.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#if defined(QCA8074_HEADERS_DEF)
+
+#undef UMAC
+#define WLAN_HEADERS 1
+
+#include <qca8074/hw/reg_header/defines/lithium_top_reg.h>
+
+#define MISSING 0
+
+#define SOC_RESET_CONTROL_OFFSET MISSING
+#define GPIO_PIN0_OFFSET MISSING
+#define GPIO_PIN1_OFFSET MISSING
+#define GPIO_PIN0_CONFIG_MASK MISSING
+#define GPIO_PIN1_CONFIG_MASK MISSING
+#define LOCAL_SCRATCH_OFFSET 0x18
+#define GPIO_PIN10_OFFSET MISSING
+#define GPIO_PIN11_OFFSET MISSING
+#define GPIO_PIN12_OFFSET MISSING
+#define GPIO_PIN13_OFFSET MISSING
+#define MBOX_BASE_ADDRESS MISSING
+#define INT_STATUS_ENABLE_ERROR_LSB MISSING
+#define INT_STATUS_ENABLE_ERROR_MASK MISSING
+#define INT_STATUS_ENABLE_CPU_LSB MISSING
+#define INT_STATUS_ENABLE_CPU_MASK MISSING
+#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
+#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define INT_STATUS_ENABLE_ADDRESS MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define HOST_INT_STATUS_ADDRESS MISSING
+#define CPU_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
+#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
+#define COUNT_DEC_ADDRESS MISSING
+#define HOST_INT_STATUS_CPU_MASK MISSING
+#define HOST_INT_STATUS_CPU_LSB MISSING
+#define HOST_INT_STATUS_ERROR_MASK MISSING
+#define HOST_INT_STATUS_ERROR_LSB MISSING
+#define HOST_INT_STATUS_COUNTER_MASK MISSING
+#define HOST_INT_STATUS_COUNTER_LSB MISSING
+#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
+#define WINDOW_DATA_ADDRESS MISSING
+#define WINDOW_READ_ADDR_ADDRESS MISSING
+#define WINDOW_WRITE_ADDR_ADDRESS MISSING
+/* GPIO Register */
+#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
+#define GPIO_PIN0_CONFIG_LSB MISSING
+#define GPIO_PIN0_PAD_PULL_LSB MISSING
+#define GPIO_PIN0_PAD_PULL_MASK MISSING
+/* SI reg */
+#define SI_CONFIG_ERR_INT_MASK MISSING
+#define SI_CONFIG_ERR_INT_LSB MISSING
+
+#define RTC_SOC_BASE_ADDRESS MISSING
+#define RTC_WMAC_BASE_ADDRESS MISSING
+#define SOC_CORE_BASE_ADDRESS MISSING
+#define WLAN_MAC_BASE_ADDRESS MISSING
+#define GPIO_BASE_ADDRESS MISSING
+#define ANALOG_INTF_BASE_ADDRESS MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define CE_COUNT 12
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define SI_BASE_ADDRESS MISSING
+#define DRAM_BASE_ADDRESS MISSING
+
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
+#define CLOCK_CONTROL_OFFSET MISSING
+#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
+#define RESET_CONTROL_SI0_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_OFFSET MISSING
+#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
+#define CPU_CLOCK_OFFSET MISSING
+
+#define CPU_CLOCK_STANDARD_LSB MISSING
+#define CPU_CLOCK_STANDARD_MASK MISSING
+#define LPO_CAL_ENABLE_LSB MISSING
+#define LPO_CAL_ENABLE_MASK MISSING
+#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
+
+#define SOC_CHIP_ID_ADDRESS MISSING
+#define SOC_CHIP_ID_REVISION_MASK MISSING
+#define SOC_CHIP_ID_REVISION_LSB MISSING
+#define SOC_CHIP_ID_REVISION_MSB MISSING
+
+#define FW_IND_EVENT_PENDING MISSING
+#define FW_IND_INITIALIZED MISSING
+
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
+
+#define SR_WR_INDEX_ADDRESS MISSING
+#define DST_WATERMARK_ADDRESS MISSING
+
+#define DST_WR_INDEX_ADDRESS MISSING
+#define SRC_WATERMARK_ADDRESS MISSING
+#define SRC_WATERMARK_LOW_MASK MISSING
+#define SRC_WATERMARK_HIGH_MASK MISSING
+#define DST_WATERMARK_LOW_MASK MISSING
+#define DST_WATERMARK_HIGH_MASK MISSING
+#define CURRENT_SRRI_ADDRESS MISSING
+#define CURRENT_DRRI_ADDRESS MISSING
+#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_ADDRESS MISSING
+#define MISC_IS_ADDRESS MISSING
+#define HOST_IS_COPY_COMPLETE_MASK MISSING
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
+#define HOST_IE_ADDRESS UMAC_CE_COMMON_CE_HOST_IE_0
+#define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_CE_HOST_IE_1
+#define HOST_IE_COPY_COMPLETE_MASK MISSING
+#define SR_BA_ADDRESS MISSING
+#define SR_BA_ADDRESS_HIGH MISSING
+#define SR_SIZE_ADDRESS MISSING
+#define CE_CTRL1_ADDRESS MISSING
+#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
+#define DR_BA_ADDRESS MISSING
+#define DR_BA_ADDRESS_HIGH MISSING
+#define DR_SIZE_ADDRESS MISSING
+#define CE_CMD_REGISTER MISSING
+#define CE_MSI_ADDRESS MISSING
+#define CE_MSI_ADDRESS_HIGH MISSING
+#define CE_MSI_DATA MISSING
+#define CE_MSI_ENABLE_BIT MISSING
+#define MISC_IE_ADDRESS MISSING
+#define MISC_IS_AXI_ERR_MASK MISSING
+#define MISC_IS_DST_ADDR_ERR_MASK MISSING
+#define MISC_IS_SRC_LEN_ERR_MASK MISSING
+#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
+#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
+#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
+#define SRC_WATERMARK_LOW_LSB MISSING
+#define SRC_WATERMARK_HIGH_LSB MISSING
+#define DST_WATERMARK_LOW_LSB MISSING
+#define DST_WATERMARK_HIGH_LSB MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
+#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
+#define CE_WRAPPER_DEBUG_OFFSET MISSING
+#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
+#define CE_DEBUG_OFFSET MISSING
+#define CE_DEBUG_SEL_MSB MISSING
+#define CE_DEBUG_SEL_LSB MISSING
+#define CE_DEBUG_SEL_MASK MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
+
+#define QCA8074_BOARD_DATA_SZ MISSING
+#define QCA8074_BOARD_EXT_DATA_SZ MISSING
+
+#define MY_TARGET_DEF QCA8074_TARGETdef
+#define MY_HOST_DEF QCA8074_HOSTdef
+#define MY_CEREG_DEF QCA8074_CE_TARGETdef
+#define MY_TARGET_BOARD_DATA_SZ QCA8074_BOARD_DATA_SZ
+#define MY_TARGET_BOARD_EXT_DATA_SZ QCA8074_BOARD_EXT_DATA_SZ
+#include "targetdef.h"
+#include "hostdef.h"
+#else
+#include "common_drv.h"
+#include "targetdef.h"
+#include "hostdef.h"
+struct targetdef_s *QCA8074_TARGETdef;
+struct hostdef_s *QCA8074_HOSTdef;
+#endif /*QCA8074_HEADERS_DEF */