qcacmn: Add legacy DP CFG items and APIs
Add the basic infra for legacy DP CFG items and the APIs to be used from
other components.
Change-Id: Iec1718f0a93fcb91061892b96ae6ae88174df9ee
CRs-Fixed: 2328481
diff --git a/dp/inc/cdp_txrx_cmn.h b/dp/inc/cdp_txrx_cmn.h
index 1d61acb..1532a65 100644
--- a/dp/inc/cdp_txrx_cmn.h
+++ b/dp/inc/cdp_txrx_cmn.h
@@ -2047,4 +2047,26 @@
soc->ops->cmn_drv_ops->txrx_get_ba_aging_timeout(soc, ac, value);
}
+
+/**
+ * cdp_cfg_get() - get cfg for dp enum
+ *
+ * @soc: pointer to the soc
+ * @cfg: cfg enum
+ *
+ * Return - cfg value
+ */
+static inline uint32_t cdp_cfg_get(ol_txrx_soc_handle soc, enum cdp_dp_cfg cfg)
+{
+ if (!soc || !soc->ops) {
+ QDF_TRACE(QDF_MODULE_ID_CDP, QDF_TRACE_LEVEL_DEBUG,
+ "%s: Invalid Instance", __func__);
+ return 0;
+ }
+
+ if (!soc->ops->cmn_drv_ops || !soc->ops->cmn_drv_ops->txrx_get_cfg)
+ return 0;
+
+ return soc->ops->cmn_drv_ops->txrx_get_cfg(soc, cfg);
+}
#endif /* _CDP_TXRX_CMN_H_ */
diff --git a/dp/inc/cdp_txrx_cmn_struct.h b/dp/inc/cdp_txrx_cmn_struct.h
index d717a0c..0403143 100644
--- a/dp/inc/cdp_txrx_cmn_struct.h
+++ b/dp/inc/cdp_txrx_cmn_struct.h
@@ -1349,4 +1349,24 @@
uint16_t mo_ctrl;
uint16_t mo_data;
};
+
+/**
+ * cdp_dp_cfg - dp ini config enum
+ */
+enum cdp_dp_cfg {
+ cfg_dp_enable_data_stall,
+ cfg_dp_enable_ip_tcp_udp_checksum_offload,
+ cfg_dp_tso_enable,
+ cfg_dp_lro_enable,
+ cfg_dp_gro_enable,
+ cfg_dp_tx_flow_start_queue_offset,
+ cfg_dp_tx_flow_stop_queue_threshold,
+ cfg_dp_ipa_uc_tx_buf_size,
+ cfg_dp_ipa_uc_tx_partition_base,
+ cfg_dp_ipa_uc_rx_ind_ring_count,
+ cfg_dp_enable_flow_steering,
+ cfg_dp_reorder_offload_supported,
+ cfg_dp_ce_classify_enable,
+ cfg_dp_disable_intra_bss_fwd,
+};
#endif
diff --git a/dp/inc/cdp_txrx_mob_def.h b/dp/inc/cdp_txrx_mob_def.h
index 2107b77..193f7c9 100644
--- a/dp/inc/cdp_txrx_mob_def.h
+++ b/dp/inc/cdp_txrx_mob_def.h
@@ -294,6 +294,12 @@
#endif
struct ol_tx_sched_wrr_ac_specs_t ac_specs[TX_WMM_AC_NUM];
+ bool gro_enable;
+ bool tso_enable;
+ bool lro_enable;
+ bool enable_data_stall_detection;
+ bool enable_flow_steering;
+ bool disable_intra_bss_fwd;
};
#ifdef IPA_OFFLOAD
diff --git a/dp/inc/cdp_txrx_ops.h b/dp/inc/cdp_txrx_ops.h
index 98148ee..3cee76c 100644
--- a/dp/inc/cdp_txrx_ops.h
+++ b/dp/inc/cdp_txrx_ops.h
@@ -182,6 +182,8 @@
void (*txrx_set_privacy_filters)
(struct cdp_vdev *vdev, void *filter, uint32_t num);
+ uint32_t (*txrx_get_cfg)(void *soc, enum cdp_dp_cfg cfg);
+
/********************************************************************
* Data Interface (B Interface)
********************************************************************/
diff --git a/dp/wifi3.0/dp_main.c b/dp/wifi3.0/dp_main.c
index 07bc0dc..e462a24 100644
--- a/dp/wifi3.0/dp_main.c
+++ b/dp/wifi3.0/dp_main.c
@@ -7904,6 +7904,50 @@
pdev->ctrl_pdev = ctrl_pdev;
}
+/*
+ * dp_get_cfg() - get dp cfg
+ * @soc: cdp soc handle
+ * @cfg: cfg enum
+ *
+ * Return: cfg value
+ */
+static uint32_t dp_get_cfg(void *soc, enum cdp_dp_cfg cfg)
+{
+ struct dp_soc *dpsoc = (struct dp_soc *)soc;
+ uint32_t value = 0;
+
+ switch (cfg) {
+ case cfg_dp_enable_data_stall:
+ value = dpsoc->wlan_cfg_ctx->enable_data_stall_detection;
+ break;
+ case cfg_dp_enable_ip_tcp_udp_checksum_offload:
+ value = dpsoc->wlan_cfg_ctx->tcp_udp_checksumoffload;
+ break;
+ case cfg_dp_tso_enable:
+ value = dpsoc->wlan_cfg_ctx->tso_enabled;
+ break;
+ case cfg_dp_lro_enable:
+ value = dpsoc->wlan_cfg_ctx->lro_enabled;
+ break;
+ case cfg_dp_gro_enable:
+ value = dpsoc->wlan_cfg_ctx->gro_enabled;
+ break;
+ case cfg_dp_tx_flow_start_queue_offset:
+ value = dpsoc->wlan_cfg_ctx->tx_flow_start_queue_offset;
+ break;
+ case cfg_dp_tx_flow_stop_queue_threshold:
+ value = dpsoc->wlan_cfg_ctx->tx_flow_stop_queue_threshold;
+ break;
+ case cfg_dp_disable_intra_bss_fwd:
+ value = dpsoc->wlan_cfg_ctx->disable_intra_bss_fwd;
+ break;
+ default:
+ value = 0;
+ }
+
+ return value;
+}
+
static struct cdp_cmn_ops dp_ops_cmn = {
.txrx_soc_attach_target = dp_soc_attach_target_wifi3,
.txrx_vdev_attach = dp_vdev_attach_wifi3,
@@ -7987,6 +8031,7 @@
dp_get_os_rx_handles_from_vdev_wifi3,
.delba_tx_completion = dp_delba_tx_completion_wifi3,
.get_dp_capabilities = dp_get_cfg_capabilities,
+ .txrx_get_cfg = dp_get_cfg,
};
static struct cdp_ctrl_ops dp_ops_ctrl = {
diff --git a/wlan_cfg/cfg_dp.h b/wlan_cfg/cfg_dp.h
index f0c97eb..86d14cb 100644
--- a/wlan_cfg/cfg_dp.h
+++ b/wlan_cfg/cfg_dp.h
@@ -39,13 +39,16 @@
#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
#ifdef CONFIG_MCL
-#ifdef IPA_OFFLOAD
-#define WLAN_CFG_PER_PDEV_TX_RING 0
+#ifdef QCA_LL_TX_FLOW_CONTROL_V2
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
#else
-#define WLAN_CFG_PER_PDEV_TX_RING 1
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
#endif
#else
-#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
#endif
#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
@@ -54,11 +57,19 @@
#ifdef CONFIG_MCL
#define WLAN_CFG_PER_PDEV_RX_RING 0
#define WLAN_CFG_PER_PDEV_LMAC_RING 0
-#define WLAN_LRO_ENABLE 1
+#define WLAN_LRO_ENABLE 0
#ifdef IPA_OFFLOAD
#define WLAN_CFG_TX_RING_SIZE 2048
+#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
#else
#define WLAN_CFG_TX_RING_SIZE 512
+#define WLAN_CFG_PER_PDEV_TX_RING 1
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
#endif
#define WLAN_CFG_TX_COMP_RING_SIZE 1024
@@ -75,6 +86,11 @@
#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
+#else
+#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
#endif
#ifdef CONFIG_WIN
@@ -467,7 +483,7 @@
"DP Napi Enabled")
#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
- CFG_INI_BOOL("dp_tcp_udp_checksumoffload", true, \
+ CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
"DP TCP UDP Checksum Offload")
#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
@@ -579,6 +595,44 @@
WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
+#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
+ CFG_INI_UINT("TxFlowStartQueueOffset", \
+ 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
+ CFG_VALUE_OR_DEFAULT, "Start queue offset")
+
+#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
+ CFG_INI_UINT("TxFlowStopQueueThreshold", \
+ 0, 50, 15, \
+ CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
+
+#define CFG_DP_IPA_UC_TX_BUF_SIZE \
+ CFG_INI_UINT("IpaUcTxBufSize", \
+ 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
+ CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
+
+#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
+ CFG_INI_UINT("IpaUcTxPartitionBase", \
+ 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
+ CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
+
+#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
+ CFG_INI_UINT("IpaUcRxIndRingCount", \
+ 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
+ CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
+
+#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
+ CFG_INI_UINT("gReorderOffloadSupported", \
+ 0, 1, 1, \
+ CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
+
+#define CFG_DP_AP_STA_SECURITY_SEPERATION \
+ CFG_INI_BOOL("gDisableIntraBssFwd", \
+ false, "Disable intrs BSS Rx packets")
+
+#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
+ CFG_INI_BOOL("gEnableDataStallDetection", \
+ true, "Enable/Disable Data stall detection")
+
#define CFG_DP \
CFG(CFG_DP_HTT_PACKET_TYPE) \
CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
@@ -629,6 +683,14 @@
CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
- CFG(CFG_DP_RXDMA_ERR_DST_RING)
+ CFG(CFG_DP_RXDMA_ERR_DST_RING) \
+ CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
+ CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
+ CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
+ CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
+ CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
+ CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
+ CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
+ CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
#endif /* _CFG_DP_H_ */
diff --git a/wlan_cfg/wlan_cfg.c b/wlan_cfg/wlan_cfg.c
index d4aa81a..17c6662 100644
--- a/wlan_cfg/wlan_cfg.c
+++ b/wlan_cfg/wlan_cfg.c
@@ -310,12 +310,18 @@
CFG_DP_REO_CMD_RING);
wlan_cfg_ctx->reo_status_ring = cfg_get(psoc,
CFG_DP_REO_STATUS_RING);
-
wlan_cfg_ctx->rxdma_refill_ring = cfg_get(psoc,
CFG_DP_RXDMA_REFILL_RING);
-
wlan_cfg_ctx->rxdma_err_dst_ring = cfg_get(psoc,
CFG_DP_RXDMA_ERR_DST_RING);
+ wlan_cfg_ctx->enable_data_stall_detection =
+ cfg_get(psoc, CFG_DP_ENABLE_DATA_STALL_DETECTION);
+ wlan_cfg_ctx->tx_flow_start_queue_offset =
+ cfg_get(psoc, CFG_DP_TX_FLOW_START_QUEUE_OFFSET);
+ wlan_cfg_ctx->tx_flow_stop_queue_threshold =
+ cfg_get(psoc, CFG_DP_TX_FLOW_STOP_QUEUE_TH);
+ wlan_cfg_ctx->disable_intra_bss_fwd =
+ cfg_get(psoc, CFG_DP_AP_STA_SECURITY_SEPERATION);
return wlan_cfg_ctx;
}
diff --git a/wlan_cfg/wlan_cfg.h b/wlan_cfg/wlan_cfg.h
index bbe521f..7988a6e 100644
--- a/wlan_cfg/wlan_cfg.h
+++ b/wlan_cfg/wlan_cfg.h
@@ -177,10 +177,8 @@
bool tcp_udp_checksumoffload;
bool defrag_timeout_check;
int nss_cfg;
-#ifdef QCA_LL_TX_FLOW_CONTROL_V2
uint32_t tx_flow_stop_queue_threshold;
uint32_t tx_flow_start_queue_offset;
-#endif
int rx_defrag_min_timeout;
int reo_dst_ring_size;
int wbm_release_ring;
@@ -195,6 +193,8 @@
int rxdma_refill_ring;
int rxdma_err_dst_ring;
bool raw_mode_war;
+ bool enable_data_stall_detection;
+ bool disable_intra_bss_fwd;
};
/**