diff --git a/wlan_cfg/cfg_dp.h b/wlan_cfg/cfg_dp.h
index f0c97eb..86d14cb 100644
--- a/wlan_cfg/cfg_dp.h
+++ b/wlan_cfg/cfg_dp.h
@@ -39,13 +39,16 @@
 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
 
 #ifdef CONFIG_MCL
-#ifdef IPA_OFFLOAD
-#define WLAN_CFG_PER_PDEV_TX_RING 0
+#ifdef QCA_LL_TX_FLOW_CONTROL_V2
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
 #else
-#define WLAN_CFG_PER_PDEV_TX_RING 1
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
 #endif
 #else
-#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
+#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
 #endif
 
 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
@@ -54,11 +57,19 @@
 #ifdef CONFIG_MCL
 #define WLAN_CFG_PER_PDEV_RX_RING 0
 #define WLAN_CFG_PER_PDEV_LMAC_RING 0
-#define WLAN_LRO_ENABLE 1
+#define WLAN_LRO_ENABLE 0
 #ifdef IPA_OFFLOAD
 #define WLAN_CFG_TX_RING_SIZE 2048
+#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
 #else
 #define WLAN_CFG_TX_RING_SIZE 512
+#define WLAN_CFG_PER_PDEV_TX_RING 1
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
 #endif
 #define WLAN_CFG_TX_COMP_RING_SIZE 1024
 
@@ -75,6 +86,11 @@
 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
+#else
+#define WLAN_CFG_PER_PDEV_TX_RING 0
+#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
+#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
+#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
 #endif
 
 #ifdef CONFIG_WIN
@@ -467,7 +483,7 @@
 	"DP Napi Enabled")
 
 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
-	CFG_INI_BOOL("dp_tcp_udp_checksumoffload", true, \
+	CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
 	"DP TCP UDP Checksum Offload")
 
 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \
@@ -579,6 +595,44 @@
 		WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
 		CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
 
+#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
+		CFG_INI_UINT("TxFlowStartQueueOffset", \
+		0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
+		CFG_VALUE_OR_DEFAULT, "Start queue offset")
+
+#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
+		CFG_INI_UINT("TxFlowStopQueueThreshold", \
+		0, 50, 15, \
+		CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
+
+#define CFG_DP_IPA_UC_TX_BUF_SIZE \
+		CFG_INI_UINT("IpaUcTxBufSize", \
+		0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
+		CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
+
+#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
+		CFG_INI_UINT("IpaUcTxPartitionBase", \
+		0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
+		CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
+
+#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
+		CFG_INI_UINT("IpaUcRxIndRingCount", \
+		0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
+		CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
+
+#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
+		CFG_INI_UINT("gReorderOffloadSupported", \
+		0, 1, 1, \
+		CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
+
+#define CFG_DP_AP_STA_SECURITY_SEPERATION \
+			CFG_INI_BOOL("gDisableIntraBssFwd", \
+			false, "Disable intrs BSS Rx packets")
+
+#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
+		CFG_INI_BOOL("gEnableDataStallDetection", \
+		true, "Enable/Disable Data stall detection")
+
 #define CFG_DP \
 		CFG(CFG_DP_HTT_PACKET_TYPE) \
 		CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
@@ -629,6 +683,14 @@
 		CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
 		CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
 		CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
-		CFG(CFG_DP_RXDMA_ERR_DST_RING)
+		CFG(CFG_DP_RXDMA_ERR_DST_RING) \
+		CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
+		CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
+		CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
+		CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
+		CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
+		CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
+		CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
+		CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
 
 #endif /* _CFG_DP_H_ */