qcacmn: Support register writing result check for IPA case
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
diff --git a/hal/wifi3.0/hal_api.h b/hal/wifi3.0/hal_api.h
index 6eec126..b1b7f74 100644
--- a/hal/wifi3.0/hal_api.h
+++ b/hal/wifi3.0/hal_api.h
@@ -71,6 +71,41 @@
}
#endif
+#ifdef HAL_REGISTER_WRITE_DEBUG
+/**
+ * hal_reg_write_result_check() - check register writing result
+ * @hal_soc: HAL soc handle
+ * @offset: register offset to read
+ * @exp_val: the expected value of register
+ * @ret_confirm: result confirm flag
+ *
+ * Return: none
+ */
+static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
+ uint32_t offset,
+ uint32_t exp_val,
+ bool ret_confirm)
+{
+ uint32_t value;
+
+ if (!ret_confirm)
+ return;
+
+ value = qdf_ioread32(hal_soc->dev_base_addr + offset);
+ if (exp_val != value) {
+ QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
+ "register offset 0x%x write failed!\n", offset);
+ QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
+ "the expectation 0x%x, actual value 0x%x\n",
+ exp_val,
+ value);
+ }
+}
+#else
+/* no op */
+#define hal_reg_write_result_check(_hal_soc, _offset, _exp_val, _ret_confirm)
+#endif
+
#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
static inline int hal_force_wake_request(struct hal_soc *soc)
{
@@ -138,22 +173,34 @@
#endif
#ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
-static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
+static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset,
+ bool ret_confirm)
{
uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
WINDOW_ENABLE_BIT | window);
hal_soc->register_window = window;
+
+ hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
+ WINDOW_ENABLE_BIT | window,
+ ret_confirm);
}
#else
-static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
+static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset,
+ bool ret_confirm)
{
uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
if (window != hal_soc->register_window) {
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
WINDOW_ENABLE_BIT | window);
hal_soc->register_window = window;
+
+ hal_reg_write_result_check(
+ hal_soc,
+ WINDOW_REG_ADDRESS,
+ WINDOW_ENABLE_BIT | window,
+ ret_confirm);
}
}
#endif
@@ -166,24 +213,31 @@
*/
#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
- uint32_t value)
+ uint32_t value, bool ret_confirm)
{
unsigned long flags;
if (!hal_soc->use_register_windowing ||
offset < MAX_UNWINDOWED_ADDRESS) {
qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
+ hal_reg_write_result_check(hal_soc, offset,
+ value, ret_confirm);
} else {
hal_lock_reg_access(hal_soc, &flags);
- hal_select_window(hal_soc, offset);
+ hal_select_window(hal_soc, offset, ret_confirm);
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK), value);
+
+ hal_reg_write_result_check(
+ hal_soc,
+ WINDOW_START + (offset & WINDOW_RANGE_MASK),
+ value, ret_confirm);
hal_unlock_reg_access(hal_soc, &flags);
}
}
#else
static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
- uint32_t value)
+ uint32_t value, bool ret_confirm)
{
int ret;
unsigned long flags;
@@ -202,11 +256,19 @@
if (!hal_soc->use_register_windowing ||
offset < MAX_UNWINDOWED_ADDRESS) {
qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
+ hal_reg_write_result_check(hal_soc, offset,
+ value, ret_confirm);
} else {
hal_lock_reg_access(hal_soc, &flags);
- hal_select_window(hal_soc, offset);
+ hal_select_window(hal_soc, offset, ret_confirm);
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK), value);
+
+ hal_reg_write_result_check(
+ hal_soc,
+ WINDOW_START + (offset & WINDOW_RANGE_MASK),
+ value,
+ ret_confirm);
hal_unlock_reg_access(hal_soc, &flags);
}
@@ -231,7 +293,7 @@
return qdf_iowrite32(addr, value);
offset = addr - hal_soc->dev_base_addr;
- hal_write32_mb(hal_soc, offset, value);
+ hal_write32_mb(hal_soc, offset, value, false);
}
#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
@@ -246,7 +308,7 @@
}
hal_lock_reg_access(hal_soc, &flags);
- hal_select_window(hal_soc, offset);
+ hal_select_window(hal_soc, offset, false);
ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK));
hal_unlock_reg_access(hal_soc, &flags);
@@ -293,7 +355,7 @@
}
hal_lock_reg_access(hal_soc, &flags);
- hal_select_window(hal_soc, offset);
+ hal_select_window(hal_soc, offset, false);
ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK));
hal_unlock_reg_access(hal_soc, &flags);
diff --git a/hal/wifi3.0/hal_hw_headers.h b/hal/wifi3.0/hal_hw_headers.h
index b1b1dec..d363d12 100644
--- a/hal/wifi3.0/hal_hw_headers.h
+++ b/hal/wifi3.0/hal_hw_headers.h
@@ -113,7 +113,11 @@
(_reg ## _ ## _fld ## _SHFT))
#define HAL_REG_WRITE(_soc, _reg, _value) \
- hal_write32_mb(_soc, (_reg), (_value))
+ hal_write32_mb(_soc, (_reg), (_value), false)
+
+/* Check register writing result */
+#define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \
+ hal_write32_mb(_soc, (_reg), (_value), true)
#define HAL_REG_READ(_soc, _offset) \
hal_read32_mb(_soc, (_offset))
diff --git a/hal/wifi3.0/hal_srng.c b/hal/wifi3.0/hal_srng.c
index d683985..1234459 100644
--- a/hal/wifi3.0/hal_srng.c
+++ b/hal/wifi3.0/hal_srng.c
@@ -492,7 +492,7 @@
reg_offset =
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET);
- HAL_REG_WRITE(hal, reg_offset, *ix0);
+ HAL_REG_WRITE_CONFIRM(hal, reg_offset, *ix0);
}
if (ix1) {