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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / abac9eedad7455b54e0abb627af54c7a79598b73 / . / wlan_cfg / cfg_dp.h
blob: 261d428e436cfc3cb181504067d30ed3b01c5f51 [file] [log] [blame]
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]1/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800[diff] [blame]2 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]29#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]30#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -0700[diff] [blame]34#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]35#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
hangtian04f0ad42019-06-07 11:04:02 +0800[diff] [blame]41#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]43#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
44#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]45#else
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]46#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
47#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]48#endif
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]49
50#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
51#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
52
Vevek Venkatesan4a6c3e82019-06-24 14:29:19 +0530[diff] [blame]53#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]54#define WLAN_CFG_PER_PDEV_RX_RING 0
55#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]56#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -0700[diff] [blame]57#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]58#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -0700[diff] [blame]59/* Size of TCL TX Ring */
60#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]61#define WLAN_CFG_PER_PDEV_TX_RING 0
62#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
63#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
64#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]65#else
66#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]67#define WLAN_CFG_PER_PDEV_TX_RING 1
68#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
69#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
70#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]71#endif
72#define WLAN_CFG_TX_COMP_RING_SIZE 1024
73
74/* Tx Descriptor and Tx Extension Descriptor pool sizes */
75#define WLAN_CFG_NUM_TX_DESC 1024
76#define WLAN_CFG_NUM_TX_EXT_DESC 1024
77
78/* Interrupt Mitigation - Batch threshold in terms of number of frames */
79#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
80#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
81#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
82
83/* Interrupt Mitigation - Timer threshold in us */
84#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
85#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
86#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]87#endif
88
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]89#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256
90#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 256
91
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]92#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
93#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
94
95#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
96#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
97
98#define WLAN_CFG_TX_RING_SIZE_MIN 512
99#define WLAN_CFG_TX_RING_SIZE_MAX 2048
100
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]101#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]102#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
103
104#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530[diff] [blame]105#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]106
107#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
108#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
109
110#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
111#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
112
113#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
114#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
115
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]116#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1
117#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128
118
119#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1
120#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128
121
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]122#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
123#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
124
125#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
126#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
127
128#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
129#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
130
131#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
132#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
133
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]134#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8
135#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 500
136
137#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8
138#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500
139
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530[diff] [blame]140#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
141#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530[diff] [blame]142#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]143
144#ifdef QCA_LL_TX_FLOW_CONTROL_V2
145
146/* Per vdev pools */
147#define WLAN_CFG_NUM_TX_DESC_POOL 3
148#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
149
150#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
151
152#ifdef TX_PER_PDEV_DESC_POOL
153#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
154#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
155
156#else /* TX_PER_PDEV_DESC_POOL */
157
158#define WLAN_CFG_NUM_TX_DESC_POOL 3
159#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
160
161#endif /* TX_PER_PDEV_DESC_POOL */
162#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
163
164#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
165#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
166
167#define WLAN_CFG_HTT_PKT_TYPE 2
168#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
169#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
170
171#define WLAN_CFG_MAX_PEER_ID 64
172#define WLAN_CFG_MAX_PEER_ID_MIN 64
173#define WLAN_CFG_MAX_PEER_ID_MAX 64
174
175#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
176#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
177#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
178
179#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
180#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
181#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
182
183#define WLAN_CFG_NUM_REO_DEST_RING 4
184#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
185#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
186
187#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
188#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
189#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
190
191#define WLAN_CFG_TCL_CMD_RING_SIZE 32
192#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
193#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
194
195#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
196#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
197#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
198
199#if defined(QCA_WIFI_QCA6290)
200#define WLAN_CFG_REO_DST_RING_SIZE 1024
201#else
202#define WLAN_CFG_REO_DST_RING_SIZE 2048
203#endif
204
205#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
206#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
207
208#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
209#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
210#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
211
212#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]213#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530[diff] [blame]214#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]215#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530[diff] [blame]216#else
217#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
218#endif
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]219
220#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
221#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
222#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
223
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]224#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]225#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]226#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]227
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700[diff] [blame]228#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]229#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800[diff] [blame]230#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]231
232#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
233#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
234#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
235
236#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]237#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]238#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
239
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame]240#define WLAN_CFG_TX_DESC_LIMIT_0 0
241#define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096
242#define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768
243
244#define WLAN_CFG_TX_DESC_LIMIT_1 0
245#define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096
246#define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768
247
248#define WLAN_CFG_TX_DESC_LIMIT_2 0
249#define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096
250#define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768
251
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530[diff] [blame]252#define WLAN_CFG_TX_DEVICE_LIMIT 65536
253#define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384
254#define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536
255
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530[diff] [blame^]256#define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024
257#define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128
258#define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024
259
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]260#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]261#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]262#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]263
264#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]265#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]266#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]267
268#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530[diff] [blame]269#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]270#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]271
272#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
273#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800[diff] [blame]274#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]275
276#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
277#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700[diff] [blame]278#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]279
280/* DP INI Declerations */
281#define CFG_DP_HTT_PACKET_TYPE \
282 CFG_INI_UINT("dp_htt_packet_type", \
283 WLAN_CFG_HTT_PKT_TYPE_MIN, \
284 WLAN_CFG_HTT_PKT_TYPE_MAX, \
285 WLAN_CFG_HTT_PKT_TYPE, \
286 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
287
288#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
289 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700[diff] [blame]290 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
291 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
292 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]293 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other")
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]294
295#define CFG_DP_INT_BATCH_THRESHOLD_RX \
296 CFG_INI_UINT("dp_int_batch_threshold_rx", \
297 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
298 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
299 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]300 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx")
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]301
302#define CFG_DP_INT_BATCH_THRESHOLD_TX \
303 CFG_INI_UINT("dp_int_batch_threshold_tx", \
304 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
305 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
306 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
307 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
308
309#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
310 CFG_INI_UINT("dp_int_timer_threshold_other", \
311 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
312 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
313 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
314 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
315
316#define CFG_DP_INT_TIMER_THRESHOLD_RX \
317 CFG_INI_UINT("dp_int_timer_threshold_rx", \
318 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
319 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
320 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
321 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
322
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700[diff] [blame]323#define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \
324 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \
325 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \
326 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \
327 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \
328 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring")
329
330#define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \
331 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \
332 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \
333 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \
334 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \
335 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring")
336
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]337#define CFG_DP_INT_TIMER_THRESHOLD_TX \
338 CFG_INI_UINT("dp_int_timer_threshold_tx", \
339 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
340 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
341 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
342 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
343
344#define CFG_DP_MAX_ALLOC_SIZE \
345 CFG_INI_UINT("dp_max_alloc_size", \
346 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
347 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
348 WLAN_CFG_MAX_ALLOC_SIZE, \
349 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
350
351#define CFG_DP_MAX_CLIENTS \
352 CFG_INI_UINT("dp_max_clients", \
353 WLAN_CFG_MAX_CLIENTS_MIN, \
354 WLAN_CFG_MAX_CLIENTS_MAX, \
355 WLAN_CFG_MAX_CLIENTS, \
356 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
357
358#define CFG_DP_MAX_PEER_ID \
359 CFG_INI_UINT("dp_max_peer_id", \
360 WLAN_CFG_MAX_PEER_ID_MIN, \
361 WLAN_CFG_MAX_PEER_ID_MAX, \
362 WLAN_CFG_MAX_PEER_ID, \
363 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
364
365#define CFG_DP_REO_DEST_RINGS \
366 CFG_INI_UINT("dp_reo_dest_rings", \
367 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
368 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
369 WLAN_CFG_NUM_REO_DEST_RING, \
370 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
371
372#define CFG_DP_TCL_DATA_RINGS \
373 CFG_INI_UINT("dp_tcl_data_rings", \
374 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
375 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
376 WLAN_CFG_NUM_TCL_DATA_RINGS, \
377 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
378
379#define CFG_DP_TX_DESC \
380 CFG_INI_UINT("dp_tx_desc", \
381 WLAN_CFG_NUM_TX_DESC_MIN, \
382 WLAN_CFG_NUM_TX_DESC_MAX, \
383 WLAN_CFG_NUM_TX_DESC, \
384 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
385
386#define CFG_DP_TX_EXT_DESC \
387 CFG_INI_UINT("dp_tx_ext_desc", \
388 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
389 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
390 WLAN_CFG_NUM_TX_EXT_DESC, \
391 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
392
393#define CFG_DP_TX_EXT_DESC_POOLS \
394 CFG_INI_UINT("dp_tx_ext_desc_pool", \
395 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
396 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
397 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
398 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
399
400#define CFG_DP_PDEV_RX_RING \
401 CFG_INI_UINT("dp_pdev_rx_ring", \
402 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
403 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
404 WLAN_CFG_PER_PDEV_RX_RING, \
405 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
406
407#define CFG_DP_PDEV_TX_RING \
408 CFG_INI_UINT("dp_pdev_tx_ring", \
409 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
410 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
411 WLAN_CFG_PER_PDEV_TX_RING, \
412 CFG_VALUE_OR_DEFAULT, \
413 "DP PDEV Tx Ring")
414
415#define CFG_DP_RX_DEFRAG_TIMEOUT \
416 CFG_INI_UINT("dp_rx_defrag_timeout", \
417 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
418 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
419 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
420 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
421
422#define CFG_DP_TX_COMPL_RING_SIZE \
423 CFG_INI_UINT("dp_tx_compl_ring_size", \
424 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
425 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
426 WLAN_CFG_TX_COMP_RING_SIZE, \
427 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
428
429#define CFG_DP_TX_RING_SIZE \
430 CFG_INI_UINT("dp_tx_ring_size", \
431 WLAN_CFG_TX_RING_SIZE_MIN,\
432 WLAN_CFG_TX_RING_SIZE_MAX,\
433 WLAN_CFG_TX_RING_SIZE,\
434 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
435
436#define CFG_DP_NSS_COMP_RING_SIZE \
437 CFG_INI_UINT("dp_nss_comp_ring_size", \
438 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
439 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
440 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
441 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
442
443#define CFG_DP_PDEV_LMAC_RING \
444 CFG_INI_UINT("dp_pdev_lmac_ring", \
445 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
446 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
447 WLAN_CFG_PER_PDEV_LMAC_RING, \
448 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
449
450#define CFG_DP_BASE_HW_MAC_ID \
451 CFG_INI_UINT("dp_base_hw_macid", \
452 0, 1, 1, \
453 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
454
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]455#define CFG_DP_RX_HASH \
456 CFG_INI_BOOL("dp_rx_hash", true, \
457 "DP Rx Hash")
458
459#define CFG_DP_TSO \
460 CFG_INI_BOOL("TSOEnable", false, \
461 "DP TSO Enabled")
462
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530[diff] [blame]463#define CFG_DP_LRO \
464 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
465 "DP LRO Enable")
466
467#define CFG_DP_SG \
468 CFG_INI_BOOL("dp_sg_support", false, \
469 "DP SG Enable")
470
471#define CFG_DP_GRO \
472 CFG_INI_BOOL("GROEnable", false, \
473 "DP GRO Enable")
474
475#define CFG_DP_OL_TX_CSUM \
476 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
477 "DP tx csum Enable")
478
479#define CFG_DP_OL_RX_CSUM \
480 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
481 "DP rx csum Enable")
482
483#define CFG_DP_RAWMODE \
484 CFG_INI_BOOL("dp_rawmode_support", false, \
485 "DP rawmode Enable")
486
487#define CFG_DP_PEER_FLOW_CTRL \
488 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
489 "DP peer flow ctrl Enable")
490
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]491#define CFG_DP_NAPI \
Vivek7047d0d2019-07-09 19:30:40 +0530[diff] [blame]492 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]493 "DP Napi Enabled")
494
495#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]496 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]497 "DP TCP UDP Checksum Offload")
498
499#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
500 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
501 "DP Defrag Timeout Check")
502
503#define CFG_DP_WBM_RELEASE_RING \
504 CFG_INI_UINT("dp_wbm_release_ring", \
505 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
506 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
507 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
508 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
509
510#define CFG_DP_TCL_CMD_RING \
511 CFG_INI_UINT("dp_tcl_cmd_ring", \
512 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
513 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
514 WLAN_CFG_TCL_CMD_RING_SIZE, \
515 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
516
517#define CFG_DP_TCL_STATUS_RING \
518 CFG_INI_UINT("dp_tcl_status_ring",\
519 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
520 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
521 WLAN_CFG_TCL_STATUS_RING_SIZE, \
522 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
523
524#define CFG_DP_REO_REINJECT_RING \
525 CFG_INI_UINT("dp_reo_reinject_ring", \
526 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
527 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
528 WLAN_CFG_REO_REINJECT_RING_SIZE, \
529 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
530
531#define CFG_DP_RX_RELEASE_RING \
532 CFG_INI_UINT("dp_rx_release_ring", \
533 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
534 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
535 WLAN_CFG_RX_RELEASE_RING_SIZE, \
536 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
537
538#define CFG_DP_REO_EXCEPTION_RING \
539 CFG_INI_UINT("dp_reo_exception_ring", \
540 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
541 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
542 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
543 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
544
545#define CFG_DP_REO_CMD_RING \
546 CFG_INI_UINT("dp_reo_cmd_ring", \
547 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
548 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
549 WLAN_CFG_REO_CMD_RING_SIZE, \
550 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
551
552#define CFG_DP_REO_STATUS_RING \
553 CFG_INI_UINT("dp_reo_status_ring", \
554 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
555 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
556 WLAN_CFG_REO_STATUS_RING_SIZE, \
557 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
558
559#define CFG_DP_RXDMA_BUF_RING \
560 CFG_INI_UINT("dp_rxdma_buf_ring", \
561 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
562 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
563 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
564 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
565
566#define CFG_DP_RXDMA_REFILL_RING \
567 CFG_INI_UINT("dp_rxdma_refill_ring", \
568 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
569 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
570 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
571 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
572
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame]573#define CFG_DP_TX_DESC_LIMIT_0 \
574 CFG_INI_UINT("dp_tx_desc_limit_0", \
575 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \
576 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \
577 WLAN_CFG_TX_DESC_LIMIT_0, \
578 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0")
579
580#define CFG_DP_TX_DESC_LIMIT_1 \
581 CFG_INI_UINT("dp_tx_desc_limit_1", \
582 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \
583 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \
584 WLAN_CFG_TX_DESC_LIMIT_1, \
585 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1")
586
587#define CFG_DP_TX_DESC_LIMIT_2 \
588 CFG_INI_UINT("dp_tx_desc_limit_2", \
589 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \
590 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \
591 WLAN_CFG_TX_DESC_LIMIT_2, \
592 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2")
593
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530[diff] [blame]594#define CFG_DP_TX_DEVICE_LIMIT \
595 CFG_INI_UINT("dp_tx_device_limit", \
596 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \
597 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \
598 WLAN_CFG_TX_DEVICE_LIMIT, \
599 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit")
600
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530[diff] [blame^]601#define CFG_DP_TX_SW_INTERNODE_QUEUE \
602 CFG_INI_UINT("dp_tx_sw_internode_queue", \
603 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \
604 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \
605 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \
606 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue")
607
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]608#define CFG_DP_RXDMA_MONITOR_BUF_RING \
609 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
610 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
611 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
612 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
613 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
614
615#define CFG_DP_RXDMA_MONITOR_DST_RING \
616 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
617 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
618 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
619 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
620 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
621
622#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
623 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
624 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
625 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
626 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
627 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
628
629#define CFG_DP_RXDMA_MONITOR_DESC_RING \
630 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
631 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
632 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
633 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
634 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
635
636#define CFG_DP_RXDMA_ERR_DST_RING \
637 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
638 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
639 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
640 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
641 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
642
Krunal Soni03ba0f52019-02-12 11:44:46 -0800[diff] [blame]643#define CFG_DP_PER_PKT_LOGGING \
644 CFG_INI_UINT("enable_verbose_debug", \
645 0, 0xffff, 0, \
646 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
647
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]648#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
649 CFG_INI_UINT("TxFlowStartQueueOffset", \
650 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
651 CFG_VALUE_OR_DEFAULT, "Start queue offset")
652
653#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
654 CFG_INI_UINT("TxFlowStopQueueThreshold", \
655 0, 50, 15, \
656 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
657
658#define CFG_DP_IPA_UC_TX_BUF_SIZE \
659 CFG_INI_UINT("IpaUcTxBufSize", \
660 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
661 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
662
663#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
664 CFG_INI_UINT("IpaUcTxPartitionBase", \
665 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
666 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
667
668#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
669 CFG_INI_UINT("IpaUcRxIndRingCount", \
670 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
671 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
672
673#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
674 CFG_INI_UINT("gReorderOffloadSupported", \
675 0, 1, 1, \
676 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
677
678#define CFG_DP_AP_STA_SECURITY_SEPERATION \
679 CFG_INI_BOOL("gDisableIntraBssFwd", \
680 false, "Disable intrs BSS Rx packets")
681
682#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
683 CFG_INI_BOOL("gEnableDataStallDetection", \
684 true, "Enable/Disable Data stall detection")
685
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]686#define CFG_DP \
687 CFG(CFG_DP_HTT_PACKET_TYPE) \
688 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
689 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
690 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
691 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
692 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
693 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
694 CFG(CFG_DP_MAX_ALLOC_SIZE) \
695 CFG(CFG_DP_MAX_CLIENTS) \
696 CFG(CFG_DP_MAX_PEER_ID) \
697 CFG(CFG_DP_REO_DEST_RINGS) \
698 CFG(CFG_DP_TCL_DATA_RINGS) \
699 CFG(CFG_DP_TX_DESC) \
700 CFG(CFG_DP_TX_EXT_DESC) \
701 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
702 CFG(CFG_DP_PDEV_RX_RING) \
703 CFG(CFG_DP_PDEV_TX_RING) \
704 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
705 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
706 CFG(CFG_DP_TX_RING_SIZE) \
707 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
708 CFG(CFG_DP_PDEV_LMAC_RING) \
709 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]710 CFG(CFG_DP_RX_HASH) \
711 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530[diff] [blame]712 CFG(CFG_DP_LRO) \
713 CFG(CFG_DP_SG) \
714 CFG(CFG_DP_GRO) \
715 CFG(CFG_DP_OL_TX_CSUM) \
716 CFG(CFG_DP_OL_RX_CSUM) \
717 CFG(CFG_DP_RAWMODE) \
718 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]719 CFG(CFG_DP_NAPI) \
720 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
721 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
722 CFG(CFG_DP_WBM_RELEASE_RING) \
723 CFG(CFG_DP_TCL_CMD_RING) \
724 CFG(CFG_DP_TCL_STATUS_RING) \
725 CFG(CFG_DP_REO_REINJECT_RING) \
726 CFG(CFG_DP_RX_RELEASE_RING) \
727 CFG(CFG_DP_REO_EXCEPTION_RING) \
728 CFG(CFG_DP_REO_CMD_RING) \
729 CFG(CFG_DP_REO_STATUS_RING) \
730 CFG(CFG_DP_RXDMA_BUF_RING) \
731 CFG(CFG_DP_RXDMA_REFILL_RING) \
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530[diff] [blame]732 CFG(CFG_DP_TX_DESC_LIMIT_0) \
733 CFG(CFG_DP_TX_DESC_LIMIT_1) \
734 CFG(CFG_DP_TX_DESC_LIMIT_2) \
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530[diff] [blame]735 CFG(CFG_DP_TX_DEVICE_LIMIT) \
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530[diff] [blame^]736 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]737 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
738 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
739 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
740 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]741 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800[diff] [blame]742 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530[diff] [blame]743 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
744 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
745 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
746 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
747 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
748 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
749 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
750 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
Vivek126db5d2018-07-25 22:05:04 +0530[diff] [blame]751
752#endif /* _CFG_DP_H_ */